From 9e86786a4b17ad186f456dc6ac0508a17556731b Mon Sep 17 00:00:00 2001 From: David Daney Date: Sat, 20 Sep 2008 10:16:36 -0700 Subject: MIPS: Malta: Fix include paths in malta-amon.c On linux-queue, malta doesn't build after the include file relocation. This should fix it. There some occurrences of 'asm-mips' in the comments of quite a few files, but this is the only place I found it in any code. Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/mti-malta/malta-amon.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index 96236bf3383..df9e526312a 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -22,9 +22,9 @@ #include #include -#include -#include -#include +#include +#include +#include int amon_cpu_avail(int cpu) { -- cgit v1.2.3 From 1b432840d0a4740020e29ae7a00717ef8f44954b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 31 Oct 2008 14:24:29 +0100 Subject: MIPS: RB532: GPIO register offsets are relative to GPIOBASE This patch fixes the wrong use of GPIO register offsets in devices.c. To avoid further problems, use gpio_get_value to return the NAND status instead of our own expanded code. Also define the zero offset of the alternate function register to allow consistent access. Signed-off-by: Florian Fainelli Signed-off-by: Phil Sutter Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-rc32434/rb.h | 14 ++++++++------ arch/mips/rb532/devices.c | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 79e8ef67d0d..f25a8491670 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -40,12 +40,14 @@ #define BTCS 0x010040 #define BTCOMPARE 0x010044 #define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC 0x00 +#define GPIOCFG 0x04 +#define GPIOD 0x08 +#define GPIOILEVEL 0x0C +#define GPIOISTAT 0x10 +#define GPIONMIEN 0x14 +#define IMASK6 0x38 #define LO_WPX (1 << 0) #define LO_ALE (1 << 1) #define LO_CLE (1 << 2) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 2f22d714d5b..c1c29181bd4 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = { /* Resources and device for NAND */ static int rb532_dev_ready(struct mtd_info *mtd) { - return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; + return gpio_get_value(GPIO_RDY); } static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -- cgit v1.2.3 From f43909dfb39c63ce54a598cbd7921643029afdeb Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Fri, 31 Oct 2008 19:54:11 +0200 Subject: MIPS: IP22: Make indy_sc_ops variable static The indy_sc_ops variable in arch/mips/mm/sc-ip22.c is needlessly defined global, and this patch makes it static. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- --- arch/mips/mm/sc-ip22.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index 1f602a110e1..13adb578211 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void) /* XXX Check with wje if the Indy caches can differenciate between writeback + invalidate and just invalidate. */ -struct bcache_ops indy_sc_ops = { +static struct bcache_ops indy_sc_ops = { .bc_enable = indy_sc_enable, .bc_disable = indy_sc_disable, .bc_wback_inv = indy_sc_wback_invalidate, -- cgit v1.2.3 From 2e373952cc893207a8b47a5e68c2f5155f912449 Mon Sep 17 00:00:00 2001 From: Phil Sutter Date: Sat, 1 Nov 2008 15:13:21 +0100 Subject: MIPS: RB532: Provide functions for gpio configuration As gpiolib doesn't support pin multiplexing, it provides no way to access the GPIOFUNC register. Also there is no support for setting interrupt status and level. These functions provide access to them and are needed by the CompactFlash driver. Signed-off-by: Phil Sutter Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-rc32434/gpio.h | 2 + arch/mips/rb532/gpio.c | 193 +++++++++++------------------- 2 files changed, 75 insertions(+), 120 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index c8e554eafce..b5cf6457305 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned extern unsigned get_434_reg(unsigned reg_offs); extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); +extern void rb532_gpio_set_istat(int bit, unsigned gpio); #endif /* _RC32434_GPIO_H_ */ diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 70c4a672637..0e84c8ab6a3 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -39,10 +39,6 @@ struct rb532_gpio_chip { struct gpio_chip chip; void __iomem *regbase; - void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_level)(struct gpio_chip *chip, unsigned offset); - void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_status)(struct gpio_chip *chip, unsigned offset); }; struct mpmc_device dev3; @@ -111,15 +107,47 @@ unsigned char get_latch_u5(void) } EXPORT_SYMBOL(get_latch_u5); +/* rb532_set_bit - sanely set a bit + * + * bitval: new value for the bit + * offset: bit index in the 4 byte address range + * ioaddr: 4 byte aligned address being altered + */ +static inline void rb532_set_bit(unsigned bitval, + unsigned offset, void __iomem *ioaddr) +{ + unsigned long flags; + u32 val; + + bitval = !!bitval; /* map parameter to {0,1} */ + + local_irq_save(flags); + + val = readl(ioaddr); + val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ + val |= ( bitval << offset ); /* set bit if bitval == 1 */ + writel(val, ioaddr); + + local_irq_restore(flags); +} + +/* rb532_get_bit - read a bit + * + * returns the boolean state of the bit, which may be > 1 + */ +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) +{ + return (readl(ioaddr) & (1 << offset)); +} + /* * Return GPIO level */ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) { - u32 mask = 1 << offset; struct rb532_gpio_chip *gpch; gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOD) & mask; + return rb532_get_bit(offset, gpch->regbase + GPIOD); } /* @@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) static void rb532_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpvr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpvr = gpch->regbase + GPIOD; - - local_irq_save(flags); - tmp = readl(gpvr); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpvr); - local_irq_restore(flags); + rb532_set_bit(value, offset, gpch->regbase + GPIOD); } /* @@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip, */ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - unsigned long flags; - u32 mask = 1 << offset; - u32 value; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - value = readl(gpdr); - value &= ~mask; - writel(value, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); return 0; } @@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int rb532_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - writel(mask, gpch->regbase + GPIOD); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - tmp = readl(gpdr); - tmp |= mask; - writel(tmp, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + /* set the initial output value */ + rb532_set_bit(value, offset, gpch->regbase + GPIOD); + + rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); return 0; } -/* - * Set the GPIO interrupt level - */ -static void rb532_gpio_set_int_level(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpil; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpil = gpch->regbase + GPIOILEVEL; - - local_irq_save(flags); - tmp = readl(gpil); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpil); - local_irq_restore(flags); -} +static struct rb532_gpio_chip rb532_gpio_chip[] = { + [0] = { + .chip = { + .label = "gpio0", + .direction_input = rb532_gpio_direction_input, + .direction_output = rb532_gpio_direction_output, + .get = rb532_gpio_get, + .set = rb532_gpio_set, + .base = 0, + .ngpio = 32, + }, + }, +}; /* - * Get the GPIO interrupt level + * Set GPIO interrupt level */ -static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) +void rb532_gpio_set_ilevel(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOILEVEL) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); } +EXPORT_SYMBOL(rb532_gpio_set_ilevel); /* - * Set the GPIO interrupt status + * Set GPIO interrupt status */ -static void rb532_gpio_set_int_status(struct gpio_chip *chip, - unsigned offset, int value) +void rb532_gpio_set_istat(int bit, unsigned gpio) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpis; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpis = gpch->regbase + GPIOISTAT; - - local_irq_save(flags); - tmp = readl(gpis); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpis); - local_irq_restore(flags); + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); } +EXPORT_SYMBOL(rb532_gpio_set_istat); /* - * Get the GPIO interrupt status + * Configure GPIO alternate function */ -static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) +static void rb532_gpio_set_func(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOISTAT) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } -static struct rb532_gpio_chip rb532_gpio_chip[] = { - [0] = { - .chip = { - .label = "gpio0", - .direction_input = rb532_gpio_direction_input, - .direction_output = rb532_gpio_direction_output, - .get = rb532_gpio_get, - .set = rb532_gpio_set, - .base = 0, - .ngpio = 32, - }, - .get_int_level = rb532_gpio_get_int_level, - .set_int_level = rb532_gpio_set_int_level, - .get_int_status = rb532_gpio_get_int_status, - .set_int_status = rb532_gpio_set_int_status, - }, -}; - int __init rb532_gpio_init(void) { struct resource *r; @@ -310,9 +261,11 @@ int __init rb532_gpio_init(void) return -ENXIO; } - /* Set the interrupt status and level for the CF pin */ - rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); - rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); + /* configure CF_GPIO_NUM as CFRDY IRQ source */ + rb532_gpio_set_func(0, CF_GPIO_NUM); + rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); + rb532_gpio_set_ilevel(1, CF_GPIO_NUM); + rb532_gpio_set_istat(0, CF_GPIO_NUM); return 0; } -- cgit v1.2.3 From 664c4bbb73ec53e4f81f7d80a09571b49bad1f96 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 3 Nov 2008 11:31:54 +0000 Subject: MIPS: csrc-r4k: Fix spelling mistake. Signed-off-by: Ralf Baechle --- arch/mips/kernel/csrc-r4k.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 86e026f067b..74fb74583b4 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -27,7 +27,7 @@ int __init init_mips_clocksource(void) if (!cpu_has_counter || !mips_hpt_frequency) return -ENXIO; - /* Calclate a somewhat reasonable rating value */ + /* Calculate a somewhat reasonable rating value */ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); -- cgit v1.2.3 From a24e849c019f15796984be9fe301fa9ead6f0f9e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 3 Nov 2008 11:32:34 +0000 Subject: MIPS: csrc-r4k: Fix declaration depending on the wrong CONFIG_ symbol. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/time.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index d3bd5c5aa2e..9601ea95054 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_CSRC_R4K extern int init_mips_clocksource(void); #else static inline int init_mips_clocksource(void) -- cgit v1.2.3 From 8ec2e24356e63dc298c6040557faf396410907ac Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 20 Nov 2008 17:26:36 -0800 Subject: MIPS: Make BUG() __noreturn. Often we do things like put BUG() in the default clause of a case statement. Since it was not declared __noreturn, this could sometimes lead to bogus compiler warnings that variables were used uninitialized. There is a small problem in that we have to put a magic while(1); loop to fool GCC into really thinking it is noreturn. This makes the new BUG() function 3 instructions long instead of just 1, but I think it is worth it as it is now unnecessary to do extra work to silence the 'used uninitialized' warnings. I also re-wrote BUG_ON so that if it is given a constant condition, it just does BUG() instead of loading a constant value in to a register and testing it. Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bug.h | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 7eb63de808b..08ea46863fe 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -7,20 +7,31 @@ #include -#define BUG() \ -do { \ - __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ -} while (0) +static inline void __noreturn BUG(void) +{ + __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); + /* Fool GCC into thinking the function doesn't return. */ + while (1) + ; +} #define HAVE_ARCH_BUG #if (_MIPS_ISA > _MIPS_ISA_MIPS1) -#define BUG_ON(condition) \ -do { \ - __asm__ __volatile__("tne $0, %0, %1" \ - : : "r" (condition), "i" (BRK_BUG)); \ -} while (0) +static inline void __BUG_ON(unsigned long condition) +{ + if (__builtin_constant_p(condition)) { + if (condition) + BUG(); + else + return; + } + __asm__ __volatile__("tne $0, %0, %1" + : : "r" (condition), "i" (BRK_BUG)); +} + +#define BUG_ON(C) __BUG_ON((unsigned long)(C)) #define HAVE_ARCH_BUG_ON -- cgit v1.2.3 From 96b8936a9ed08746e47081458a5eb9e43a751e24 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 25 Nov 2008 08:10:03 +0100 Subject: remove __ARCH_WANT_COMPAT_SYS_PTRACE All architectures now use the generic compat_sys_ptrace, as should every new architecture that needs 32bit compat (if we'll ever get another). Remove the now superflous __ARCH_WANT_COMPAT_SYS_PTRACE define, and also kill a comment about __ARCH_SYS_PTRACE that was added after __ARCH_SYS_PTRACE was already gone. Signed-off-by: Christoph Hellwig Acked-by: David S. Miller Signed-off-by: Linus Torvalds --- arch/mips/include/asm/ptrace.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 813abd16255..c2c8bac4330 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -9,10 +9,6 @@ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -#ifdef CONFIG_64BIT -#define __ARCH_WANT_COMPAT_SYS_PTRACE -#endif - /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 -- cgit v1.2.3