From 036f290d8952fdcafa9d6c9e2d94efbcb793d123 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 26 Jan 2010 05:56:30 +0000 Subject: powerpc/44x: Add MTD support (NOR FLASH) to Katmai dts This patch adds NOR FLASH MTD support to the Katmai (440SPe) dts file. For this the OPB ranges address is mapped differently (base 0x00000000 -> 0xe0000000). This results in the address being identical to the lower 32bit of its physical address. This is needed for the MTD mapping to work correctly, since U-Boot will insert the physical addresses of the EBC chip selects into the EBC ranges property. This is the way its done in most other 4xx dts files as well. Additionally with a small whitespace cleanup. Signed-off-by: Stefan Roese Cc: Josh Boyer Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/katmai.dts | 71 +++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 19 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index 8f345de960c..8cf2c0c88c0 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -156,7 +156,7 @@ compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>; + ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { @@ -165,14 +165,47 @@ #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ + /* ranges property is supplied by U-Boot */ interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x01000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "user"; + reg = <0x00400000 0x00b60000>; + }; + partition@f60000 { + label = "env"; + reg = <0x00f60000 0x00040000>; + }; + partition@fa0000 { + label = "u-boot"; + reg = <0x00fa0000 0x00060000>; + }; + }; }; - UART0: serial@10000200 { + UART0: serial@f0000200 { device_type = "serial"; compatible = "ns16550"; - reg = <0x10000200 0x00000008>; + reg = <0xf0000200 0x00000008>; virtual-reg = <0xa0000200>; clock-frequency = <0>; /* Filled in by zImage */ current-speed = <115200>; @@ -180,10 +213,10 @@ interrupts = <0x0 0x4>; }; - UART1: serial@10000300 { + UART1: serial@f0000300 { device_type = "serial"; compatible = "ns16550"; - reg = <0x10000300 0x00000008>; + reg = <0xf0000300 0x00000008>; virtual-reg = <0xa0000300>; clock-frequency = <0>; current-speed = <0>; @@ -192,10 +225,10 @@ }; - UART2: serial@10000600 { + UART2: serial@f0000600 { device_type = "serial"; compatible = "ns16550"; - reg = <0x10000600 0x00000008>; + reg = <0xf0000600 0x00000008>; virtual-reg = <0xa0000600>; clock-frequency = <0>; current-speed = <0>; @@ -203,27 +236,27 @@ interrupts = <0x5 0x4>; }; - IIC0: i2c@10000400 { + IIC0: i2c@f0000400 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <0x10000400 0x00000014>; + reg = <0xf0000400 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x2 0x4>; }; - IIC1: i2c@10000500 { + IIC1: i2c@f0000500 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <0x10000500 0x00000014>; + reg = <0xf0000500 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x3 0x4>; }; - EMAC0: ethernet@10000800 { + EMAC0: ethernet@f0000800 { linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-440spe", "ibm,emac4"; interrupt-parent = <&UIC1>; interrupts = <0x1c 0x4 0x1d 0x4>; - reg = <0x10000800 0x00000074>; + reg = <0xf0000800 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -248,11 +281,11 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ - 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ - 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ - 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ - 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed @@ -453,6 +486,6 @@ }; chosen { - linux,stdout-path = "/plb/opb/serial@10000200"; + linux,stdout-path = "/plb/opb/serial@f0000200"; }; }; -- cgit v1.2.3 From 6f57518cfa097b170a8f500d6d70651e81589e30 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 9 Feb 2010 23:08:34 +0000 Subject: powerpc/44x: Update Arches dts Sync Arches dts with latest Canyonlands version: - Add 16k FIFO size to supported EMAC nodes - Add next-level-cache property - Add Crypto device node Signed-off-by: Stefan Roese Cc: Josh Boyer Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/arches.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts index 414ef8b7e57..30f41204acf 100644 --- a/arch/powerpc/boot/dts/arches.dts +++ b/arch/powerpc/boot/dts/arches.dts @@ -60,6 +60,7 @@ d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; + next-level-cache = <&L2C0>; }; }; @@ -146,6 +147,13 @@ dcr-reg = <0x010 0x002>; }; + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + MAL0: mcmal { compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; dcr-reg = <0x180 0x062>; @@ -274,6 +282,7 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; phy-mode = "sgmii"; phy-map = <0xffffffff>; gpcs-address = <0x0000000a>; @@ -302,6 +311,7 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; phy-mode = "sgmii"; phy-map = <0x00000000>; gpcs-address = <0x0000000b>; @@ -331,6 +341,8 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ phy-mode = "sgmii"; phy-map = <0x00000001>; gpcs-address = <0x0000000C>; -- cgit v1.2.3 From 5a6543e8da6e338fef3cd42cc79ac85f6f53a8e7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 9 Feb 2010 23:08:28 +0000 Subject: powerpc/44x: Update Glacier dts Sync Glacier dts with latest Canyonlands version: - Add l2 cache support - Add NDFC support - Add RTC support - Add AD7414 hwmon support - Change EMAC compatible node from emac4 to emac4sync and correct the register size - Add support for ISA holes on 4xx PCI/X/E (as done in Benjamin Herrenschmidt's patch for Canyonlands) - Add Crypto device node Signed-off-by: Stefan Roese Cc: Josh Boyer Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/glacier.dts | 76 ++++++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 9 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts index f6f61893929..d62a4fb6f93 100644 --- a/arch/powerpc/boot/dts/glacier.dts +++ b/arch/powerpc/boot/dts/glacier.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for AMCC Glacier (460GT) * - * Copyright 2008 DENX Software Engineering, Stefan Roese + * Copyright 2008-2010 DENX Software Engineering, Stefan Roese * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without @@ -42,6 +42,7 @@ d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; + next-level-cache = <&L2C0>; }; }; @@ -106,6 +107,16 @@ dcr-reg = <0x00c 0x002>; }; + L2C0: l2c { + compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + plb { compatible = "ibm,plb-460gt", "ibm,plb4"; #address-cells = <2>; @@ -118,6 +129,13 @@ dcr-reg = <0x010 0x002>; }; + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + MAL0: mcmal { compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; dcr-reg = <0x180 0x062>; @@ -186,6 +204,29 @@ reg = <0x03fa0000 0x00060000>; }; }; + + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@100000 { + label = "user"; + reg = <0x00000000 0x03f00000>; + }; + }; + }; }; UART0: serial@ef600300 { @@ -237,6 +278,20 @@ reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC2>; + interrupts = <0x19 0x8>; + }; + sttm@48 { + compatible = "ad,ad7414"; + reg = <0x48>; + interrupt-parent = <&UIC1>; + interrupts = <0x14 0x8>; + }; }; IIC1: i2c@ef600800 { @@ -275,7 +330,7 @@ EMAC0: ethernet@ef600e00 { device_type = "network"; - compatible = "ibm,emac-460gt", "ibm,emac4"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -283,7 +338,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600e00 0x00000074>; + reg = <0xef600e00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -305,7 +360,7 @@ EMAC1: ethernet@ef600f00 { device_type = "network"; - compatible = "ibm,emac-460gt", "ibm,emac4"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; interrupt-parent = <&EMAC1>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -313,7 +368,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600f00 0x00000074>; + reg = <0xef600f00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; @@ -336,7 +391,7 @@ EMAC2: ethernet@ef601100 { device_type = "network"; - compatible = "ibm,emac-460gt", "ibm,emac4"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; interrupt-parent = <&EMAC2>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -344,7 +399,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef601100 0x00000074>; + reg = <0xef601100 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <2>; @@ -366,7 +421,7 @@ EMAC3: ethernet@ef601200 { device_type = "network"; - compatible = "ibm,emac-460gt", "ibm,emac4"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; interrupt-parent = <&EMAC3>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -374,7 +429,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef601200 0x00000074>; + reg = <0xef601200 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <3>; @@ -414,6 +469,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ @@ -444,6 +500,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ @@ -485,6 +542,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ -- cgit v1.2.3 From dcc79d7870cfc3b3f11137e040e743dc50f88acf Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 16 Feb 2010 11:12:04 -0700 Subject: powerpc/mpc5121: update mpc5121ads DTS Collects several changes needed after applying previous mpc5121 platform and driver patches: - Add mpc5121 reset module node - Clean up and fix NAND description, remove unused properties here and correct NAND flash chip size. - Clean up I2C nodes: remove obsolete "cell-index" properties, add "fsl,preserve-clocking" property - Add I2C RTC node for m41t61 RTC - Add I2C nodes for AD7414 temperature sensor and AT24C32CD3 EEPROM - Fix compatible property in DMA node - Clean up CAN nodes, remove unused "cell-index" properties - Fix compatible property in DIU node - USB node changes: - use "fsl,mpc5121-usb2-dr" compatible property only - remove "port0" and "port1" properties as these are only used for multi-port host(MHP) module which is not available on MPC5121. - use 'fsl,invert-drvvbus' and 'fsl,invert-pwr-fault' in USB node for internal PHY to specify polarities of the appropriate port pins. Signed-off-by: Piotr Ziecik Signed-off-by: Wolfgang Denk Signed-off-by: Detlev Zundel Signed-off-by: Anatolij Gustschin Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/mpc5121ads.dts | 55 +++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 22 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts index c353dac3341..d2b2db7cb4a 100644 --- a/arch/powerpc/boot/dts/mpc5121ads.dts +++ b/arch/powerpc/boot/dts/mpc5121ads.dts @@ -62,17 +62,12 @@ interrupt-parent = < &ipic >; #address-cells = <1>; #size-cells = <1>; - bank-width = <1>; // ADS has two Hynix 512MB Nand flash chips in a single - // stacked package . + // stacked package. chips = <2>; - nand0@0 { - label = "nand0"; - reg = <0x00000000 0x02000000>; // first 32 MB of chip 0 - }; - nand1@20000000 { - label = "nand1"; - reg = <0x20000000 0x02000000>; // first 32 MB of chip 1 + nand@0 { + label = "nand"; + reg = <0x00000000 0x40000000>; // 512MB + 512MB }; }; @@ -166,6 +161,11 @@ interrupt-parent = < &ipic >; }; + reset@e00 { // Reset module + compatible = "fsl,mpc5121-reset"; + reg = <0xe00 0x100>; + }; + clock@f00 { // Clock control compatible = "fsl,mpc5121-clock"; reg = <0xf00 0x100>; @@ -185,17 +185,15 @@ interrupt-parent = < &ipic >; }; - mscan@1300 { + can@1300 { compatible = "fsl,mpc5121-mscan"; - cell-index = <0>; interrupts = <12 0x8>; interrupt-parent = < &ipic >; reg = <0x1300 0x80>; }; - mscan@1380 { + can@1380 { compatible = "fsl,mpc5121-mscan"; - cell-index = <1>; interrupts = <13 0x8>; interrupt-parent = < &ipic >; reg = <0x1380 0x80>; @@ -205,17 +203,31 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5121-i2c", "fsl-i2c"; - cell-index = <0>; reg = <0x1700 0x20>; interrupts = <9 0x8>; interrupt-parent = < &ipic >; + fsl,preserve-clocking; + + hwmon@4a { + compatible = "adi,ad7414"; + reg = <0x4a>; + }; + + eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; + + rtc@68 { + compatible = "stm,m41t62"; + reg = <0x68>; + }; }; i2c@1720 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5121-i2c", "fsl-i2c"; - cell-index = <1>; reg = <0x1720 0x20>; interrupts = <10 0x8>; interrupt-parent = < &ipic >; @@ -225,7 +237,6 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5121-i2c", "fsl-i2c"; - cell-index = <2>; reg = <0x1740 0x20>; interrupts = <11 0x8>; interrupt-parent = < &ipic >; @@ -244,7 +255,7 @@ }; display@2100 { - compatible = "fsl,mpc5121-diu", "fsl-diu"; + compatible = "fsl,mpc5121-diu", "fsl,diu"; reg = <0x2100 0x100>; interrupts = <64 0x8>; interrupt-parent = < &ipic >; @@ -277,7 +288,7 @@ // USB1 using external ULPI PHY //usb@3000 { - // compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; + // compatible = "fsl,mpc5121-usb2-dr"; // reg = <0x3000 0x1000>; // #address-cells = <1>; // #size-cells = <0>; @@ -285,12 +296,11 @@ // interrupts = <43 0x8>; // dr_mode = "otg"; // phy_type = "ulpi"; - // port1; //}; // USB0 using internal UTMI PHY usb@4000 { - compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; + compatible = "fsl,mpc5121-usb2-dr"; reg = <0x4000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -298,7 +308,8 @@ interrupts = <44 0x8>; dr_mode = "otg"; phy_type = "utmi_wide"; - port0; + fsl,invert-drvvbus; + fsl,invert-pwr-fault; }; // IO control @@ -365,7 +376,7 @@ }; dma@14000 { - compatible = "fsl,mpc5121-dma2"; + compatible = "fsl,mpc5121-dma"; reg = <0x14000 0x1800>; interrupts = <65 0x8>; interrupt-parent = < &ipic >; -- cgit v1.2.3 From d24720a45ad2928f687c6371482cdfba19b74fc5 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 17 Feb 2010 07:33:22 -0700 Subject: powerpc/mpc5121: correct DIU compatible property The DIU driver should bind against "fsl,mpc5121-diu" directly. Add this compatible property to the match table and fix DTS and platform code accordingly. Signed-off-by: Anatolij Gustschin Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/mpc5121ads.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts index d2b2db7cb4a..c9ef6bbe26c 100644 --- a/arch/powerpc/boot/dts/mpc5121ads.dts +++ b/arch/powerpc/boot/dts/mpc5121ads.dts @@ -255,7 +255,7 @@ }; display@2100 { - compatible = "fsl,mpc5121-diu", "fsl,diu"; + compatible = "fsl,mpc5121-diu"; reg = <0x2100 0x100>; interrupts = <64 0x8>; interrupt-parent = < &ipic >; -- cgit v1.2.3 From f5d570d32c836c108c4e64c285d5bdb75cc6a737 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 11 Jan 2010 12:23:12 +0000 Subject: powerpc/86xx: Add MSI section to GE SBC310 DTS Add the MSI section to the DTS file for the GE SBC310. Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_sbc310.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 820c2b355ab..8ea8d4ad270 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts @@ -338,6 +338,22 @@ device_type = "open-pic"; }; + msi@41600 { + compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; -- cgit v1.2.3 From 9b952a3970c75bd0b46f73976b3613b3c68476f4 Mon Sep 17 00:00:00 2001 From: Malcolm Crossley Date: Mon, 11 Jan 2010 12:23:18 +0000 Subject: powerpc/86xx: Fix GE SBC310 XMC site support Correction to interrupt map mask for GE SBC310 XMC site and addition of alias. Signed-off-by: Malcolm Crossley Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_sbc310.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 8ea8d4ad270..8e4efff3bda 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts @@ -32,6 +32,7 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; }; cpus { @@ -374,7 +375,7 @@ clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <0x18 0x2>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; interrupt-map = < 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 -- cgit v1.2.3 From 6459ba984a57e90326b3eaf7a35cc2f3fffe26a0 Mon Sep 17 00:00:00 2001 From: Malcolm Crossley Date: Mon, 11 Jan 2010 12:23:24 +0000 Subject: powerpc/86xx: Add MSI section to GE SBC610 DTS Add the MSI section to the DTS file for the GE SBC610. Signed-off-by: Malcolm Crossley Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_sbc610.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 30911adefc8..78c336f0fcb 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -305,6 +305,22 @@ device_type = "open-pic"; }; + msi@41600 { + compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; -- cgit v1.2.3 From ae1f7553b9c9ac3762dc91ecb92574bb9fac0b1e Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 11 Jan 2010 12:23:31 +0000 Subject: powerpc/86xx: Basic flash support for GE SBC610 Support for the SBC610 VPX Single Board Computer from GE (PowerPC MPC8641D). This patch adds basic support for the on-board flash. Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_sbc610.dts | 50 ++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 8 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 78c336f0fcb..bb7060078fb 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -75,14 +75,48 @@ interrupts = <19 2>; interrupt-parent = <&mpic>; - ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash - 1 0 0xe8000000 0x08000000 // Paged Flash 0 - 2 0 0xe0000000 0x08000000 // Paged Flash 1 - 3 0 0xfc100000 0x00020000 // NVRAM - 4 0 0xfc000000 0x00008000 // FPGA - 5 0 0xfc008000 0x00008000 // AFIX FPGA - 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) - 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) + ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash + 1 0 0xe8000000 0x08000000 // Paged Flash 0 + 2 0 0xe0000000 0x08000000 // Paged Flash 1 + 3 0 0xfc100000 0x00020000 // NVRAM + 4 0 0xfc000000 0x00008000 // FPGA + 5 0 0xfc008000 0x00008000 // AFIX FPGA + 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) + 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) + + /* flash@0,0 is a mirror of part of the memory in flash@1,0 + flash@0,0 { + compatible = "gef,sbc610-firmware-mirror", "cfi-flash"; + reg = <0x0 0x0 0x1000000>; + bank-width = <4>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "firmware"; + reg = <0x0 0x1000000>; + read-only; + }; + }; + */ + + flash@1,0 { + compatible = "gef,sbc610-paged-flash", "cfi-flash"; + reg = <0x1 0x0 0x8000000>; + bank-width = <4>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "user"; + reg = <0x0 0x7800000>; + }; + partition@7800000 { + label = "firmware"; + reg = <0x7800000 0x800000>; + read-only; + }; + }; nvram@3,0 { device_type = "nvram"; -- cgit v1.2.3 From 41cbdeef37b6614f6bac4e3953dd2c7208bbe1d0 Mon Sep 17 00:00:00 2001 From: Malcolm Crossley Date: Mon, 11 Jan 2010 12:23:44 +0000 Subject: powerpc/86xx: Add MSI section to GE PPC9A DTS Add the MSI section to the DTS file for the GE PPC9A. Signed-off-by: Malcolm Crossley Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_ppc9a.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index c86114e93f1..977f260d5e6 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -341,6 +341,22 @@ device_type = "open-pic"; }; + msi@41600 { + compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; -- cgit v1.2.3 From e98efaf303ccbff11522a054d155593d7f2bb41f Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Sat, 6 Feb 2010 00:06:26 +0300 Subject: powerpc/85xx: Add NOR, LEDs and PIB support for MPC8568E-MDS boards This patch adds NOR Flash, LEDs and PIB support for MPC8568E-MDS boards. Plus, move bcsr node into localbus node, and add bcsr5 gpio-controller node. Some platform code modifications were also needed. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8568mds.dts | 65 ++++++++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 6d892ba74e5..92fb17876e7 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -54,9 +54,52 @@ reg = <0x0 0x10000000>; }; - bcsr@f8000000 { - compatible = "fsl,mpc8568mds-bcsr"; - reg = <0xf8000000 0x8000>; + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", + "simple-bus"; + reg = <0xe0005000 0x1000>; + + ranges = <0x0 0x0 0xfe000000 0x02000000 + 0x1 0x0 0xf8000000 0x00008000 + 0x2 0x0 0xf0000000 0x04000000 + 0x4 0x0 0xf8008000 0x00008000 + 0x5 0x0 0xf8010000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x02000000>; + bank-width = <2>; + device-width = <2>; + }; + + bcsr@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8568mds-bcsr"; + reg = <1 0 0x8000>; + ranges = <0 1 0 0x8000>; + + bcsr5: gpio-controller@11 { + #gpio-cells = <2>; + compatible = "fsl,mpc8568mds-bcsr-gpio"; + reg = <0x5 0x1>; + gpio-controller; + }; + }; + + pib@4,0 { + compatible = "fsl,mpc8568mds-pib"; + reg = <4 0 0x8000>; + }; + + pib@5,0 { + compatible = "fsl,mpc8568mds-pib"; + reg = <5 0 0x8000>; + }; }; soc8568@e0000000 { @@ -610,4 +653,20 @@ sleep = <&pmc 0x00080000 /* controller */ &pmc 0x00040000>; /* message unit */ }; + + leds { + compatible = "gpio-leds"; + + green { + gpios = <&bcsr5 1 0>; + }; + + amber { + gpios = <&bcsr5 2 0>; + }; + + red { + gpios = <&bcsr5 3 0>; + }; + }; }; -- cgit v1.2.3