From fbcc4bacee30cad4e4a13d05492a9ed0c9c3e8c7 Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Thu, 4 Sep 2008 04:08:20 +0000 Subject: ibm_newemac: MAL support for PowerPC 405EZ The PowerPC 405EZ SoC has some differences in the interrupt layout and handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into a single interrupt. Also, due to the possibility for interrupt coalescing, the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in the ICINTSTAT SDR. This sets the proper MAL feature bits for 405EZ boards, and adds a common shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR are added to the proper header file as well. This has been adapted from code originally written by Stefan Roese. Signed-off-by: Josh Boyer Acked-by: Benjamin Herrenschmidt Acked-by: Jeff Garzik Signed-off-by: Josh Boyer --- arch/powerpc/include/asm/dcr-regs.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/powerpc/include/asm/dcr-regs.h') diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 29b0ecef980..7b833ff9c14 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -68,6 +68,13 @@ #define SDR0_UART3 0x0123 #define SDR0_CUST0 0x4000 +/* SDR for 405EZ */ +#define DCRN_SDR_ICINTSTAT 0x4510 +#define ICINTSTAT_ICRX 0x80000000 +#define ICINTSTAT_ICTX0 0x40000000 +#define ICINTSTAT_ICTX1 0x20000000 +#define ICINTSTAT_ICTX 0x60000000 + /* * All those DCR register addresses are offsets from the base address * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is -- cgit v1.2.3 From 9e3cb29497561c846d0e7efc445731764d93c749 Mon Sep 17 00:00:00 2001 From: Victor Gallardo Date: Wed, 1 Oct 2008 23:37:57 -0700 Subject: ibm_newemac: Add support for GPCS, SGMII and M88E1112 PHY Add support for the phy types found on the Arches and other PowerPC 460 based boards. Signed-off-by: Victor Gallardo Acked-by: Benjamin Herrenschmidt Acked-by: Jeff Garzik Signed-off-by: Josh Boyer --- arch/powerpc/include/asm/dcr-regs.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/include/asm/dcr-regs.h') diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 7b833ff9c14..828e3aa1f2f 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -75,6 +75,10 @@ #define ICINTSTAT_ICTX1 0x20000000 #define ICINTSTAT_ICTX 0x60000000 +/* SDRs (460EX/460GT) */ +#define SDR0_ETH_CFG 0x4103 +#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ + /* * All those DCR register addresses are offsets from the base address * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is -- cgit v1.2.3