From 3a4295d101d9654ca909b64c786f9da6ca1bf37a Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Fri, 14 Mar 2008 16:47:39 +1100 Subject: [POWERPC] Fix cell IOMMU code to cope with empty dma-ranges and non-PCI devices The cell IOMMU code to parse the dma-ranges properties, used for the fixed mapping, was broken in two ways for some devices. Firstly it didn't cope with empty dma-ranges properties. An empty property implies no translation so can be safely skipped. The code also wrongly assumed it would be looking at PCI devices, and hard coded the number of address and size cells. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/cell/iommu.c | 41 ++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 16 deletions(-) (limited to 'arch/powerpc/platforms/cell') diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c index 20ea0e118f2..d75ccded7f1 100644 --- a/arch/powerpc/platforms/cell/iommu.c +++ b/arch/powerpc/platforms/cell/iommu.c @@ -802,17 +802,24 @@ static int __init cell_iommu_init_disabled(void) static u64 cell_iommu_get_fixed_address(struct device *dev) { - u64 cpu_addr, size, best_size, pci_addr = OF_BAD_ADDR; + u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR; struct device_node *np; const u32 *ranges = NULL; - int i, len, best; + int i, len, best, naddr, nsize, pna, range_size; np = of_node_get(dev->archdata.of_node); - while (np) { + while (1) { + naddr = of_n_addr_cells(np); + nsize = of_n_size_cells(np); + np = of_get_next_parent(np); + if (!np) + break; + ranges = of_get_property(np, "dma-ranges", &len); - if (ranges) + + /* Ignore empty ranges, they imply no translation required */ + if (ranges && len > 0) break; - np = of_get_next_parent(np); } if (!ranges) { @@ -822,15 +829,17 @@ static u64 cell_iommu_get_fixed_address(struct device *dev) len /= sizeof(u32); + pna = of_n_addr_cells(np); + range_size = naddr + nsize + pna; + /* dma-ranges format: - * 1 cell: pci space - * 2 cells: pci address - * 2 cells: parent address - * 2 cells: size + * child addr : naddr cells + * parent addr : pna cells + * size : nsize cells */ - for (i = 0, best = -1, best_size = 0; i < len; i += 7) { - cpu_addr = of_translate_dma_address(np, ranges +i + 3); - size = of_read_number(ranges + i + 5, 2); + for (i = 0, best = -1, best_size = 0; i < len; i += range_size) { + cpu_addr = of_translate_dma_address(np, ranges + i + naddr); + size = of_read_number(ranges + i + naddr + pna, nsize); if (cpu_addr == 0 && size > best_size) { best = i; @@ -838,15 +847,15 @@ static u64 cell_iommu_get_fixed_address(struct device *dev) } } - if (best >= 0) - pci_addr = of_read_number(ranges + best + 1, 2); - else + if (best >= 0) { + dev_addr = of_read_number(ranges + best, naddr); + } else dev_dbg(dev, "iommu: no suitable range found!\n"); out: of_node_put(np); - return pci_addr; + return dev_addr; } static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) -- cgit v1.2.3 From ebf3a6509299e46c531f88ee727372bd95cf542a Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Wed, 19 Mar 2008 17:10:55 +1100 Subject: [POWERPC] Hide resources on Axon PCIE root complex nodes The PCI bridge representing the PCIE root complex on Axon, contains device BARs for a memory range and ROM that define inbound accesses. This confuses the kernel resource management code -- the resources need to be hidden when Axon is a host bridge. Signed-off-by: Michael Ellerman Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/cell/setup.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/powerpc/platforms/cell') diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index dda34650cb0..5c531e8f9f6 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c @@ -81,6 +81,42 @@ static void cell_progress(char *s, unsigned short hex) printk("*** %04x : %s\n", hex, s ? s : ""); } +static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev) +{ + struct pci_controller *hose; + const char *s; + int i; + + if (!machine_is(cell)) + return; + + /* We're searching for a direct child of the PHB */ + if (dev->bus->self != NULL || dev->devfn != 0) + return; + + hose = pci_bus_to_host(dev->bus); + if (hose == NULL) + return; + + /* Only on PCIE */ + if (!of_device_is_compatible(hose->dn, "pciex")) + return; + + /* And only on axon */ + s = of_get_property(hose->dn, "model", NULL); + if (!s || strcmp(s, "Axon") != 0) + return; + + for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { + dev->resource[i].start = dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + + printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n", + pci_name(dev)); +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex); + static int __init cell_publish_devices(void) { int node; -- cgit v1.2.3