From c9cf73aee140baa425429902aaed2c758401343f Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Sun, 31 Jul 2005 22:34:52 -0700 Subject: [PATCH] ppc32: add 440ep support Add PPC440EP core support. PPC440EP is a PPC440-based SoC with a classic PPC FPU and another set of peripherals. Signed-off-by: Wade Farnsworth Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 50936cda0af..8a3d74f2531 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -852,6 +852,26 @@ struct cpu_spec cpu_specs[] = { #endif /* CONFIG_40x */ #ifdef CONFIG_44x + { + .pvr_mask = 0xf0000fff, + .pvr_value = 0x40000850, + .cpu_name = "440EP Rev. A", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */ + .icache_bsize = 32, + .dcache_bsize = 32, + }, + { + .pvr_mask = 0xf0000fff, + .pvr_value = 0x400008d3, + .cpu_name = "440EP Rev. B", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */ + .icache_bsize = 32, + .dcache_bsize = 32, + }, { /* 440GP Rev. B */ .pvr_mask = 0xf0000fff, .pvr_value = 0x40000440, -- cgit v1.2.3