From b4367e7451f19a3ae8b453e8b7ac0a1fdd9bca04 Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:12:32 -0700 Subject: [PATCH] powerpc: Move xparameters.h into xilinx virtex device specific path xparameters should not be needed by anything but virtex platform code. Move it from include/asm-ppc/ to platforms/4xx/xparameters/ This is preparing for work to remove xparameters from the dependancy tree for most c files. xparam changes should not cause a recompile of the world. Instead, drivers should get device info from the platform bus (populated by the boot code) Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/virtex-ii_pro.h | 2 +- arch/ppc/platforms/4xx/xparameters/xparameters.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 arch/ppc/platforms/4xx/xparameters/xparameters.h (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h index 9014c488733..026130c8e72 100644 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.h +++ b/arch/ppc/platforms/4xx/virtex-ii_pro.h @@ -16,7 +16,7 @@ #define __ASM_VIRTEXIIPRO_H__ #include -#include +#include /* serial defines */ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h new file mode 100644 index 00000000000..fe4eac62913 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -0,0 +1,18 @@ +/* + * include/asm-ppc/xparameters.h + * + * This file includes the correct xparameters.h for the CONFIG'ed board + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#include + +#if defined(CONFIG_XILINX_ML300) +#include +#endif -- cgit v1.2.3 From 562e7370a4d59d7ee8988fb0e13707d1f01a046a Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:12:40 -0700 Subject: [PATCH] powerpc: Make Virtex-II Pro support generic for all Virtex devices The PPC405 hard core is used in both the Virtex-II Pro and Virtex 4 FX FPGAs. This patch cleans up the Virtex naming convention to reflect more than just the Virtex-II Pro. Rename files virtex-ii_pro.[ch] to virtex.[ch] Rename config value VIRTEX_II_PRO to XILINX_VIRTEX Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/Kconfig | 7 ++- arch/ppc/platforms/4xx/Makefile | 2 +- arch/ppc/platforms/4xx/virtex-ii_pro.c | 60 --------------------- arch/ppc/platforms/4xx/virtex-ii_pro.h | 99 ---------------------------------- arch/ppc/platforms/4xx/virtex.c | 60 +++++++++++++++++++++ arch/ppc/platforms/4xx/virtex.h | 99 ++++++++++++++++++++++++++++++++++ arch/ppc/platforms/4xx/xilinx_ml300.c | 2 +- arch/ppc/platforms/4xx/xilinx_ml300.h | 2 +- 8 files changed, 168 insertions(+), 163 deletions(-) delete mode 100644 arch/ppc/platforms/4xx/virtex-ii_pro.c delete mode 100644 arch/ppc/platforms/4xx/virtex-ii_pro.h create mode 100644 arch/ppc/platforms/4xx/virtex.c create mode 100644 arch/ppc/platforms/4xx/virtex.h (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index d8837911bbc..203abab32cc 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -208,11 +208,16 @@ config 405GPR depends on SYCAMORE default y -config VIRTEX_II_PRO +config XILINX_VIRTEX_II_PRO bool depends on XILINX_ML300 default y +config XILINX_VIRTEX + bool + depends on XILINX_VIRTEX_II_PRO + default y + config STB03xxx bool depends on REDWOOD_5 || REDWOOD_6 diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index c9bb6117095..be4163c8afe 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -26,4 +26,4 @@ obj-$(CONFIG_440SP) += ibm440sp.o obj-$(CONFIG_440SPE) += ppc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o -obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o +obj-$(CONFIG_XILINX_VIRTEX) += virtex.o diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c deleted file mode 100644 index 097cc9d5aca..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.c - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include "virtex-ii_pro.h" - -/* Have OCP take care of the serial ports. */ -struct ocp_def core_ocp[] = { -#ifdef XPAR_UARTNS550_0_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = XPAR_UARTNS550_0_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_1_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = XPAR_UARTNS550_1_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_2_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = XPAR_UARTNS550_2_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_3_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 3, - .paddr = XPAR_UARTNS550_3_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_4_BASEADDR -#error Edit this file to add more devices. -#endif /* 4 */ -#endif /* 3 */ -#endif /* 2 */ -#endif /* 1 */ -#endif /* 0 */ - { .vendor = OCP_VENDOR_INVALID - } -}; diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h deleted file mode 100644 index 026130c8e72..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.h - * - * Include file that defines the Xilinx Virtex-II Pro processor - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_VIRTEXIIPRO_H__ -#define __ASM_VIRTEXIIPRO_H__ - -#include -#include - -/* serial defines */ - -#define RS_TABLE_SIZE 4 /* change this and add more devices below - if you have more then 4 16x50 UARTs */ - -#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16) - -/* The serial ports in the Virtex-II Pro have each I/O byte in the - * LSByte of a word. This means that iomem_reg_shift needs to be 2 to - * change the byte offsets into word offsets. In addition the base - * addresses need to have 3 added to them to get to the LSByte. - */ -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ - ASYNC_BOOT_AUTOCONF, \ - .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM}, - -#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define ML300_UART0 STD_UART_OP(0) -#else -#define ML300_UART0 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define ML300_UART1 STD_UART_OP(1) -#else -#define ML300_UART1 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define ML300_UART2 STD_UART_OP(2) -#else -#define ML300_UART2 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define ML300_UART3 STD_UART_OP(3) -#else -#define ML300_UART3 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID) -#error Edit this file to add more devices. -#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define NR_SER_PORTS 4 -#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define NR_SER_PORTS 3 -#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define NR_SER_PORTS 2 -#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define NR_SER_PORTS 1 -#else -#define NR_SER_PORTS 0 -#endif - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_PORT_DFNS \ - ML300_UART0 \ - ML300_UART1 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_PORT_DFNS \ - ML300_UART1 \ - ML300_UART0 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#define DCRN_CPMFR_BASE 0 - -#include - -#endif /* __ASM_VIRTEXIIPRO_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c new file mode 100644 index 00000000000..bbb12c0c0b2 --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.c @@ -0,0 +1,60 @@ +/* + * arch/ppc/platforms/4xx/virtex.c + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +/* Have OCP take care of the serial ports. */ +struct ocp_def core_ocp[] = { +#ifdef XPAR_UARTNS550_0_BASEADDR + { .vendor = OCP_VENDOR_XILINX, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = XPAR_UARTNS550_0_BASEADDR, + .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, + .pm = OCP_CPM_NA + }, +#ifdef XPAR_UARTNS550_1_BASEADDR + { .vendor = OCP_VENDOR_XILINX, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = XPAR_UARTNS550_1_BASEADDR, + .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID, + .pm = OCP_CPM_NA + }, +#ifdef XPAR_UARTNS550_2_BASEADDR + { .vendor = OCP_VENDOR_XILINX, + .function = OCP_FUNC_16550, + .index = 2, + .paddr = XPAR_UARTNS550_2_BASEADDR, + .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID, + .pm = OCP_CPM_NA + }, +#ifdef XPAR_UARTNS550_3_BASEADDR + { .vendor = OCP_VENDOR_XILINX, + .function = OCP_FUNC_16550, + .index = 3, + .paddr = XPAR_UARTNS550_3_BASEADDR, + .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID, + .pm = OCP_CPM_NA + }, +#ifdef XPAR_UARTNS550_4_BASEADDR +#error Edit this file to add more devices. +#endif /* 4 */ +#endif /* 3 */ +#endif /* 2 */ +#endif /* 1 */ +#endif /* 0 */ + { .vendor = OCP_VENDOR_INVALID + } +}; diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h new file mode 100644 index 00000000000..049c767d33e --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.h @@ -0,0 +1,99 @@ +/* + * arch/ppc/platforms/4xx/virtex.h + * + * Include file that defines the Xilinx Virtex-II Pro processor + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_VIRTEX_H__ +#define __ASM_VIRTEX_H__ + +#include +#include + +/* serial defines */ + +#define RS_TABLE_SIZE 4 /* change this and add more devices below + if you have more then 4 16x50 UARTs */ + +#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16) + +/* The serial ports in the Virtex-II Pro have each I/O byte in the + * LSByte of a word. This means that iomem_reg_shift needs to be 2 to + * change the byte offsets into word offsets. In addition the base + * addresses need to have 3 added to them to get to the LSByte. + */ +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ + ASYNC_BOOT_AUTOCONF, \ + .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM}, + +#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) +#define ML300_UART0 STD_UART_OP(0) +#else +#define ML300_UART0 +#endif + +#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) +#define ML300_UART1 STD_UART_OP(1) +#else +#define ML300_UART1 +#endif + +#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) +#define ML300_UART2 STD_UART_OP(2) +#else +#define ML300_UART2 +#endif + +#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) +#define ML300_UART3 STD_UART_OP(3) +#else +#define ML300_UART3 +#endif + +#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID) +#error Edit this file to add more devices. +#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) +#define NR_SER_PORTS 4 +#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) +#define NR_SER_PORTS 3 +#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) +#define NR_SER_PORTS 2 +#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) +#define NR_SER_PORTS 1 +#else +#define NR_SER_PORTS 0 +#endif + +#if defined(CONFIG_UART0_TTYS0) +#define SERIAL_PORT_DFNS \ + ML300_UART0 \ + ML300_UART1 \ + ML300_UART2 \ + ML300_UART3 +#endif + +#if defined(CONFIG_UART0_TTYS1) +#define SERIAL_PORT_DFNS \ + ML300_UART1 \ + ML300_UART0 \ + ML300_UART2 \ + ML300_UART3 +#endif + +#define DCRN_CPMFR_BASE 0 + +#include + +#endif /* __ASM_VIRTEX_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c index 0b1b77d986b..b0de0a2f131 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ b/arch/ppc/platforms/4xx/xilinx_ml300.c @@ -22,7 +22,7 @@ #include #include -#include /* for NR_SER_PORTS */ +#include /* for NR_SER_PORTS */ /* * As an overview of how the following functions (platform_init, diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h index f8c58841233..89939814362 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.h +++ b/arch/ppc/platforms/4xx/xilinx_ml300.h @@ -16,7 +16,7 @@ #define __ASM_XILINX_ML300_H__ /* ML300 has a Xilinx Virtex-II Pro processor */ -#include +#include #ifndef __ASSEMBLY__ -- cgit v1.2.3 From 1a42e53d175074f340a3f85042ed64cfc51be216 Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:12:48 -0700 Subject: [PATCH] powerpc: Migrate Xilinx Vertex support from the OCP bus to the platfom bus. This patch only deals with the serial port definitions as there is no support for any other xilinx IP cores in the kernel tree at the moment. Board specific configuration moved out of virtex.[ch] and into the xparameters.h wrapper. This also prepares for the transition to the flattened device tree model. When the bootloader provides a device tree generated from an xparameters.h files, the kernel will no longer need xparameters/*. The platform bus will get populated with data from the device tree, and the device drivers will be automatically connected to the devices. Only the bootloader (or ppcboot) will need xparameters directly. Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/Kconfig | 5 -- arch/ppc/platforms/4xx/virtex.c | 88 +++++++++++------------- arch/ppc/platforms/4xx/virtex.h | 86 +++-------------------- arch/ppc/platforms/4xx/xparameters/xparameters.h | 21 +++++- 4 files changed, 72 insertions(+), 128 deletions(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index 203abab32cc..057c7c2ab99 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -172,11 +172,6 @@ config IBM_OCP depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y -config XILINX_OCP - bool - depends on XILINX_ML300 - default y - config IBM_EMAC4 bool depends on 440GX || 440SP || 440SPE diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c index bbb12c0c0b2..133a8314719 100644 --- a/arch/ppc/platforms/4xx/virtex.c +++ b/arch/ppc/platforms/4xx/virtex.c @@ -1,60 +1,56 @@ /* - * arch/ppc/platforms/4xx/virtex.c + * Virtex-II Pro & Virtex-4 FX common infrastructure * - * Author: MontaVista Software, Inc. - * source@mvista.com + * Maintainer: Grant Likely * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. + * Copyright 2005 Secret Lab Technologies Ltd. + * Copyright 2005 General Dynamics Canada Ltd. + * Copyright 2005 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. */ -#include #include -#include +#include +#include +#include +#include #include +#include + +#define XPAR_UART(num) { \ + .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \ + .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ + .iotype = UPIO_MEM, \ + .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \ + .flags = UPF_BOOT_AUTOCONF, \ + .regshift = 2, \ + } -/* Have OCP take care of the serial ports. */ -struct ocp_def core_ocp[] = { +struct plat_serial8250_port serial_platform_data[] = { #ifdef XPAR_UARTNS550_0_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = XPAR_UARTNS550_0_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, - .pm = OCP_CPM_NA - }, + XPAR_UART(0), +#endif #ifdef XPAR_UARTNS550_1_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = XPAR_UARTNS550_1_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID, - .pm = OCP_CPM_NA - }, + XPAR_UART(1), +#endif #ifdef XPAR_UARTNS550_2_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = XPAR_UARTNS550_2_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID, - .pm = OCP_CPM_NA - }, + XPAR_UART(2), +#endif #ifdef XPAR_UARTNS550_3_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 3, - .paddr = XPAR_UARTNS550_3_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID, - .pm = OCP_CPM_NA + XPAR_UART(3), +#endif + { }, /* terminated by empty record */ +}; + +struct platform_device ppc_sys_platform_devices[] = { + [VIRTEX_UART] = { + .name = "serial8250", + .id = 0, + .dev.platform_data = serial_platform_data, }, -#ifdef XPAR_UARTNS550_4_BASEADDR -#error Edit this file to add more devices. -#endif /* 4 */ -#endif /* 3 */ -#endif /* 2 */ -#endif /* 1 */ -#endif /* 0 */ - { .vendor = OCP_VENDOR_INVALID - } }; + diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h index 049c767d33e..1a01b81cff1 100644 --- a/arch/ppc/platforms/4xx/virtex.h +++ b/arch/ppc/platforms/4xx/virtex.h @@ -15,85 +15,21 @@ #ifndef __ASM_VIRTEX_H__ #define __ASM_VIRTEX_H__ -#include -#include - /* serial defines */ -#define RS_TABLE_SIZE 4 /* change this and add more devices below - if you have more then 4 16x50 UARTs */ - -#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16) - -/* The serial ports in the Virtex-II Pro have each I/O byte in the - * LSByte of a word. This means that iomem_reg_shift needs to be 2 to - * change the byte offsets into word offsets. In addition the base - * addresses need to have 3 added to them to get to the LSByte. - */ -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ - ASYNC_BOOT_AUTOCONF, \ - .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM}, - -#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define ML300_UART0 STD_UART_OP(0) -#else -#define ML300_UART0 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define ML300_UART1 STD_UART_OP(1) -#else -#define ML300_UART1 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define ML300_UART2 STD_UART_OP(2) -#else -#define ML300_UART2 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define ML300_UART3 STD_UART_OP(3) -#else -#define ML300_UART3 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID) -#error Edit this file to add more devices. -#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define NR_SER_PORTS 4 -#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define NR_SER_PORTS 3 -#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define NR_SER_PORTS 2 -#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define NR_SER_PORTS 1 -#else -#define NR_SER_PORTS 0 -#endif +#include -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_PORT_DFNS \ - ML300_UART0 \ - ML300_UART1 \ - ML300_UART2 \ - ML300_UART3 +/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */ +#if !defined(BASE_BAUD) + #define BASE_BAUD (0) /* dummy value; not used */ #endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_PORT_DFNS \ - ML300_UART1 \ - ML300_UART0 \ - ML300_UART2 \ - ML300_UART3 + +/* Device type enumeration for platform bus definitions */ +#ifndef __ASSEMBLY__ +enum ppc_sys_devices { + VIRTEX_UART, +}; #endif - -#define DCRN_CPMFR_BASE 0 - -#include - + #endif /* __ASM_VIRTEX_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h index fe4eac62913..7b7304379dd 100644 --- a/arch/ppc/platforms/4xx/xparameters/xparameters.h +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -1,7 +1,8 @@ /* * include/asm-ppc/xparameters.h * - * This file includes the correct xparameters.h for the CONFIG'ed board + * This file includes the correct xparameters.h for the CONFIG'ed board plus + * fixups to translate board specific XPAR values to a common set of names * * Author: MontaVista Software, Inc. * source@mvista.com @@ -14,5 +15,21 @@ #include #if defined(CONFIG_XILINX_ML300) -#include + #include "xparameters_ml300.h" +#else + /* Add other board xparameter includes here before the #else */ + #error No xparameters_*.h file included +#endif + +#ifndef SERIAL_PORT_DFNS + /* zImage serial port definitions */ + #define RS_TABLE_SIZE 1 + #define SERIAL_PORT_DFNS { \ + .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \ + .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \ + .flags = ASYNC_BOOT_AUTOCONF, \ + .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, #endif -- cgit v1.2.3 From e27db622b850e6426b69ef42e5678ba068c7f8e0 Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:13:03 -0700 Subject: [PATCH] powerpc: Migrate ML300 reference design to the platform bus Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/xilinx_ml300.c | 74 ++++++++++++++++++++++++----------- arch/ppc/platforms/4xx/xilinx_ml300.h | 2 +- 2 files changed, 53 insertions(+), 23 deletions(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c index b0de0a2f131..267afb50607 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ b/arch/ppc/platforms/4xx/xilinx_ml300.c @@ -17,12 +17,14 @@ #include #include #include +#include #include #include #include -#include +#include -#include /* for NR_SER_PORTS */ +#include +#include /* * As an overview of how the following functions (platform_init, @@ -54,6 +56,22 @@ * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c */ +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML300 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + #if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) static volatile unsigned *powerdown_base = @@ -80,28 +98,39 @@ ml300_map_io(void) #endif } +/* Early serial support functions */ static void __init +ml300_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init ml300_early_serial_map(void) { #ifdef CONFIG_SERIAL_8250 - struct serial_state old_ports[] = { SERIAL_PORT_DFNS }; - struct uart_port port; - int i; - - /* Setup ioremapped serial port access */ - for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) { - memset(&port, 0, sizeof(port)); - port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16); - port.irq = old_ports[i].irq; - port.uartclk = old_ports[i].baud_base * 16; - port.regshift = old_ports[i].iomem_reg_shift; - port.iotype = SERIAL_IO_MEM; - port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; - port.line = i; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port %d failed\n", i); - } + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml300_early_serial_init(i, pdata); + pdata++; + i++; } #endif /* CONFIG_SERIAL_8250 */ } @@ -109,9 +138,8 @@ ml300_early_serial_map(void) void __init ml300_setup_arch(void) { - ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ - ml300_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ /* Identify the system */ printk(KERN_INFO "Xilinx Virtex-II Pro port\n"); @@ -131,6 +159,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, { ppc4xx_init(r3, r4, r5, r6, r7); + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + ppc_md.setup_arch = ml300_setup_arch; ppc_md.setup_io_mappings = ml300_map_io; ppc_md.init_IRQ = ml300_init_irq; diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h index 89939814362..ae8bf1353b0 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.h +++ b/arch/ppc/platforms/4xx/xilinx_ml300.h @@ -41,7 +41,7 @@ typedef struct board_info { #define PPC4xx_ONB_IO_VADDR 0u #define PPC4xx_ONB_IO_SIZE 0u -#define PPC4xx_MACHINE_NAME "Xilinx ML300" +#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System" #endif /* __ASM_XILINX_ML300_H__ */ #endif /* __KERNEL__ */ -- cgit v1.2.3 From b58b5aa51c78079fa4f652cd42e7b496a1d5411a Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:13:28 -0700 Subject: [PATCH] powerpc: Add xparameters file for Xilinx ML403 reference design Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- .../platforms/4xx/xparameters/xparameters_ml403.h | 243 +++++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h new file mode 100644 index 00000000000..5cacdcb3964 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h @@ -0,0 +1,243 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000 +#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF + +/******************************************************************/ + +#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000 +#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF +#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000 +#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF +#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF +#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000 +#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF +#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000 +#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF + +/******************************************************************/ + +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 + +/******************************************************************/ + +#define XPAR_XUARTNS550_NUM_INSTANCES 1 +#define XPAR_XUARTNS550_CLOCK_HZ 100000000 +#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 +#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF +#define XPAR_OPB_UART16550_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XGPIO_NUM_INSTANCES 3 +#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000 +#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF +#define XPAR_OPB_GPIO_0_DEVICE_ID 0 +#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000 +#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF +#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000 +#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF +#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2 +#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0 + +/******************************************************************/ + +#define XPAR_XPS2_NUM_INSTANCES 2 +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) + +/******************************************************************/ + +#define XPAR_XIIC_NUM_INSTANCES 1 +#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 +#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF +#define XPAR_OPB_IIC_0_DEVICE_ID 0 +#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 +#define XPAR_OPB_IIC_0_GPO_WIDTH 1 + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +#define XPAR_XINTC_NUM_INSTANCES 1 +#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0 +#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF +#define XPAR_OPB_INTC_0_DEVICE_ID 0 +#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0 +#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001 +#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0 +#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002 +#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1 +#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004 +#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2 +#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008 +#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5 +#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040 +#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 +#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200 +#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9 + +/******************************************************************/ + +#define XPAR_XTFT_NUM_INSTANCES 1 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 +#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XSYSACE_MEM_WIDTH 16 +#define XPAR_XSYSACE_NUM_INSTANCES 1 +#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 +#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF +#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 +#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16 + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + + +/******************************************************************/ + +/* Linux Redefines */ + +/******************************************************************/ + +#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) +#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ +#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR +#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR +#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR +#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR +#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR +#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR +#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR + +/******************************************************************/ + +#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR + +/******************************************************************/ + +#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR +#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR +#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT +#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST +#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0 +#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0 +#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0 +#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1 +#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1 +#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1 +#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0 +#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0 +#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0 +#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1 +#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1 +#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1 +#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR +#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR +#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 +#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 +#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 +#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 +#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 +#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 + +/******************************************************************/ + +#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR +#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR +#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR +#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR +#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR +#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ +#define XPAR_DDR_0_SIZE 0x4000000 + +/******************************************************************/ + +#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 +#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF +#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 + +/******************************************************************/ + +#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 + +/******************************************************************/ + -- cgit v1.2.3 From 909aeca664dd1fe55111dc4ec25c1bebe91674a2 Mon Sep 17 00:00:00 2001 From: "Grant C. Likely" Date: Thu, 19 Jan 2006 01:13:37 -0700 Subject: [PATCH] powerpc: Add support for Xilinx ML403 reference design Includes fix for Xilinx silicon errata 213 Signed-off-by: Grant C. Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/Kconfig | 13 +- arch/ppc/platforms/4xx/Makefile | 2 + arch/ppc/platforms/4xx/xilinx_ml403.c | 177 +++++++++++++++++++++++ arch/ppc/platforms/4xx/xilinx_ml403.h | 49 +++++++ arch/ppc/platforms/4xx/xparameters/xparameters.h | 2 + 5 files changed, 241 insertions(+), 2 deletions(-) create mode 100644 arch/ppc/platforms/4xx/xilinx_ml403.c create mode 100644 arch/ppc/platforms/4xx/xilinx_ml403.h (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index 057c7c2ab99..174ddbc9758 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -57,6 +57,10 @@ config XILINX_ML300 help This option enables support for the Xilinx ML300 evaluation board. +config XILINX_ML403 + bool "Xilinx-ML403" + help + This option enables support for the Xilinx ML403 evaluation board. endchoice choice @@ -208,9 +212,14 @@ config XILINX_VIRTEX_II_PRO depends on XILINX_ML300 default y +config XILINX_VIRTEX_4_FX + bool + depends on XILINX_ML403 + default y + config XILINX_VIRTEX bool - depends on XILINX_VIRTEX_II_PRO + depends on XILINX_VIRTEX_II_PRO || XILINX_VIRTEX_4_FX default y config STB03xxx @@ -220,7 +229,7 @@ config STB03xxx config EMBEDDEDBOOT bool - depends on EP405 || XILINX_ML300 + depends on EP405 || XILINX_ML300 || XILINX_ML403 default y config IBM_OPENBIOS diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index be4163c8afe..a04a0d0a0f5 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o obj-$(CONFIG_SYCAMORE) += sycamore.o obj-$(CONFIG_WALNUT) += walnut.o obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o +obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o obj-$(CONFIG_405GP) += ibm405gp.o obj-$(CONFIG_REDWOOD_5) += ibmstb4.o @@ -27,3 +28,4 @@ obj-$(CONFIG_440SPE) += ppc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o obj-$(CONFIG_XILINX_VIRTEX) += virtex.o + diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c new file mode 100644 index 00000000000..4c0c7e4c111 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.c @@ -0,0 +1,177 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.c + * + * Xilinx ML403 evaluation board initialization + * + * Author: Grant Likely + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * As an overview of how the following functions (platform_init, + * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the + * kernel startup procedure, here's a call tree: + * + * start_here arch/ppc/kernel/head_4xx.S + * early_init arch/ppc/kernel/setup.c + * machine_init arch/ppc/kernel/setup.c + * platform_init this file + * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c + * parse_bootinfo + * find_bootinfo + * "setup some default ppc_md pointers" + * MMU_init arch/ppc/mm/init.c + * *ppc_md.setup_io_mappings == ml403_map_io this file + * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c + * start_kernel init/main.c + * setup_arch arch/ppc/kernel/setup.c + * #if defined(CONFIG_KGDB) + * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc + * #endif + * *ppc_md.setup_arch == ml403_setup_arch this file + * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c + * init_IRQ arch/ppc/kernel/irq.c + * *ppc_md.init_IRQ == ml403_init_IRQ this file + * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c + */ + +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML403 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + +static volatile unsigned *powerdown_base = + (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR; + +static void +xilinx_power_off(void) +{ + local_irq_disable(); + out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE); + while (1) ; +} +#endif + +void __init +ml403_map_io(void) +{ + ppc4xx_map_io(); + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + powerdown_base = ioremap((unsigned long) powerdown_base, + XPAR_POWER_0_POWERDOWN_HIGHADDR - + XPAR_POWER_0_POWERDOWN_BASEADDR + 1); +#endif +} + +/* Early serial support functions */ +static void __init +ml403_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init +ml403_early_serial_map(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml403_early_serial_init(i, pdata); + pdata++; + i++; + } +#endif /* CONFIG_SERIAL_8250 */ +} + +void __init +ml403_setup_arch(void) +{ + ml403_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ + + /* Identify the system */ + printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n"); +} + +/* Called after board_setup_irq from ppc4xx_init_IRQ(). */ +void __init +ml403_init_irq(void) +{ + ppc4xx_init_IRQ(); +} + +void __init +platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + ppc4xx_init(r3, r4, r5, r6, r7); + + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + + ppc_md.setup_arch = ml403_setup_arch; + ppc_md.setup_io_mappings = ml403_map_io; + ppc_md.init_IRQ = ml403_init_irq; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + ppc_md.power_off = xilinx_power_off; +#endif + +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = ml403_early_serial_map; +#endif +} + diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.h b/arch/ppc/platforms/4xx/xilinx_ml403.h new file mode 100644 index 00000000000..47359695990 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.h @@ -0,0 +1,49 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.h + * + * Include file that defines the Xilinx ML403 reference design + * + * Author: Grant Likely + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_XILINX_ML403_H__ +#define __ASM_XILINX_ML403_H__ + +/* ML403 has a Xilinx Virtex-4 FPGA with a PPC405 hard core */ +#include + +#ifndef __ASSEMBLY__ + +#include + +typedef struct board_info { + unsigned int bi_memsize; /* DRAM installed, in bytes */ + unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ + unsigned int bi_intfreq; /* Processor speed, in Hz */ + unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ +} bd_t; + +/* Some 4xx parts use a different timebase frequency from the internal clock. +*/ +#define bi_tbfreq bi_intfreq + +#endif /* !__ASSEMBLY__ */ + +/* We don't need anything mapped. Size of zero will accomplish that. */ +#define PPC4xx_ONB_IO_PADDR 0u +#define PPC4xx_ONB_IO_VADDR 0u +#define PPC4xx_ONB_IO_SIZE 0u + +#define PPC4xx_MACHINE_NAME "Xilinx ML403 Reference Design" + +#endif /* __ASM_XILINX_ML403_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h index 7b7304379dd..4cf21f25635 100644 --- a/arch/ppc/platforms/4xx/xparameters/xparameters.h +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -16,6 +16,8 @@ #if defined(CONFIG_XILINX_ML300) #include "xparameters_ml300.h" +#elif defined(CONFIG_XILINX_ML403) + #include "xparameters_ml403.h" #else /* Add other board xparameter includes here before the #else */ #error No xparameters_*.h file included -- cgit v1.2.3 From 42dc75c4b97922d3d7707ac0b097fbeeca20b108 Mon Sep 17 00:00:00 2001 From: Vitaly Bordug Date: Fri, 20 Jan 2006 22:22:36 +0300 Subject: [PATCH] ppc32: MPC885ADS, MPC866ADS and MPC8272ADS-specific platform stuff for fs_enet Added proper ppc_sys identification and fs_platform_info's for MPC 885ADS, 866ADS and 8272ADS, utilizing function assignment to remove/do not use platform devices which conflict with PD-incompatible drivers. Signed-off-by: Vitaly Bordug Signed-off-by: Paul Mackerras --- arch/ppc/platforms/Makefile | 3 + arch/ppc/platforms/fads.h | 2 +- arch/ppc/platforms/mpc8272ads_setup.c | 236 +++++++++++++++++++++ arch/ppc/platforms/mpc866ads_setup.c | 273 ++++++++++++++++++++++++ arch/ppc/platforms/mpc885ads_setup.c | 389 ++++++++++++++++++++++++++++++++++ arch/ppc/platforms/pq2ads.h | 4 + arch/ppc/platforms/pq2ads_pd.h | 114 ++++++++++ 7 files changed, 1020 insertions(+), 1 deletion(-) create mode 100644 arch/ppc/platforms/mpc8272ads_setup.c create mode 100644 arch/ppc/platforms/mpc866ads_setup.c create mode 100644 arch/ppc/platforms/mpc885ads_setup.c create mode 100644 arch/ppc/platforms/pq2ads_pd.h (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile index 51430e294b3..e8b91a33ce9 100644 --- a/arch/ppc/platforms/Makefile +++ b/arch/ppc/platforms/Makefile @@ -37,6 +37,9 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o obj-$(CONFIG_SPRUCE) += spruce.o obj-$(CONFIG_LITE5200) += lite5200.o obj-$(CONFIG_EV64360) += ev64360.o +obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o +obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o +obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_PPC_CHRP) += chrp_smp.o diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h index a48fb8d723e..e1c0b1b6dcb 100644 --- a/arch/ppc/platforms/fads.h +++ b/arch/ppc/platforms/fads.h @@ -112,7 +112,7 @@ /* CPM Ethernet through SCC1 or SCC2 */ -#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */ +#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */ /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. * TCLK - CLK1, RCLK - CLK2. diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c new file mode 100644 index 00000000000..bc9b94f77e3 --- /dev/null +++ b/arch/ppc/platforms/mpc8272ads_setup.c @@ -0,0 +1,236 @@ +/* + * arch/ppc/platforms/82xx/pq2ads_pd.c + * + * MPC82xx Board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "pq2ads_pd.h" + +static void init_fcc1_ioports(void); +static void init_fcc2_ioports(void); + +static struct fs_mii_bus_info mii_bus_info = { + .method = fsmii_bitbang, + .id = 0, + .i.bitbang = { + .mdio_port = fsiop_portc, + .mdio_bit = 18, + .mdc_port = fsiop_portc, + .mdc_bit = 19, + .delay = 1, + }, +}; + +static struct fs_platform_info mpc82xx_fcc1_pdata = { + .fs_no = fsid_fcc1, + .cp_page = CPM_CR_FCC1_PAGE, + .cp_block = CPM_CR_FCC1_SBLOCK, + .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), + .clk_route = CMX1_CLK_ROUTE, + .clk_mask = CMX1_CLK_MASK, + .init_ioports = init_fcc1_ioports, + + .phy_addr = 0, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC1_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static struct fs_platform_info mpc82xx_fcc2_pdata = { + .fs_no = fsid_fcc2, + .cp_page = CPM_CR_FCC2_PAGE, + .cp_block = CPM_CR_FCC2_SBLOCK, + .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), + .clk_route = CMX2_CLK_ROUTE, + .clk_mask = CMX2_CLK_MASK, + .init_ioports = init_fcc2_ioports, + + .phy_addr = 3, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC2_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static void init_fcc1_ioports(void) +{ + struct io_port *io; + u32 tempval; + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32)); + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR1_FETHIEN); + setbits32(bcsr, BCSR1_FETH_RST); + + /* FCC1 pins are on port A/C. */ + /* Configure port A and C pins for FCC1 Ethernet. */ + + tempval = in_be32(&io->iop_pdira); + tempval &= ~PA1_DIRA0; + tempval |= PA1_DIRA1; + out_be32(&io->iop_pdira, tempval); + + tempval = in_be32(&io->iop_psora); + tempval &= ~PA1_PSORA0; + tempval |= PA1_PSORA1; + out_be32(&io->iop_psora, tempval); + + setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1); + + /* Alter clocks */ + tempval = PC_F1TXCLK|PC_F1RXCLK; + + clrbits32(&io->iop_psorc, tempval); + clrbits32(&io->iop_pdirc, tempval); + setbits32(&io->iop_pparc, tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE); + iounmap(bcsr); + iounmap(immap); +} + +static void init_fcc2_ioports(void) +{ + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32)); + + struct io_port *io; + u32 tempval; + + immap = cpm2_immr; + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR3_FETHIEN2); + setbits32(bcsr, BCSR3_FETH2_RST); + + /* FCC2 are port B/C. */ + /* Configure port A and C pins for FCC2 Ethernet. */ + + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB2_DIRB0; + tempval |= PB2_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB2_PSORB0; + tempval |= PB2_PSORB1; + out_be32(&io->iop_psorb, tempval); + + setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1); + + tempval = PC_F2RXCLK|PC_F2TXCLK; + + /* Alter clocks */ + clrbits32(&io->iop_psorc,tempval); + clrbits32(&io->iop_pdirc,tempval); + setbits32(&io->iop_pparc,tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE); + + iounmap(bcsr); + iounmap(immap); +} + + +static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, + int idx) +{ + bd_t* bi = (void*)__res; + int fs_no = fsid_fcc1+pdev->id-1; + + mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase; + mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c; + + switch(fs_no) { + case fsid_fcc1: + memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6); + pdev->dev.platform_data = &mpc82xx_fcc1_pdata; + break; + case fsid_fcc2: + memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6); + mpc82xx_fcc2_pdata.macaddr[5] ^= 1; + pdev->dev.platform_data = &mpc82xx_fcc2_pdata; + break; + } +} + +static int mpc8272ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fcc", + .rtn = mpc8272ads_fixup_enet_pdata + }, + { + .bus_id = NULL + } + }; + platform_notify_map(dev_map,dev); + + return 0; + +} + +int __init mpc8272ads_init(void) +{ + printk(KERN_NOTICE "mpc8272ads: Init\n"); + + platform_notify = mpc8272ads_platform_notify; + + ppc_sys_device_initfunc(); + + ppc_sys_device_disable_all(); + ppc_sys_device_enable(MPC82xx_CPM_FCC1); + ppc_sys_device_enable(MPC82xx_CPM_FCC2); + + return 0; +} + +arch_initcall(mpc8272ads_init); diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c new file mode 100644 index 00000000000..ac8fcc68afe --- /dev/null +++ b/arch/ppc/platforms/mpc866ads_setup.c @@ -0,0 +1,273 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern unsigned char __res[]; + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { + .method = fsmii_fixed, + .id = 0, + .i.fixed.speed = 10, + .i.fixed.duplex = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 15, + .phy_irq = -1, + + .use_rmii = 0, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = -1, + .phy_irq = -1, + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io,(0x80000000 >> 7)); +#else + setbits32(bcsr_io,(0x80000000 >> 7)); + + cp->cp_pbpar &= ~(0x000000c0); + cp->cp_pbdir |= 0x000000c0; + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,(0x80000000 >> 13)); +#else + clrbits32(bcsr_io,(0x80000000 >> 13)); + cp->cp_pbpar &= ~(0x00000c00); + cp->cp_pbdir |= 0x00000c00; + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + setbits16(&immap->im_ioport.iop_pdpar, 0x1fff); + setbits16(&immap->im_ioport.iop_pddir, 0x1fff); +} + +static void setup_scc1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } + + /* Enable the PHY. + */ + clrbits32(bcsr_io,BCSR1_ETHEN); + + /* Configure port A pins for Txd and Rxd. + */ + /* Disable receive and transmit in case EPPC-Bug started it. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + /* Configure port A for TCLK and RCLK. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + +} + +static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + + break; + case fsid_scc1: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc1_ioports; + + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +static int mpc866ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc866ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc866ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + + return 0; +} + +int __init mpc866ads_init(void) +{ + printk(KERN_NOTICE "mpc866ads: Init\n"); + + platform_notify = mpc866ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + +#ifdef MPC8xx_SECOND_ETH_SCC1 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); +#endif + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + + return 0; +} + +arch_initcall(mpc866ads_init); diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c new file mode 100644 index 00000000000..50a99e5f7c6 --- /dev/null +++ b/arch/ppc/platforms/mpc885ads_setup.c @@ -0,0 +1,389 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern unsigned char __res[]; + +static void __init mpc885ads_scc_phy_init(char); + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { +#ifdef CONFIG_SCC_ENET_8xx_FIXED + .method = fsmii_fixed, +#else + .method = fsmii_fec, +#endif + + .id = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 0, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + }, { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 1, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 2, +#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED + .phy_irq = -1, +#else + .phy_irq = SIU_IRQ7, +#endif + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned int *bcsr_io; + +#ifdef CONFIG_FS_ENET + immap_t *immap = (immap_t *) IMAP_ADDR; +#endif + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io, BCSR1_RS232EN_1); +#else + setbits32(bcsr_io,BCSR1_RS232EN_1); + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,BCSR1_RS232EN_2); +#else + setbits32(bcsr_io,BCSR1_RS232EN_2); + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); + +#ifdef CONFIG_FS_ENET + /* use MDC for MII (common) */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); +#endif +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC1 pins */ + setbits16(&immap->im_ioport.iop_papar, 0xf830); + setbits16(&immap->im_ioport.iop_padir, 0x0830); + clrbits16(&immap->im_ioport.iop_padir, 0xf000); + setbits32(&immap->im_cpm.cp_pbpar, 0x00001001); + + clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001); + setbits16(&immap->im_ioport.iop_pcpar, 0x000c); + clrbits16(&immap->im_ioport.iop_pcdir, 0x000c); + setbits32(&immap->im_cpm.cp_pepar, 0x00000003); + + setbits32(&immap->im_cpm.cp_pedir, 0x00000003); + clrbits32(&immap->im_cpm.cp_peso, 0x00000003); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000100); +} + +static void setup_fec2_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC2 pins */ + setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); + setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); + setbits32(&immap->im_cpm.cp_peso, 0x00037800); + clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); +} + +static void setup_scc3_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } + + /* Enable the PHY. + */ + setbits32(bcsr_io+4, BCSR4_ETH10_RST); + /* Configure port A pins for Txd and Rxd. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port E for TCLK and RCLK. + */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, + PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. + */ + immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode + * by H/W setting after reset. SCC ethernet controller support only half duplex. + * This discrepancy of modes causes a lot of carrier lost errors. + */ + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + setbits32(bcsr_io+1, BCSR1_ETHEN); + iounmap(bcsr_io); +} + +static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + break; + case fsid_fec2: + fpi = &mpc8xx_fec_pdata[1]; + fpi->init_ioports = &setup_fec2_ioports; + break; + case fsid_scc3: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc3_ioports; + mpc885ads_scc_phy_init(fpi->phy_addr); + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +/* SCC ethernet controller does not have MII management channel. FEC1 MII + * channel is used to communicate with the 10Mbit PHY. + */ + +#define MII_ECNTRL_PINMUX 0x4 +#define FEC_ECNTRL_PINMUX 0x00000004 +#define FEC_RCNTRL_MII_MODE 0x00000004 + +/* Make MII read/write commands. + */ +#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \ + ((VAL) & 0xffff) | ((PHY_ADDR) << 23)) + +static void mpc885ads_scc_phy_init(char phy_addr) +{ + volatile immap_t *immap; + volatile fec_t *fecp; + bd_t *bd; + + bd = (bd_t *) __res; + immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */ + fecp = &(immap->im_cpm.cp_fec); + + /* Enable MII pins of the FEC1 + */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); + /* Set MII speed to 2.5 MHz + */ + out_be32(&fecp->fec_mii_speed, + ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1); + + /* Enable FEC pin MUX + */ + setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr)); + udelay(100); + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_ADVERTISE, + ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr)); + udelay(100); + + /* Disable FEC MII settings + */ + clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + out_be32(&fecp->fec_mii_speed, 0); +} + +static int mpc885ads_platform_notify(struct device *dev) +{ + + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc885ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc885ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + +} + +int __init mpc885ads_init(void) +{ + printk(KERN_NOTICE "mpc885ads: Init\n"); + + platform_notify = mpc885ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + +#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); + +#endif +#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 + ppc_sys_device_enable(MPC8xx_CPM_FEC2); +#endif + + return 0; +} + +arch_initcall(mpc885ads_init); diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h index 067d9a5aebc..6b26dd36c64 100644 --- a/arch/ppc/platforms/pq2ads.h +++ b/arch/ppc/platforms/pq2ads.h @@ -13,6 +13,10 @@ #include +#if defined(CONFIG_ADS8272) +#define BOARD_CHIP_NAME "8272" +#endif + /* Memory map is configured by the PROM startup. * We just map a few things we need. The CSR is actually 4 byte-wide * registers that can be accessed as 8-, 16-, or 32-bit values. diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h new file mode 100644 index 00000000000..8f14a43eafe --- /dev/null +++ b/arch/ppc/platforms/pq2ads_pd.h @@ -0,0 +1,114 @@ +#ifndef __PQ2ADS_PD_H +#define __PQ2ADS_PD_H +/* + * arch/ppc/platforms/82xx/pq2ads_pd.h + * + * Some defines for MPC82xx board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* FCC1 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK9-12 */ + +#define F1_RXCLK 11 +#define F1_TXCLK 10 + +/* FCC2 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F2_RXCLK 15 +#define F2_TXCLK 16 + +/* FCC3 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F3_RXCLK 13 +#define F3_TXCLK 14 + +/* Automatically generates register configurations */ +#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ + +#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ +#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ +#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ +#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ +#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ +#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ + +#define PC_F1RXCLK PC_CLK(F1_RXCLK) +#define PC_F1TXCLK PC_CLK(F1_TXCLK) +#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) +#define CMX1_CLK_MASK ((uint)0xff000000) + +#define PC_F2RXCLK PC_CLK(F2_RXCLK) +#define PC_F2TXCLK PC_CLK(F2_TXCLK) +#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) +#define CMX2_CLK_MASK ((uint)0x00ff0000) + +#define PC_F3RXCLK PC_CLK(F3_RXCLK) +#define PC_F3TXCLK PC_CLK(F3_TXCLK) +#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) +#define CMX3_CLK_MASK ((uint)0x0000ff00) + +/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PA1_COL 0x00000001U +#define PA1_CRS 0x00000002U +#define PA1_TXER 0x00000004U +#define PA1_TXEN 0x00000008U +#define PA1_RXDV 0x00000010U +#define PA1_RXER 0x00000020U +#define PA1_TXDAT 0x00003c00U +#define PA1_RXDAT 0x0003c000U +#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) +#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ + PA1_RXDV | PA1_RXER) +#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) +#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) + + +/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB2_TXER 0x00000001U +#define PB2_RXDV 0x00000002U +#define PB2_TXEN 0x00000004U +#define PB2_RXER 0x00000008U +#define PB2_COL 0x00000010U +#define PB2_CRS 0x00000020U +#define PB2_TXDAT 0x000003c0U +#define PB2_RXDAT 0x00003c00U +#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ + PB2_RXER | PB2_RXDV | PB2_TXER) +#define PB2_PSORB1 (PB2_TXEN) +#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) +#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) + + +/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB3_RXDV 0x00004000U +#define PB3_RXER 0x00008000U +#define PB3_TXER 0x00010000U +#define PB3_TXEN 0x00020000U +#define PB3_COL 0x00040000U +#define PB3_CRS 0x00080000U +#define PB3_TXDAT 0x0f000000U +#define PB3_RXDAT 0x00f00000U +#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ + PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) +#define PB3_PSORB1 0 +#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) +#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) + +#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) +#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) +#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) + +#endif -- cgit v1.2.3 From 2ef9481e666b4654159ac9f847e6963809e3c470 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 23 Jan 2006 10:58:20 -0600 Subject: [PATCH] powerpc: trivial: modify comments to refer to new location of files This patch removes all self references and fixes references to files in the now defunct arch/ppc64 tree. I think this accomplises everything wanted, though there might be a few references I missed. Signed-off-by: Jon Mason Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/bamboo.c | 2 -- arch/ppc/platforms/4xx/bamboo.h | 2 -- arch/ppc/platforms/4xx/bubinga.h | 2 -- arch/ppc/platforms/4xx/cpci405.c | 2 -- arch/ppc/platforms/4xx/ebony.c | 2 -- arch/ppc/platforms/4xx/ebony.h | 2 -- arch/ppc/platforms/4xx/ep405.c | 2 -- arch/ppc/platforms/4xx/ep405.h | 2 -- arch/ppc/platforms/4xx/ibm405ep.c | 2 -- arch/ppc/platforms/4xx/ibm405ep.h | 2 -- arch/ppc/platforms/4xx/ibm405gp.h | 2 -- arch/ppc/platforms/4xx/ibm405gpr.c | 2 -- arch/ppc/platforms/4xx/ibm405gpr.h | 2 -- arch/ppc/platforms/4xx/ibm440ep.c | 2 -- arch/ppc/platforms/4xx/ibm440ep.h | 2 -- arch/ppc/platforms/4xx/ibm440gp.c | 2 -- arch/ppc/platforms/4xx/ibm440gp.h | 2 -- arch/ppc/platforms/4xx/ibm440gx.c | 2 -- arch/ppc/platforms/4xx/ibm440gx.h | 2 -- arch/ppc/platforms/4xx/ibm440sp.c | 2 -- arch/ppc/platforms/4xx/ibm440sp.h | 2 -- arch/ppc/platforms/4xx/ibmnp405h.c | 2 -- arch/ppc/platforms/4xx/ibmnp405h.h | 2 -- arch/ppc/platforms/4xx/ibmstb4.c | 2 -- arch/ppc/platforms/4xx/ibmstb4.h | 2 -- arch/ppc/platforms/4xx/ibmstbx25.c | 2 -- arch/ppc/platforms/4xx/ibmstbx25.h | 2 -- arch/ppc/platforms/4xx/luan.c | 2 -- arch/ppc/platforms/4xx/luan.h | 2 -- arch/ppc/platforms/4xx/ocotea.c | 2 -- arch/ppc/platforms/4xx/ocotea.h | 2 -- arch/ppc/platforms/4xx/ppc440spe.c | 2 -- arch/ppc/platforms/4xx/ppc440spe.h | 2 -- arch/ppc/platforms/4xx/redwood5.c | 2 -- arch/ppc/platforms/4xx/redwood5.h | 2 -- arch/ppc/platforms/4xx/redwood6.c | 2 -- arch/ppc/platforms/4xx/redwood6.h | 2 -- arch/ppc/platforms/4xx/sycamore.c | 2 -- arch/ppc/platforms/4xx/sycamore.h | 2 -- arch/ppc/platforms/4xx/walnut.c | 2 -- arch/ppc/platforms/4xx/walnut.h | 2 -- arch/ppc/platforms/4xx/xilinx_ml300.c | 2 -- arch/ppc/platforms/4xx/xilinx_ml300.h | 2 -- arch/ppc/platforms/4xx/yucca.c | 2 -- arch/ppc/platforms/4xx/yucca.h | 2 -- arch/ppc/platforms/83xx/mpc834x_sys.c | 2 -- arch/ppc/platforms/83xx/mpc834x_sys.h | 2 -- arch/ppc/platforms/85xx/mpc8540_ads.c | 2 -- arch/ppc/platforms/85xx/mpc8540_ads.h | 2 -- arch/ppc/platforms/85xx/mpc8555_cds.h | 2 -- arch/ppc/platforms/85xx/mpc8560_ads.c | 2 -- arch/ppc/platforms/85xx/mpc8560_ads.h | 2 -- arch/ppc/platforms/85xx/mpc85xx_ads_common.c | 2 -- arch/ppc/platforms/85xx/mpc85xx_ads_common.h | 2 -- arch/ppc/platforms/85xx/mpc85xx_cds_common.c | 2 -- arch/ppc/platforms/85xx/mpc85xx_cds_common.h | 2 -- arch/ppc/platforms/85xx/sbc8560.c | 2 -- arch/ppc/platforms/85xx/sbc8560.h | 2 -- arch/ppc/platforms/85xx/sbc85xx.c | 2 -- arch/ppc/platforms/85xx/sbc85xx.h | 2 -- arch/ppc/platforms/85xx/stx_gp3.c | 2 -- arch/ppc/platforms/85xx/stx_gp3.h | 2 -- arch/ppc/platforms/85xx/tqm85xx.c | 2 -- arch/ppc/platforms/85xx/tqm85xx.h | 2 -- arch/ppc/platforms/apus_setup.c | 2 -- arch/ppc/platforms/chestnut.c | 2 -- arch/ppc/platforms/chestnut.h | 2 -- arch/ppc/platforms/chrp_pegasos_eth.c | 2 -- arch/ppc/platforms/chrp_setup.c | 2 -- arch/ppc/platforms/chrp_time.c | 2 -- arch/ppc/platforms/cpci690.c | 2 -- arch/ppc/platforms/cpci690.h | 2 -- arch/ppc/platforms/ev64260.c | 2 -- arch/ppc/platforms/ev64260.h | 2 -- arch/ppc/platforms/ev64360.c | 2 -- arch/ppc/platforms/ev64360.h | 2 -- arch/ppc/platforms/gemini.h | 3 --- arch/ppc/platforms/gemini_prom.S | 2 -- arch/ppc/platforms/gemini_setup.c | 2 -- arch/ppc/platforms/hdpu.c | 3 --- arch/ppc/platforms/hdpu.h | 2 -- arch/ppc/platforms/katana.c | 2 -- arch/ppc/platforms/katana.h | 2 -- arch/ppc/platforms/lite5200.c | 2 -- arch/ppc/platforms/lite5200.h | 2 -- arch/ppc/platforms/lopec.c | 2 -- arch/ppc/platforms/mvme5100.c | 2 -- arch/ppc/platforms/pal4.h | 2 -- arch/ppc/platforms/pal4_pci.c | 2 -- arch/ppc/platforms/pal4_serial.h | 2 -- arch/ppc/platforms/pal4_setup.c | 2 -- arch/ppc/platforms/powerpmc250.c | 2 -- arch/ppc/platforms/pplus.c | 2 -- arch/ppc/platforms/pplus.h | 2 -- arch/ppc/platforms/pq2ads.c | 2 -- arch/ppc/platforms/prep_setup.c | 2 -- arch/ppc/platforms/prpmc750.c | 2 -- arch/ppc/platforms/prpmc800.c | 2 -- arch/ppc/platforms/radstone_ppc7d.c | 2 -- arch/ppc/platforms/radstone_ppc7d.h | 2 -- arch/ppc/platforms/sandpoint.c | 2 -- arch/ppc/platforms/sandpoint.h | 2 -- arch/ppc/platforms/sbc82xx.c | 2 -- arch/ppc/platforms/spruce.c | 2 -- arch/ppc/platforms/tqm8260_setup.c | 2 -- 105 files changed, 212 deletions(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c index 0ec53f04933..b940cfd646c 100644 --- a/arch/ppc/platforms/4xx/bamboo.c +++ b/arch/ppc/platforms/4xx/bamboo.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/bamboo.c - * * Bamboo board specific routines * * Wade Farnsworth diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h index 5c019282649..31c0dd6a26c 100644 --- a/arch/ppc/platforms/4xx/bamboo.h +++ b/arch/ppc/platforms/4xx/bamboo.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/bamboo.h - * * Bamboo board definitions * * Wade Farnsworth diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h index b5380cfaf5c..606aa9fa5ca 100644 --- a/arch/ppc/platforms/4xx/bubinga.h +++ b/arch/ppc/platforms/4xx/bubinga.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/bubinga.h - * * Bubinga board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c index ff966773a0b..6571e39fbe4 100644 --- a/arch/ppc/platforms/4xx/cpci405.c +++ b/arch/ppc/platforms/4xx/cpci405.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci405.c - * * Board setup routines for the esd CPCI-405 cPCI Board. * * Author: Stefan Roese diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 9a828b62341..b4ecb9c7985 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ebony.c - * * Ebony board specific routines * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h index b91ad4272df..27b2e77c7c8 100644 --- a/arch/ppc/platforms/4xx/ebony.h +++ b/arch/ppc/platforms/4xx/ebony.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ebony.h - * * Ebony board definitions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c index 26a07cdb30e..6efa91ff9c0 100644 --- a/arch/ppc/platforms/4xx/ep405.c +++ b/arch/ppc/platforms/4xx/ep405.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ep405.c - * * Embedded Planet 405GP board * http://www.embeddedplanet.com * diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h index ea3eb21338f..9814fc43172 100644 --- a/arch/ppc/platforms/4xx/ep405.h +++ b/arch/ppc/platforms/4xx/ep405.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ep405.h - * * Embedded Planet 405GP board * http://www.embeddedplanet.com * diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c index 093b28d27a4..55af769a6e7 100644 --- a/arch/ppc/platforms/4xx/ibm405ep.c +++ b/arch/ppc/platforms/4xx/ibm405ep.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ibm405ep.c - * * Support for IBM PPC 405EP processors. * * Author: SAW (IBM), derived from ibmnp405l.c. diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h index e051e3fe8c6..fe46640de15 100644 --- a/arch/ppc/platforms/4xx/ibm405ep.h +++ b/arch/ppc/platforms/4xx/ibm405ep.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405ep.h - * * IBM PPC 405EP processor defines. * * Author: SAW (IBM), derived from ibm405gp.h. diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h index b2b642e81af..eaf0ef57028 100644 --- a/arch/ppc/platforms/4xx/ibm405gp.h +++ b/arch/ppc/platforms/4xx/ibm405gp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gp.h - * * Author: Armin Kuster akuster@mvista.com * * 2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c index cd0d00d8e8e..49da61f6854 100644 --- a/arch/ppc/platforms/4xx/ibm405gpr.c +++ b/arch/ppc/platforms/4xx/ibm405gpr.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gpr.c - * * Author: Armin Kuster * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h index 45412fb4368..e90c5dde01d 100644 --- a/arch/ppc/platforms/4xx/ibm405gpr.h +++ b/arch/ppc/platforms/4xx/ibm405gpr.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gpr.h - * * Author: Armin Kuster * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c index 65ac0b9c2d0..1fed6638c81 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.c +++ b/arch/ppc/platforms/4xx/ibm440ep.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440ep.c - * * PPC440EP I/O descriptions * * Wade Farnsworth diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h index 97c80b8e3e1..61717e8a799 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.h +++ b/arch/ppc/platforms/4xx/ibm440ep.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440ep.h - * * PPC440EP definitions * * Wade Farnsworth diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c index d926245e8b3..b67a72e5c6f 100644 --- a/arch/ppc/platforms/4xx/ibm440gp.c +++ b/arch/ppc/platforms/4xx/ibm440gp.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gp.c - * * PPC440GP I/O descriptions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h index ae1efc03b29..7b2763b6024 100644 --- a/arch/ppc/platforms/4xx/ibm440gp.h +++ b/arch/ppc/platforms/4xx/ibm440gp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gp.h - * * PPC440GP definitions * * Roland Dreier diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c index d24c09ee7b1..685abffcb6c 100644 --- a/arch/ppc/platforms/4xx/ibm440gx.c +++ b/arch/ppc/platforms/4xx/ibm440gx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gx.c - * * PPC440GX I/O descriptions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h index 0b59d8dcd03..070a34efe1c 100644 --- a/arch/ppc/platforms/4xx/ibm440gx.h +++ b/arch/ppc/platforms/4xx/ibm440gx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ibm440gx.h - * * PPC440GX definitions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c index 71a0117d359..de8f7ac5623 100644 --- a/arch/ppc/platforms/4xx/ibm440sp.c +++ b/arch/ppc/platforms/4xx/ibm440sp.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440sp.c - * * PPC440SP I/O descriptions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h index c71e46a18b9..77e8bb22c52 100644 --- a/arch/ppc/platforms/4xx/ibm440sp.h +++ b/arch/ppc/platforms/4xx/ibm440sp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440sp.h - * * PPC440SP definitions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c index a477a78f490..f1dcb0ac15b 100644 --- a/arch/ppc/platforms/4xx/ibmnp405h.c +++ b/arch/ppc/platforms/4xx/ibmnp405h.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmnp405h.c - * * Author: Armin Kuster * * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h index e2c2b06128c..2c683f6aaa6 100644 --- a/arch/ppc/platforms/4xx/ibmnp405h.h +++ b/arch/ppc/platforms/4xx/ibmnp405h.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmnp405h.h - * * Author: Armin Kuster * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c index 7e33bb63544..799a2eccccc 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.c +++ b/arch/ppc/platforms/4xx/ibmstb4.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstb4.c - * * Author: Armin Kuster * * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h index 9f21d4c88a3..9de42659735 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.h +++ b/arch/ppc/platforms/4xx/ibmstb4.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstb4.h - * * Author: Armin Kuster * * 2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c index b895b9cca57..090ddcbecc5 100644 --- a/arch/ppc/platforms/4xx/ibmstbx25.c +++ b/arch/ppc/platforms/4xx/ibmstbx25.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstbx25.c - * * Author: Armin Kuster * * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h index 9a2efc366e9..6884a49d348 100644 --- a/arch/ppc/platforms/4xx/ibmstbx25.h +++ b/arch/ppc/platforms/4xx/ibmstbx25.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstbx25.h - * * Author: Armin Kuster * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c index 21d29132aeb..5c37de28e13 100644 --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/luan.c - * * Luan board specific routines * * Matt Porter diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h index bbe7d0766db..e0db6a810fe 100644 --- a/arch/ppc/platforms/4xx/luan.h +++ b/arch/ppc/platforms/4xx/luan.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/luan.h - * * Luan board definitions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index 4f355b6acab..f841972f1fa 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ocotea.c - * * Ocotea board specific routines * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h index 33251153ac5..7c799a9ff82 100644 --- a/arch/ppc/platforms/4xx/ocotea.h +++ b/arch/ppc/platforms/4xx/ocotea.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ocotea.h - * * Ocotea board definitions * * Matt Porter diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c index 6139a0b3393..1be5d1c8e26 100644 --- a/arch/ppc/platforms/4xx/ppc440spe.c +++ b/arch/ppc/platforms/4xx/ppc440spe.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ppc440spe.c - * * PPC440SPe I/O descriptions * * Roland Dreier diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h index 2216846973b..d3a620ddcde 100644 --- a/arch/ppc/platforms/4xx/ppc440spe.h +++ b/arch/ppc/platforms/4xx/ppc440spe.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440spe.h - * * PPC440SPe definitions * * Roland Dreier diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c index 611ac861804..53da2b4f7c2 100644 --- a/arch/ppc/platforms/4xx/redwood5.c +++ b/arch/ppc/platforms/4xx/redwood5.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood5.c - * * Support for the IBM redwood5 eval board file * * Author: Armin Kuster diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h index 264e34fb3fb..49edd481897 100644 --- a/arch/ppc/platforms/4xx/redwood5.h +++ b/arch/ppc/platforms/4xx/redwood5.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood5.h - * * Macros, definitions, and data structures specific to the IBM PowerPC * STB03xxx "Redwood" evaluation board. * diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c index b1311669128..41b27d106fa 100644 --- a/arch/ppc/platforms/4xx/redwood6.c +++ b/arch/ppc/platforms/4xx/redwood6.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood6.c - * * Author: Armin Kuster * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h index 1814b9f5fc3..1edcbe5c51c 100644 --- a/arch/ppc/platforms/4xx/redwood6.h +++ b/arch/ppc/platforms/4xx/redwood6.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood6.h - * * Macros, definitions, and data structures specific to the IBM PowerPC * STBx25xx "Redwood6" evaluation board. * diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c index 281b4a2ffb9..bab31eb3068 100644 --- a/arch/ppc/platforms/4xx/sycamore.c +++ b/arch/ppc/platforms/4xx/sycamore.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/sycamore.c - * * Architecture- / platform-specific boot-time initialization code for * IBM PowerPC 4xx based boards. * diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h index 1cd6c824fd6..dae01620227 100644 --- a/arch/ppc/platforms/4xx/sycamore.h +++ b/arch/ppc/platforms/4xx/sycamore.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/sycamore.h - * * Sycamore board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c index 74cb33182d9..6bd77902b9a 100644 --- a/arch/ppc/platforms/4xx/walnut.c +++ b/arch/ppc/platforms/4xx/walnut.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/walnut.c - * * Architecture- / platform-specific boot-time initialization code for * IBM PowerPC 4xx based boards. Adapted from original * code by Gary Thomas, Cort Dougan , and Dan Malek diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h index dcf2691698c..f13a577f0a4 100644 --- a/arch/ppc/platforms/4xx/walnut.h +++ b/arch/ppc/platforms/4xx/walnut.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/walnut.h - * * Walnut board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c index 267afb50607..d97a7f269f9 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ b/arch/ppc/platforms/4xx/xilinx_ml300.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/xilinx_ml300.c - * * Xilinx ML300 evaluation board initialization * * Author: MontaVista Software, Inc. diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h index ae8bf1353b0..3d57332ba82 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.h +++ b/arch/ppc/platforms/4xx/xilinx_ml300.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/xilinx_ml300.h - * * Include file that defines the Xilinx ML300 evaluation board * * Author: MontaVista Software, Inc. diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c index b065b8babcd..f287dcdbffc 100644 --- a/arch/ppc/platforms/4xx/yucca.c +++ b/arch/ppc/platforms/4xx/yucca.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/yucca.c - * * Yucca board specific routines * * Roland Dreier (based on luan.c by Matt Porter) diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h index 01a4afea151..7ae23012237 100644 --- a/arch/ppc/platforms/4xx/yucca.h +++ b/arch/ppc/platforms/4xx/yucca.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/yucca.h - * * Yucca board definitions * * Roland Dreier (based on luan.h by Matt Porter) diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c index 1a659bbc186..11626dd9090 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.c +++ b/arch/ppc/platforms/83xx/mpc834x_sys.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/83xx/mpc834x_sys.c - * * MPC834x SYS board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h index 2e514d316fb..aa86c22cdd2 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ b/arch/ppc/platforms/83xx/mpc834x_sys.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/83xx/mpc834x_sys.h - * * MPC834X SYS common board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c index 408d64f18e1..9b014df516b 100644 --- a/arch/ppc/platforms/85xx/mpc8540_ads.c +++ b/arch/ppc/platforms/85xx/mpc8540_ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8540_ads.c - * * MPC8540ADS board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.h b/arch/ppc/platforms/85xx/mpc8540_ads.h index e48ca3a9739..0b5e7ff856f 100644 --- a/arch/ppc/platforms/85xx/mpc8540_ads.h +++ b/arch/ppc/platforms/85xx/mpc8540_ads.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8540_ads.h - * * MPC8540ADS board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc8555_cds.h b/arch/ppc/platforms/85xx/mpc8555_cds.h index 1a8e6c67355..9754dbd5d18 100644 --- a/arch/ppc/platforms/85xx/mpc8555_cds.h +++ b/arch/ppc/platforms/85xx/mpc8555_cds.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mpc8555_cds.h - * * MPC8555CDS board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c index 442c7ff195d..0cb2e86470e 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/arch/ppc/platforms/85xx/mpc8560_ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8560_ads.c - * * MPC8560ADS board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.h b/arch/ppc/platforms/85xx/mpc8560_ads.h index 143ae7eefa7..c2247c21fc5 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.h +++ b/arch/ppc/platforms/85xx/mpc8560_ads.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mpc8560_ads.h - * * MPC8540ADS board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c index 17ce48fe350..8fd9d763f58 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_ads_common.c - * * MPC85xx ADS board common routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h index 198a6a02cde..de8d41aafe1 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_ads_common.h - * * MPC85XX ADS common board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 1801ab392e2..c9e0aeeca3d 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platform/85xx/mpc85xx_cds_common.c - * * MPC85xx CDS board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h index 5b588cfd0e4..62df54f61ae 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_cds_common.h - * * MPC85xx CDS board definitions * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c index 8a72221f816..b73778ecf82 100644 --- a/arch/ppc/platforms/85xx/sbc8560.c +++ b/arch/ppc/platforms/85xx/sbc8560.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc8560.c - * * Wind River SBC8560 board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/sbc8560.h b/arch/ppc/platforms/85xx/sbc8560.h index 5e1b00c77da..44ffaa2d2c8 100644 --- a/arch/ppc/platforms/85xx/sbc8560.h +++ b/arch/ppc/platforms/85xx/sbc8560.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc8560.h - * * Wind River SBC8560 board definitions * * Copyright 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c index c02f110219f..d3ff280510f 100644 --- a/arch/ppc/platforms/85xx/sbc85xx.c +++ b/arch/ppc/platforms/85xx/sbc85xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platform/85xx/sbc85xx.c - * * WindRiver PowerQUICC III SBC85xx board common routines * * Copyright 2002, 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/sbc85xx.h b/arch/ppc/platforms/85xx/sbc85xx.h index 7af93c691a6..5dd8b6a98c9 100644 --- a/arch/ppc/platforms/85xx/sbc85xx.h +++ b/arch/ppc/platforms/85xx/sbc85xx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc85xx.h - * * WindRiver PowerQUICC III SBC85xx common board definitions * * Copyright 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c index 061bb7cf2d9..8d7baa9a397 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.c +++ b/arch/ppc/platforms/85xx/stx_gp3.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/stx_gp3.c - * * STx GP3 board specific routines * * Dan Malek diff --git a/arch/ppc/platforms/85xx/stx_gp3.h b/arch/ppc/platforms/85xx/stx_gp3.h index 2f25b519515..3f71f8f5937 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.h +++ b/arch/ppc/platforms/85xx/stx_gp3.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/stx8560_gp3.h - * * STx GP3 board definitions * * Dan Malek (dan@embeddededge.com) diff --git a/arch/ppc/platforms/85xx/tqm85xx.c b/arch/ppc/platforms/85xx/tqm85xx.c index a5e38ba6273..00af132262b 100644 --- a/arch/ppc/platforms/85xx/tqm85xx.c +++ b/arch/ppc/platforms/85xx/tqm85xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/tqm85xx.c - * * TQM85xx (40/41/55/60) board specific routines * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/85xx/tqm85xx.h b/arch/ppc/platforms/85xx/tqm85xx.h index 3775eb363fd..612d80504f9 100644 --- a/arch/ppc/platforms/85xx/tqm85xx.h +++ b/arch/ppc/platforms/85xx/tqm85xx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/tqm85xx.h - * * TQM85xx (40/41/55/60) board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/apus_setup.c b/arch/ppc/platforms/apus_setup.c index c42c50073da..fe0cdc04d43 100644 --- a/arch/ppc/platforms/apus_setup.c +++ b/arch/ppc/platforms/apus_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/apus_setup.c - * * Copyright (C) 1998, 1999 Jesper Skov * * Basically what is needed to replace functionality found in diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c index aefcc0e7be5..f324f757cae 100644 --- a/arch/ppc/platforms/chestnut.c +++ b/arch/ppc/platforms/chestnut.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chestnut.c - * * Board setup routines for IBM Chestnut * * Author: diff --git a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h index 0400b2be40a..e00fd9f8bbd 100644 --- a/arch/ppc/platforms/chestnut.h +++ b/arch/ppc/platforms/chestnut.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chestnut.h - * * Definitions for IBM 750FXGX Eval (Chestnut) * * Author: diff --git a/arch/ppc/platforms/chrp_pegasos_eth.c b/arch/ppc/platforms/chrp_pegasos_eth.c index 108a6e26518..9305c8aa137 100644 --- a/arch/ppc/platforms/chrp_pegasos_eth.c +++ b/arch/ppc/platforms/chrp_pegasos_eth.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chrp_pegasos_eth.c - * * Copyright (C) 2005 Sven Luther * Thanks to : * Dale Farnsworth diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c index 48996b78737..f9fd3f4f8e2 100644 --- a/arch/ppc/platforms/chrp_setup.c +++ b/arch/ppc/platforms/chrp_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/setup.c - * * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/arch/ppc/platforms/chrp_time.c b/arch/ppc/platforms/chrp_time.c index 57753a55b58..c8627770af1 100644 --- a/arch/ppc/platforms/chrp_time.c +++ b/arch/ppc/platforms/chrp_time.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chrp_time.c - * * Copyright (C) 1991, 1992, 1995 Linus Torvalds * * Adapted for PowerPC (PReP) by Gary Thomas diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c index 6ca7bcac947..55be550a081 100644 --- a/arch/ppc/platforms/cpci690.c +++ b/arch/ppc/platforms/cpci690.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci690.c - * * Board setup routines for the Force CPCI690 board. * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h index 49584c9cedf..0fa5a4c31b6 100644 --- a/arch/ppc/platforms/cpci690.h +++ b/arch/ppc/platforms/cpci690.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci690.h - * * Definitions for Force CPCI690 * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c index ffde8f6f630..6444760caa3 100644 --- a/arch/ppc/platforms/ev64260.c +++ b/arch/ppc/platforms/ev64260.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64260.c - * * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board. * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/ev64260.h b/arch/ppc/platforms/ev64260.h index bedffced3a0..44d90d56745 100644 --- a/arch/ppc/platforms/ev64260.h +++ b/arch/ppc/platforms/ev64260.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64260.h - * * Definitions for Marvell/Galileo EV-64260-BP Evaluation Board. * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c index b9d844f88c2..b5f52eba4fc 100644 --- a/arch/ppc/platforms/ev64360.c +++ b/arch/ppc/platforms/ev64360.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64360.c - * * Board setup routines for the Marvell EV-64360-BP Evaluation Board. * * Author: Lee Nicks diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h index 68eabe49039..b30f4722690 100644 --- a/arch/ppc/platforms/ev64360.h +++ b/arch/ppc/platforms/ev64360.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64360.h - * * Definitions for Marvell EV-64360-BP Evaluation Board. * * Author: Lee Nicks diff --git a/arch/ppc/platforms/gemini.h b/arch/ppc/platforms/gemini.h index 06de5924891..5528fd0a121 100644 --- a/arch/ppc/platforms/gemini.h +++ b/arch/ppc/platforms/gemini.h @@ -1,7 +1,4 @@ /* - * arch/ppc/platforms/gemini.h - * - * * Onboard registers and descriptions for Synergy Microsystems' * "Gemini" boards. * diff --git a/arch/ppc/platforms/gemini_prom.S b/arch/ppc/platforms/gemini_prom.S index 8c5065d5650..b181f210800 100644 --- a/arch/ppc/platforms/gemini_prom.S +++ b/arch/ppc/platforms/gemini_prom.S @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/gemini_prom.S - * * Not really prom support code (yet), but sort of anti-prom code. The current * bootloader does a number of things it shouldn't and doesn't do things that it * should. The stuff in here is mainly a hodge-podge collection of setup code diff --git a/arch/ppc/platforms/gemini_setup.c b/arch/ppc/platforms/gemini_setup.c index 729897c5903..0090ff15460 100644 --- a/arch/ppc/platforms/gemini_setup.c +++ b/arch/ppc/platforms/gemini_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/gemini_setup.c - * * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index 50039a204c2..220674d883d 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c @@ -1,7 +1,4 @@ - /* - * arch/ppc/platforms/hdpu_setup.c - * * Board setup routines for the Sky Computers HDPU Compute Blade. * * Written by Brian Waite diff --git a/arch/ppc/platforms/hdpu.h b/arch/ppc/platforms/hdpu.h index 07c3cffb5c7..f9e020b6970 100644 --- a/arch/ppc/platforms/hdpu.h +++ b/arch/ppc/platforms/hdpu.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/hdpu.h - * * Definitions for Sky Computers HDPU board. * * Brian Waite diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index 6e58e30ceed..d2766617c3c 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/katana.c - * * Board setup routines for the Artesyn Katana cPCI boards. * * Author: Tim Montgomery diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h index 597257eff2e..0a9b036526b 100644 --- a/arch/ppc/platforms/katana.h +++ b/arch/ppc/platforms/katana.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/katana.h - * * Definitions for Artesyn Katana750i/3750 board. * * Author: Tim Montgomery diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c index 7ed52dc340c..5171b53bccb 100644 --- a/arch/ppc/platforms/lite5200.c +++ b/arch/ppc/platforms/lite5200.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lite5200.c - * * Platform support file for the Freescale LITE5200 based on MPC52xx. * A maximum of this file should be moved to syslib/mpc52xx_????? * so that new platform based on MPC52xx need a minimal platform file diff --git a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h index c1de2aa4717..852a18e24d0 100644 --- a/arch/ppc/platforms/lite5200.h +++ b/arch/ppc/platforms/lite5200.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lite5200.h - * * Definitions for Freescale LITE5200 : MPC52xx Standard Development * Platform board support * diff --git a/arch/ppc/platforms/lopec.c b/arch/ppc/platforms/lopec.c index 06d247c23b8..c6445a727ca 100644 --- a/arch/ppc/platforms/lopec.c +++ b/arch/ppc/platforms/lopec.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lopec.c - * * Setup routines for the Motorola LoPEC. * * Author: Dan Cox diff --git a/arch/ppc/platforms/mvme5100.c b/arch/ppc/platforms/mvme5100.c index 108eb182ddd..c717cd92c02 100644 --- a/arch/ppc/platforms/mvme5100.c +++ b/arch/ppc/platforms/mvme5100.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mvme5100.c - * * Board setup routines for the Motorola MVME5100. * * Author: Matt Porter diff --git a/arch/ppc/platforms/pal4.h b/arch/ppc/platforms/pal4.h index 641a11a3165..8569c423d88 100644 --- a/arch/ppc/platforms/pal4.h +++ b/arch/ppc/platforms/pal4.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4.h - * * Definitions for SBS Palomar IV board * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_pci.c b/arch/ppc/platforms/pal4_pci.c index c3b1b757a48..d81ae1c7e1c 100644 --- a/arch/ppc/platforms/pal4_pci.c +++ b/arch/ppc/platforms/pal4_pci.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_pci.c - * * PCI support for SBS Palomar IV * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_serial.h b/arch/ppc/platforms/pal4_serial.h index a715c66e1ad..a75343224cf 100644 --- a/arch/ppc/platforms/pal4_serial.h +++ b/arch/ppc/platforms/pal4_serial.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_serial.h - * * Definitions for SBS PalomarIV serial support * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_setup.c b/arch/ppc/platforms/pal4_setup.c index f93a3f87193..3c3d881df00 100644 --- a/arch/ppc/platforms/pal4_setup.c +++ b/arch/ppc/platforms/pal4_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_setup.c - * * Board setup routines for the SBS PalomarIV. * * Author: Dan Cox diff --git a/arch/ppc/platforms/powerpmc250.c b/arch/ppc/platforms/powerpmc250.c index e6b520e6e13..c3a86be11fb 100644 --- a/arch/ppc/platforms/powerpmc250.c +++ b/arch/ppc/platforms/powerpmc250.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/powerpmc250.c - * * Board setup routines for Force PowerPMC-250 Processor PMC * * Author: Troy Benjegerdes diff --git a/arch/ppc/platforms/pplus.c b/arch/ppc/platforms/pplus.c index 22bd40cfb09..de2761ebe0d 100644 --- a/arch/ppc/platforms/pplus.c +++ b/arch/ppc/platforms/pplus.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pplus.c - * * Board and PCI setup routines for MCG PowerPlus * * Author: Randy Vinson diff --git a/arch/ppc/platforms/pplus.h b/arch/ppc/platforms/pplus.h index 90f0cb2d409..a07cbbdd72c 100644 --- a/arch/ppc/platforms/pplus.h +++ b/arch/ppc/platforms/pplus.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pplus.h - * * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. * * Author: Mark A. Greerinclude/asm-ppc/hawk.h diff --git a/arch/ppc/platforms/pq2ads.c b/arch/ppc/platforms/pq2ads.c index 71c9fca1fe9..3365fd788a7 100644 --- a/arch/ppc/platforms/pq2ads.c +++ b/arch/ppc/platforms/pq2ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pq2ads.c - * * PQ2ADS platform support * * Author: Kumar Gala diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c index d0653580200..a0fc628ffb1 100644 --- a/arch/ppc/platforms/prep_setup.c +++ b/arch/ppc/platforms/prep_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/setup.c - * * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c index 0bb14a5e824..cdd9cfb13ee 100644 --- a/arch/ppc/platforms/prpmc750.c +++ b/arch/ppc/platforms/prpmc750.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/prpmc750_setup.c - * * Board setup routines for Motorola PrPMC750 * * Author: Matt Porter diff --git a/arch/ppc/platforms/prpmc800.c b/arch/ppc/platforms/prpmc800.c index de7baefacd3..e459a199fb1 100644 --- a/arch/ppc/platforms/prpmc800.c +++ b/arch/ppc/platforms/prpmc800.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/prpmc800.c - * * Author: Dale Farnsworth * * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 872c0a3ba3c..1b1e7c5ef15 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/radstone_ppc7d.c - * * Board setup routines for the Radstone PPC7D boards. * * Author: James Chapman diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h index 938375510be..2bb093a0c03 100644 --- a/arch/ppc/platforms/radstone_ppc7d.h +++ b/arch/ppc/platforms/radstone_ppc7d.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/radstone_ppc7d.h - * * Board definitions for the Radstone PPC7D boards. * * Author: James Chapman diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c index 9eeed357230..6dc459decb2 100644 --- a/arch/ppc/platforms/sandpoint.c +++ b/arch/ppc/platforms/sandpoint.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sandpoint_setup.c - * * Board setup routines for the Motorola SPS Sandpoint Test Platform. * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/sandpoint.h b/arch/ppc/platforms/sandpoint.h index f4e982cb69d..3b64e641848 100644 --- a/arch/ppc/platforms/sandpoint.h +++ b/arch/ppc/platforms/sandpoint.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sandpoint.h - * * Definitions for Motorola SPS Sandpoint Test Platform * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c index 74c9ff72c3d..866807b4ad0 100644 --- a/arch/ppc/platforms/sbc82xx.c +++ b/arch/ppc/platforms/sbc82xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sbc82xx.c - * * SBC82XX platform support * * Author: Guy Streeter diff --git a/arch/ppc/platforms/spruce.c b/arch/ppc/platforms/spruce.c index 69e1de7971f..3783deccd9b 100644 --- a/arch/ppc/platforms/spruce.c +++ b/arch/ppc/platforms/spruce.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/spruce.c - * * Board and PCI setup routines for IBM Spruce * * Author: MontaVista Software diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c index 3409139330b..b766339f44a 100644 --- a/arch/ppc/platforms/tqm8260_setup.c +++ b/arch/ppc/platforms/tqm8260_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/tqm8260_setup.c - * * TQM8260 platform support * * Author: Allen Curtis -- cgit v1.2.3 From ebcff3c773b42bce6182ec16485abca4e53fba97 Mon Sep 17 00:00:00 2001 From: Horst Kronstorfer Date: Tue, 21 Feb 2006 23:34:07 -0600 Subject: ppc32: Fix BCSR_SIZE for MPC834x SYS According to the 'MPC8349E MDS Processor Board User Manual Rev. 1.6' the size of the BCSR mapping is 32kb. Signed-off-by: Horst Kronstorfer Signed-off-by: Kumar Gala --- arch/ppc/platforms/83xx/mpc834x_sys.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h index aa86c22cdd2..6727bbdc36e 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ b/arch/ppc/platforms/83xx/mpc834x_sys.h @@ -23,7 +23,7 @@ #define VIRT_IMMRBAR ((uint)0xfe000000) #define BCSR_PHYS_ADDR ((uint)0xf8000000) -#define BCSR_SIZE ((uint)(128 * 1024)) +#define BCSR_SIZE ((uint)(32 * 1024)) #define BCSR_MISC_REG2_OFF 0x07 #define BCSR_MISC_REG2_PORESET 0x01 -- cgit v1.2.3 From d116fe5aeafd8226712d2de9c69428725ca74474 Mon Sep 17 00:00:00 2001 From: Eric Sesterhenn Date: Mon, 6 Mar 2006 21:13:32 +0100 Subject: [PATCH] kzalloc() conversion in arch/ppc This converts arch/ppc to kzalloc usage. Crosscompile tested with allyesconfig. Signed-off-by: Eric Sesterhenn Signed-off-by: Paul Mackerras --- arch/ppc/platforms/katana.c | 3 +-- arch/ppc/platforms/radstone_ppc7d.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index d2766617c3c..6f3bc616174 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -662,12 +662,11 @@ katana_setup_mtd(void) ptbl_entries = (size >= (64*MB)) ? 6 : 4; - if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), + if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition), GFP_KERNEL)) == NULL) { printk(KERN_WARNING "Can't alloc MTD partition table\n"); return -ENOMEM; } - memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition)); ptbl[0].name = "Monitor"; ptbl[0].size = KATANA_MTD_MONITOR_SIZE; diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 1b1e7c5ef15..30188085bd3 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -683,11 +683,10 @@ ppc7d_fixup_i2c_pdata(struct platform_device *pdev) pdata = pdev->dev.platform_data; if (pdata == NULL) { - pdata = kmalloc(sizeof(*pdata), GFP_KERNEL); + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); if (pdata == NULL) return; - memset(pdata, 0, sizeof(*pdata)); pdev->dev.platform_data = pdata; } -- cgit v1.2.3 From bbbe1212bd6f815290f782ba5b489467b54131dc Mon Sep 17 00:00:00 2001 From: Adrian Cox Date: Wed, 8 Mar 2006 22:10:20 +0000 Subject: [PATCH] ppc: Fix platform_notify functions marked __init While adding USB support to an MV64360 based board this week, I discovered that all MV64x60 boards in the kernel have platform_notify functions marked with __init. This causes an oops if a device is added after boot. The patch below removes the __init markers. I do not have all these boards to test on, but the change seems very unlikely to break anything else. Signed-off-by: Adrian Cox Signed-off-by: Paul Mackerras --- arch/ppc/platforms/cpci690.c | 2 +- arch/ppc/platforms/ev64260.c | 2 +- arch/ppc/platforms/ev64360.c | 2 +- arch/ppc/platforms/hdpu.c | 2 +- arch/ppc/platforms/katana.c | 2 +- arch/ppc/platforms/radstone_ppc7d.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c index 55be550a081..790475c22fd 100644 --- a/arch/ppc/platforms/cpci690.c +++ b/arch/ppc/platforms/cpci690.c @@ -288,7 +288,7 @@ cpci690_fixup_mpsc_pdata(struct platform_device *pdev) pdata->brg_clk_freq = cpci690_get_bus_freq(); } -static int __init +static int cpci690_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c index 6444760caa3..31e8e21e1d5 100644 --- a/arch/ppc/platforms/ev64260.c +++ b/arch/ppc/platforms/ev64260.c @@ -414,7 +414,7 @@ ev64260_fixup_mpsc_pdata(struct platform_device *pdev) return; } -static int __init +static int ev64260_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c index b5f52eba4fc..104ac9b16e8 100644 --- a/arch/ppc/platforms/ev64360.c +++ b/arch/ppc/platforms/ev64360.c @@ -298,7 +298,7 @@ ev64360_fixup_eth_pdata(struct platform_device *pdev) } #endif -static int __init +static int ev64360_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index 220674d883d..fc869bb5b2b 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c @@ -351,7 +351,7 @@ static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd) } #endif -static int __init hdpu_platform_notify(struct device *dev) +static int hdpu_platform_notify(struct device *dev) { static struct { char *bus_id; diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index 6f3bc616174..ad21280e892 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -596,7 +596,7 @@ katana_fixup_mv64xxx_pdata(struct platform_device *pdev) } #endif -static int __init +static int katana_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 30188085bd3..bc26b6d71c1 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -709,7 +709,7 @@ ppc7d_fixup_i2c_pdata(struct platform_device *pdev) } #endif -static int __init ppc7d_platform_notify(struct device *dev) +static int ppc7d_platform_notify(struct device *dev) { static struct { char *bus_id; -- cgit v1.2.3 From 898b1920a67048c1f38bb99777f4cff06380a59a Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 9 Mar 2006 23:36:40 -0700 Subject: [PATCH] Fix compile error for ML300/403 Needed due to changes in ppc_sys.c. Signed-off-by: Grant Likely Signed-off-by: Paul Mackerras --- arch/ppc/platforms/4xx/virtex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/ppc/platforms') diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h index 1a01b81cff1..c14325dfd7b 100644 --- a/arch/ppc/platforms/4xx/virtex.h +++ b/arch/ppc/platforms/4xx/virtex.h @@ -27,7 +27,7 @@ /* Device type enumeration for platform bus definitions */ #ifndef __ASSEMBLY__ enum ppc_sys_devices { - VIRTEX_UART, + VIRTEX_UART, NUM_PPC_SYS_DEVS, }; #endif -- cgit v1.2.3