From 1f3b6045f783ee394076ad6dba2d72ecaaecd243 Mon Sep 17 00:00:00 2001 From: Russ Anderson Date: Wed, 31 Oct 2007 11:10:38 -0500 Subject: [IA64] Disable/re-enable CPE interrupts on Altix When the CPE handler encounters too many CPEs (such as a solid single bit memory error), it sets up a polling timer and disables the CPE interrupt (to avoid excessive overhead logging the stream of single bit errors). disable_irq_nosync() calls chip->disable() to provide a chipset specifiec interface for disabling the interrupt. This patch adds the Altix specific support to disable and re-enable the CPE interrupt. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck --- arch/ia64/kernel/mca.c | 2 +- arch/ia64/sn/kernel/irq.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index cc87025e8f5..10b48cd15a8 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c @@ -571,7 +571,7 @@ out: * Outputs * None */ -static void __init +void ia64_mca_register_cpev (int cpev) { /* Register the CPE interrupt vector with SAL */ diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 0f9b12683bf..53351c3cd7b 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved. */ #include @@ -85,12 +85,18 @@ static void sn_shutdown_irq(unsigned int irq) { } +extern void ia64_mca_register_cpev(int); + static void sn_disable_irq(unsigned int irq) { + if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) + ia64_mca_register_cpev(0); } static void sn_enable_irq(unsigned int irq) { + if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) + ia64_mca_register_cpev(irq); } static void sn_ack_irq(unsigned int irq) -- cgit v1.2.3