From 6a05888d713dd915d3268000a479e38646aa423f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 31 May 2007 14:03:45 +0100 Subject: [MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired. Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 44f0a2c1180..a7a17eb9bfc 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void) cpu_cache_init(); tlb_init(); #ifdef CONFIG_MIPS_MT_SMTC + } else if (!secondaryTC) { + /* + * First TC in non-boot VPE must do subset of tlb_init() + * for MMU countrol registers. + */ + write_c0_pagemask(PM_DEFAULT_MASK); + write_c0_wired(0); } #endif /* CONFIG_MIPS_MT_SMTC */ } -- cgit v1.2.3