From c3fb04162a1c8ddcf6caa6e19020da3f0fd23103 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 17 May 2006 16:31:11 +0100 Subject: [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction Patch from Dimitry Andric In arch/arm/mach-s3c2410/sleep.S, the coprocessor registers are saved at suspend time, and restored at resume time. However, an undefined instruction is used when attempting to restore a non-existent "auxiliary control register". This leads to a crash on S3C2412, which has an ARM926 core instead of an ARM920. At suspend time, the following fragment runs: mrc p15, 0, r7, c2, c0, 0 @ translation table base address mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register mrc p15, 0, r9, c1, c0, 0 @ control register and at resume time, the following fragment runs: mcr p15, 0, r7, c2, c0, 0 @ translation table base mcr p15, 0, r8, c1, c1, 0 @ auxilliary control ... mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc There are several problems with these fragments: 1. The ARM920 and ARM926 cores don't have any "auxiliary control register", at least not according to the ARM920 and ARM926 TRM's. 2. The 2nd line of suspend erroneously saves the c2 register again. 3. This saved c2 value is restored using an undefined instruction. For some reason this does not crash on ARM920, but does crash on ARM926. The following patch fixes all these problems. Signed-off-by: Dimitry Andric Yes, this looks sensible Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/sleep.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S index 832fb86a03b..73de2eaca22 100644 --- a/arch/arm/mach-s3c2410/sleep.S +++ b/arch/arm/mach-s3c2410/sleep.S @@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend) mrc p15, 0, r5, c13, c0, 0 @ PID mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 0 @ translation table base address - mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register - mrc p15, 0, r9, c1, c0, 0 @ control register + mrc p15, 0, r8, c1, c0, 0 @ control register stmia r0, { r4 - r13 } @@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume) mcr p15, 0, r5, c13, c0, 0 @ PID mcr p15, 0, r6, c3, c0, 0 @ Domain ID mcr p15, 0, r7, c2, c0, 0 @ translation table base - mcr p15, 0, r8, c1, c1, 0 @ auxilliary control #ifdef CONFIG_DEBUG_RESUME mov r3, #'R' @@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume) #endif ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc + mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc nop @ second-to-last before mmu mov pc, r2 @ go back to virtual address -- cgit v1.2.3 From ec64152fee25e2a63f06d40d32c7b4cb62eab9a3 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 17 May 2006 20:14:29 +0100 Subject: [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia Patch from Thomas Gleixner The mainstone board pcmcia interrupt have been enabled via setup_irq() and the following socket check calls enable_irq again. Set the NOAUTOEN flag so the interrupt is not automatically enabled in setup_irq() Signed-off-by: Thomas Gleixner Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/mach-pxa/mainstone.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 98356f81000..02e188d98e7 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void) for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { set_irq_chip(irq, &mainstone_irq_chip); set_irq_handler(irq, do_level_IRQ); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); + else + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } set_irq_flags(MAINSTONE_IRQ(8), 0); set_irq_flags(MAINSTONE_IRQ(12), 0); -- cgit v1.2.3