From 4ed0d3e6c64cfd9ba4ceb2099b10d1cf8ece4320 Mon Sep 17 00:00:00 2001 From: Fenghua Yu Date: Fri, 24 Apr 2009 17:30:20 -0700 Subject: Intel IOMMU Pass Through Support The patch adds kernel parameter intel_iommu=pt to set up pass through mode in context mapping entry. This disables DMAR in linux kernel; but KVM still runs on VT-d and interrupt remapping still works. In this mode, kernel uses swiotlb for DMA API functions but other VT-d functionalities are enabled for KVM. KVM always uses multi level translation page table in VT-d. By default, pass though mode is disabled in kernel. This is useful when people don't want to enable VT-d DMAR in kernel but still want to use KVM and interrupt remapping for reasons like DMAR performance concern or debug purpose. Signed-off-by: Fenghua Yu Acked-by: Weidong Han Signed-off-by: David Woodhouse --- arch/ia64/include/asm/iommu.h | 1 + arch/ia64/kernel/pci-swiotlb.c | 2 +- arch/x86/include/asm/iommu.h | 1 + arch/x86/kernel/pci-dma.c | 6 ++++++ arch/x86/kernel/pci-swiotlb.c | 3 ++- 5 files changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 0490794fe4a..37d41ca5645 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -9,6 +9,7 @@ extern void pci_iommu_shutdown(void); extern void no_iommu_init(void); extern int force_iommu, no_iommu; extern int iommu_detected; +extern int iommu_pass_through; extern void iommu_dma_init(void); extern void machvec_init(const char *name); diff --git a/arch/ia64/kernel/pci-swiotlb.c b/arch/ia64/kernel/pci-swiotlb.c index 285aae8431c..223abb13410 100644 --- a/arch/ia64/kernel/pci-swiotlb.c +++ b/arch/ia64/kernel/pci-swiotlb.c @@ -46,7 +46,7 @@ void __init swiotlb_dma_init(void) void __init pci_swiotlb_init(void) { - if (!iommu_detected) { + if (!iommu_detected || iommu_pass_through) { #ifdef CONFIG_IA64_GENERIC swiotlb = 1; printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n"); diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index af326a2975b..fd6d21bbee6 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -6,6 +6,7 @@ extern void no_iommu_init(void); extern struct dma_map_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; +extern int iommu_pass_through; /* 10 seconds */ #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 745579bc825..8cad0d85424 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -160,6 +160,8 @@ again: return page_address(page); } +extern int iommu_pass_through; + /* * See for the iommu kernel parameter * documentation. @@ -209,6 +211,10 @@ static __init int iommu_setup(char *p) #ifdef CONFIG_SWIOTLB if (!strncmp(p, "soft", 4)) swiotlb = 1; + if (!strncmp(p, "pt", 2)) { + iommu_pass_through = 1; + return 1; + } #endif gart_parse_options(p); diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c index 221a3853e26..3a0c51e0ba6 100644 --- a/arch/x86/kernel/pci-swiotlb.c +++ b/arch/x86/kernel/pci-swiotlb.c @@ -71,7 +71,8 @@ void __init pci_swiotlb_init(void) { /* don't initialize swiotlb if iommu=off (no_iommu=1) */ #ifdef CONFIG_X86_64 - if (!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN) + if ((!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN) || + iommu_pass_through) swiotlb = 1; #endif if (swiotlb_force) -- cgit v1.2.3 From aed5d5f4c5ea5da01a774e42cff08c4b4fa59072 Mon Sep 17 00:00:00 2001 From: Fenghua Yu Date: Thu, 30 Apr 2009 17:57:11 -0700 Subject: Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support This updated patch should fix the compiling errors and remove the extern iommu_pass_through from drivers/pci/intel-iommu.c file. Signed-off-by: Fenghua Yu Signed-off-by: David Woodhouse --- arch/ia64/kernel/pci-dma.c | 2 ++ arch/x86/kernel/pci-dma.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c index eb987386f69..ecdde25d0d1 100644 --- a/arch/ia64/kernel/pci-dma.c +++ b/arch/ia64/kernel/pci-dma.c @@ -32,6 +32,8 @@ int force_iommu __read_mostly = 1; int force_iommu __read_mostly; #endif +int iommu_pass_through; + /* Dummy device used for NULL arguments (normally ISA). Better would be probably a smaller DMA mask, but this is bug-to-bug compatible to i386. */ diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 8cad0d85424..049005e8217 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -32,6 +32,8 @@ int no_iommu __read_mostly; /* Set this to 1 if there is a HW IOMMU in the system */ int iommu_detected __read_mostly = 0; +int iommu_pass_through; + dma_addr_t bad_dma_address __read_mostly = 0; EXPORT_SYMBOL(bad_dma_address); @@ -160,8 +162,6 @@ again: return page_address(page); } -extern int iommu_pass_through; - /* * See for the iommu kernel parameter * documentation. -- cgit v1.2.3 From ee1ca48fae7e575d5e399d4fdcfe0afc1212a64c Mon Sep 17 00:00:00 2001 From: "Pallipadi, Venkatesh" Date: Thu, 21 May 2009 17:09:10 -0700 Subject: ACPI: Disable ARB_DISABLE on platforms where it is not needed ARB_DISABLE is a NOP on all of the recent Intel platforms. For such platforms, reduce contention on c3_lock by skipping the fake ARB_DISABLE. Signed-off-by: Venkatesh Pallipadi Signed-off-by: Len Brown --- arch/x86/kernel/acpi/cstate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index bbbe4bbb6f3..8c44c232efc 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -34,12 +34,22 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, flags->bm_check = 1; else if (c->x86_vendor == X86_VENDOR_INTEL) { /* - * Today all CPUs that support C3 share cache. - * TBD: This needs to look at cache shared map, once - * multi-core detection patch makes to the base. + * Today all MP CPUs that support C3 share cache. + * And caches should not be flushed by software while + * entering C3 type state. */ flags->bm_check = 1; } + + /* + * On all recent Intel platforms, ARB_DISABLE is a nop. + * So, set bm_control to zero to indicate that ARB_DISABLE + * is not required while entering C3 type state on + * P4, Core and beyond CPUs + */ + if (c->x86_vendor == X86_VENDOR_INTEL && + (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14))) + flags->bm_control = 0; } EXPORT_SYMBOL(acpi_processor_power_init_bm_check); -- cgit v1.2.3 From fb6ea3258742f41be8dd527ebd58a1a1e2cef23a Mon Sep 17 00:00:00 2001 From: Nelson Castillo Date: Sun, 10 May 2009 15:41:32 -0500 Subject: [MTD] [NAND] S3C2410: Small colon cleanup checkpatch would complain with "disable_ecc : 1". Signed-off-by: Nelson Castillo [ben-linux@fluff.org: subject cleanup] Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/nand.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index f4dcd14af05..985546750c6 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h @@ -22,7 +22,7 @@ */ struct s3c2410_nand_set { - unsigned int disable_ecc : 1; + unsigned int disable_ecc:1; int nr_chips; int nr_partitions; @@ -39,7 +39,7 @@ struct s3c2410_platform_nand { int twrph0; /* active time for nWE/nOE */ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ - unsigned int ignore_unset_ecc : 1; + unsigned int ignore_unset_ecc:1; int nr_sets; struct s3c2410_nand_set *sets; -- cgit v1.2.3 From 6a4123e581b3112ff4ea7439ab9ae5cb271a9dbd Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 21 Apr 2009 19:58:13 -0700 Subject: mtd: nand: davinci_nand, 4-bit ECC for smallpage Minimal support for the 4-bit ECC engine found on DM355, DM365, DA830/OMAP-L137, and similar recent DaVinci-family chips. This is limited to small-page flash for now; there are some page layout issues for large page chips. Note that most boards using this engine (like the DM355 EVM) include 2GiB large page chips. Sanity tested on DM355 EVM after swapping the socketed NAND for a small-page one. Signed-off-by: David Brownell Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- arch/arm/mach-davinci/include/mach/nand.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index aa482841270..b520c4b5678 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */ /* none == NAND_ECC_NONE (strongly *not* advised!!) * soft == NAND_ECC_SOFT - * 1-bit == NAND_ECC_HW - * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips) + * else == NAND_ECC_HW, according to ecc_bits + * + * All DaVinci-family chips support 1-bit hardware ECC. + * Newer ones also support 4-bit ECC, but are awkward + * using it with large page chips. */ nand_ecc_modes_t ecc_mode; + u8 ecc_bits; /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ unsigned options; -- cgit v1.2.3 From 008fe148cb0fb51d266baabe2c09997b21cf90c6 Mon Sep 17 00:00:00 2001 From: "Luck, Tony" Date: Tue, 26 May 2009 15:45:12 -0700 Subject: intel-iommu: Fix one last ia64 build problem in Pass Through Support On ia64 with CONFIG_DMAR=n and CONFIG_SWIOTLB=y (as used in arch/ia64/configs/tiger_defconfig) there is still a link error with iommu_pass_through listed as an undefined symbol: arch/ia64/kernel/built-in.o: In function `pci_swiotlb_init': (.init.text+0x7f70): undefined reference to `iommu_pass_through' Fix it by #defining iommu_pass_through away in asm/iommu.h Signed-off-by: Tony Luck Signed-off-by: David Woodhouse --- arch/ia64/include/asm/iommu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 37d41ca5645..745e095fe82 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -9,7 +9,11 @@ extern void pci_iommu_shutdown(void); extern void no_iommu_init(void); extern int force_iommu, no_iommu; extern int iommu_detected; +#ifdef CONFIG_DMAR extern int iommu_pass_through; +#else +#define iommu_pass_through (0) +#endif extern void iommu_dma_init(void); extern void machvec_init(const char *name); -- cgit v1.2.3 From b0903ee8e4853eea35cb24cfb4dda1b60c7948dc Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Mon, 8 Jun 2009 13:04:43 +0200 Subject: CRIS: assignment/is equal confusion Somehow, the assignments of rw->lock got written as comparisons. The effect probably was that the read-write spinlocks never locked. However, since the locks are only used in CONFIG_SMP and SMP CRIS is experimental, it has never been identified as a problem. Signed-off-by: Roel Kluin Acked-by: Jesper Nilsson --- arch/cris/include/arch-v32/arch/spinlock.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/cris/include/arch-v32/arch/spinlock.h b/arch/cris/include/arch-v32/arch/spinlock.h index 129756b9666..367a53ea10c 100644 --- a/arch/cris/include/arch-v32/arch/spinlock.h +++ b/arch/cris/include/arch-v32/arch/spinlock.h @@ -78,7 +78,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) { __raw_spin_lock(&rw->slock); while (rw->lock != RW_LOCK_BIAS); - rw->lock == 0; + rw->lock = 0; __raw_spin_unlock(&rw->slock); } @@ -93,7 +93,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) { __raw_spin_lock(&rw->slock); while (rw->lock != RW_LOCK_BIAS); - rw->lock == RW_LOCK_BIAS; + rw->lock = RW_LOCK_BIAS; __raw_spin_unlock(&rw->slock); } @@ -114,7 +114,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) int ret = 0; __raw_spin_lock(&rw->slock); if (rw->lock == RW_LOCK_BIAS) { - rw->lock == 0; + rw->lock = 0; ret = 1; } __raw_spin_unlock(&rw->slock); -- cgit v1.2.3 From a4536b19df92adda215f6fc225b52dc4cee4cf83 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 13 May 2009 16:54:13 +0100 Subject: [MTD] [NAND] S3C2410: Added a kerneldoc for s3c2410_nand_set Converted the old comnent to kerneldoc. Signed-off-by: Michel Pollet [ben-linux@fluff.org: updated subject, spello fix] Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/nand.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index 985546750c6..93565166496 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h @@ -10,17 +10,19 @@ * published by the Free Software Foundation. */ -/* struct s3c2410_nand_set +/** + * struct s3c2410_nand_set - define a set of one or more nand chips + * @disable_ecc: Entirely disable ECC - Dangerous + * @nr_chips: Number of chips in this set + * @nr_partitions: Number of partitions pointed to by @partitions + * @name: Name of set (optional) + * @nr_map: Map for low-layer logical to physical chip numbers (option) + * @partitions: The mtd partition list * - * define an set of one or more nand chips registered with an unique mtd - * - * nr_chips = number of chips in this set - * nr_partitions = number of partitions pointed to be partitoons (or zero) - * name = name of set (optional) - * nr_map = map for low-layer logical to physical chip numbers (option) - * partitions = mtd partition list -*/ - + * define a set of one or more nand chips registered with an unique mtd. Also + * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger + * a warning at boot time. + */ struct s3c2410_nand_set { unsigned int disable_ecc:1; -- cgit v1.2.3 From 9db41f9edcb87ae050fcb171c44be7f212728d54 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 13 May 2009 16:54:14 +0100 Subject: [MTD] [NAND] S3C2410: Allow the machine code to get the BBT table from NAND Added a flag to allow the machine code to tell the NAND subsystem that it should try to pickup a BBT from the flash, and also skip the NAND full scan at startup. Signed-off-by: Michel Pollet Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/nand.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index 93565166496..18f958801e6 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h @@ -13,6 +13,10 @@ /** * struct s3c2410_nand_set - define a set of one or more nand chips * @disable_ecc: Entirely disable ECC - Dangerous + * @flash_bbt: Openmoko u-boot can create a Bad Block Table + * Setting this flag will allow the kernel to + * look for it at boot time and also skip the NAND + * scan. * @nr_chips: Number of chips in this set * @nr_partitions: Number of partitions pointed to by @partitions * @name: Name of set (optional) @@ -25,6 +29,7 @@ */ struct s3c2410_nand_set { unsigned int disable_ecc:1; + unsigned int flash_bbt:1; int nr_chips; int nr_partitions; -- cgit v1.2.3 From 7f2ff23db1de53ea8695bb4a7c1cfab88886e3fd Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Wed, 10 Jun 2009 15:06:55 +0200 Subject: CRISv32: Add arch optimized strcmp. Add an optimized strcmp for CRISv32. This improves strcmp performance with about 25% when comparing a 55 character string with itself. Signed-off-by: Edgar Iglesias Acked-by: Jesper Nilsson --- arch/cris/arch-v32/lib/Makefile | 2 +- arch/cris/arch-v32/lib/strcmp.S | 21 +++++++++++++++++++++ arch/cris/include/asm/string.h | 6 ++++++ 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 arch/cris/arch-v32/lib/strcmp.S (limited to 'arch') diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile index eb4aad1f115..dd296b9db03 100644 --- a/arch/cris/arch-v32/lib/Makefile +++ b/arch/cris/arch-v32/lib/Makefile @@ -3,5 +3,5 @@ # lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ - csumcpfruser.o spinlock.o delay.o + csumcpfruser.o spinlock.o delay.o strcmp.o diff --git a/arch/cris/arch-v32/lib/strcmp.S b/arch/cris/arch-v32/lib/strcmp.S new file mode 100644 index 00000000000..8f7a1ee6259 --- /dev/null +++ b/arch/cris/arch-v32/lib/strcmp.S @@ -0,0 +1,21 @@ +; strcmp.S -- CRISv32 version. +; Copyright (C) 2008 AXIS Communications AB +; Written by Edgar E. Iglesias +; +; This source code is licensed under the GNU General Public License, +; Version 2. See the file COPYING for more details. + + .global strcmp + .type strcmp,@function +strcmp: +1: + move.b [$r10+], $r12 + seq $r13 + sub.b [$r11+], $r12 + or.b $r12, $r13 + beq 1b + nop + + ret + movs.b $r12, $r10 + .size strcmp, . - strcmp diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h index 691190e99a2..d5db39f9eea 100644 --- a/arch/cris/include/asm/string.h +++ b/arch/cris/include/asm/string.h @@ -11,4 +11,10 @@ extern void *memcpy(void *, const void *, size_t); #define __HAVE_ARCH_MEMSET extern void *memset(void *, int, size_t); +#ifdef CONFIG_ETRAX_ARCH_V32 +/* For v32 we provide strcmp. */ +#define __HAVE_ARCH_STRCMP +extern int strcmp(const char *s1, const char *s2); +#endif + #endif -- cgit v1.2.3 From 91a120d03fd901fc8b95e85af7903358c5862d65 Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Thu, 11 Jun 2009 19:09:00 +0200 Subject: CRISv32: Fix potential null reference in cryptocop driver. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code didn't test the pointer to the newly allocated memory, but a parameter sent in as value. Since the input parameter was most often set, the code would have used a null pointer if the kmalloc failed. If the input parameter was not set, the code would leak the allocated buffer. http://bugzilla.kernel.org/show_bug.cgi?id=11363 Reported-by: Daniel Marjamäki Signed-off-by: Jesper Nilsson --- arch/cris/arch-v32/drivers/cryptocop.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index 67c61ea8681..fd529a0ec75 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -1395,7 +1395,7 @@ static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; + if (!p) return -ENOMEM; *p = 0x80; memset(p+1, 0, padlen - 1); @@ -1427,7 +1427,7 @@ static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, cha if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; + if (!p) return -ENOMEM; *p = 0x80; memset(p+1, 0, padlen - 1); -- cgit v1.2.3 From 768c31495abe49227a96261b5aa19f34b30882b1 Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Wed, 10 Jun 2009 11:45:47 +0200 Subject: CRISv32: irq.c - Move end brace outside #endif The end brace for a larger for statement was placed inside the #else part of #ifdef TIMER_VECT1. However, for all current chips, the define TIMER_VECT1 is always unset, and the error was never triggered. Move the brace down below the #endif. Fixes: http://bugzilla.kernel.org/show_bug.cgi?id=13476 Reported-by: Martin Ettl Signed-off-by: Jesper Nilsson Acked-by: Mikael Starvik --- arch/cris/arch-v32/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index df3925cb1c7..9c9eb5b708f 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -428,8 +428,8 @@ crisv32_do_multiple(struct pt_regs* regs) masked[i] &= ~TIMER_MASK; do_IRQ(TIMER0_INTR_VECT, regs); } - } #endif + } #ifdef IGNORE_MASK /* Remove IRQs that can't be handled as multiple. */ -- cgit v1.2.3 From 1f82de10d6b1d845155363c895c552e61b36b51a Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Thu, 23 Apr 2009 20:48:32 -0700 Subject: PCI/x86: don't assume prefetchable ranges are 64bit We should not assign 64bit ranges to PCI devices that only take 32bit prefetchable addresses. Try to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge and make the bus resource only have that bit set when all devices under it support 64bit prefetchable memory. Use that flag to allocate resources from that range. Reported-by: Yannick Reviewed-by: Ivan Kokshaysky Signed-off-by: Yinghai Lu Signed-off-by: Jesse Barnes --- arch/x86/include/asm/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index b51a1e8b0ba..927958d13c1 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -130,6 +130,7 @@ extern void pci_iommu_alloc(void); /* generic pci stuff */ #include +#define PCIBIOS_MAX_MEM_32 0xffffffff #ifdef CONFIG_NUMA /* Returns the node based on pci bus */ -- cgit v1.2.3 From 9e9f46c44e487af0a82eb61b624553e2f7118f5b Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 11 Jun 2009 10:58:28 -0700 Subject: PCI: use ACPI _CRS data by default At this point, it seems to solve more problems than it causes, so let's try using it by default. It's an easy revert if it ends up causing trouble. Reviewed-by: Yinghai Lu Acked-by: Bjorn Helgaas Signed-off-by: Jesse Barnes --- arch/x86/include/asm/pci_x86.h | 2 +- arch/x86/pci/acpi.c | 2 +- arch/x86/pci/amd_bus.c | 2 +- arch/x86/pci/common.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index e60fd3e14bd..cb739cc0a08 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -25,7 +25,7 @@ #define PCI_BIOS_IRQ_SCAN 0x2000 #define PCI_ASSIGN_ALL_BUSSES 0x4000 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 -#define PCI_USE__CRS 0x10000 +#define PCI_NO_ROOT_CRS 0x10000 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 #define PCI_HAS_IO_ECS 0x40000 #define PCI_NOASSIGN_ROMS 0x80000 diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index c0ecf250fe5..8d898e0d360 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -217,7 +217,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do #endif } - if (bus && (pci_probe & PCI_USE__CRS)) + if (bus && !(pci_probe & PCI_NO_ROOT_CRS)) get_current_resources(device, busnum, domain, bus); return bus; } diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index f893d6a6e80..2255f880678 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -101,7 +101,7 @@ void x86_pci_root_bus_res_quirks(struct pci_bus *b) struct pci_root_info *info; /* don't go for it if _CRS is used */ - if (pci_probe & PCI_USE__CRS) + if (!(pci_probe & PCI_NO_ROOT_CRS)) return; /* if only one root bus, don't need to anything */ diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 2202b6257b8..4740119e4bb 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -515,8 +515,8 @@ char * __devinit pcibios_setup(char *str) } else if (!strcmp(str, "assign-busses")) { pci_probe |= PCI_ASSIGN_ALL_BUSSES; return NULL; - } else if (!strcmp(str, "use_crs")) { - pci_probe |= PCI_USE__CRS; + } else if (!strcmp(str, "nocrs")) { + pci_probe |= PCI_NO_ROOT_CRS; return NULL; } else if (!strcmp(str, "earlydump")) { pci_early_dump_regs = 1; -- cgit v1.2.3 From c636f753b5b943f08fb3490e7f1a9b47aa5cc7d3 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Tue, 19 May 2009 23:47:38 -0400 Subject: ACPI: delete dead acpi_disabled setting code Testing CONFIG_ACPI inside boot.c is a waste of text, since boot.c is built only when CONFIG_ACPI=y Signed-off-by: Len Brown --- arch/x86/kernel/acpi/boot.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 723989d7f80..d4acedf0786 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -43,11 +43,7 @@ static int __initdata acpi_force = 0; u32 acpi_rsdt_forced; -#ifdef CONFIG_ACPI -int acpi_disabled = 0; -#else -int acpi_disabled = 1; -#endif +int acpi_disabled; EXPORT_SYMBOL(acpi_disabled); #ifdef CONFIG_X86_64 -- cgit v1.2.3 From d023e49118b9c93bbab9aaf798b25f78f1a5803c Mon Sep 17 00:00:00 2001 From: Olivier Berger Date: Thu, 21 May 2009 16:07:38 +0200 Subject: ACPI: Remove Asus P4B266 from blacklist See http://marc.info/?l=linux-acpi&m=124068823904429&w=2 for discussion Signed-off-by: Olivier Berger Signed-off-by: Len Brown --- arch/x86/kernel/acpi/boot.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index d4acedf0786..817d6a5e115 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1563,14 +1563,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "Workstation W8000"), }, }, - { - .callback = force_acpi_ht, - .ident = "ASUS P4B266", - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), - DMI_MATCH(DMI_BOARD_NAME, "P4B266"), - }, - }, { .callback = force_acpi_ht, .ident = "ASUS P2B-DS", -- cgit v1.2.3 From c4bf2f372db09ef8d16a25a60d523bfa1c50f7b5 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Thu, 11 Jun 2009 23:53:55 -0400 Subject: ACPI, PCI, x86: move MCFG parsing routine from ACPI to PCI file Move arch/x86/kernel/acpi/boot.c: acpi_parse_mcfg() to arch/x86/pci/mmconfig-shared.c: pci_parse_mcfg() where it is used, and make it static. Move associated globals and helper routine with it. No functional change. This code move is in preparation for SFI support, which will allow the PCI code to find the MCFG table on systems which do not support ACPI. Signed-off-by: Len Brown Acked-by: Jesse Barnes --- arch/x86/include/asm/pci_x86.h | 3 ++ arch/x86/kernel/acpi/boot.c | 66 ------------------------------------------ arch/x86/pci/mmconfig-shared.c | 65 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 67 insertions(+), 67 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index e60fd3e14bd..b399988eee3 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -121,6 +121,9 @@ extern int __init pcibios_init(void); extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); +extern struct acpi_mcfg_allocation *pci_mmcfg_config; +extern int pci_mmcfg_config_num; + /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space * on their northbrige except through the * %eax register. As such, you MUST diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 817d6a5e115..f54e0e557cd 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -117,72 +117,6 @@ void __init __acpi_unmap_table(char *map, unsigned long size) early_iounmap(map, size); } -#ifdef CONFIG_PCI_MMCONFIG - -static int acpi_mcfg_64bit_base_addr __initdata = FALSE; - -/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ -struct acpi_mcfg_allocation *pci_mmcfg_config; -int pci_mmcfg_config_num; - -static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) -{ - if (!strcmp(mcfg->header.oem_id, "SGI")) - acpi_mcfg_64bit_base_addr = TRUE; - - return 0; -} - -int __init acpi_parse_mcfg(struct acpi_table_header *header) -{ - struct acpi_table_mcfg *mcfg; - unsigned long i; - int config_size; - - if (!header) - return -EINVAL; - - mcfg = (struct acpi_table_mcfg *)header; - - /* how many config structures do we have */ - pci_mmcfg_config_num = 0; - i = header->length - sizeof(struct acpi_table_mcfg); - while (i >= sizeof(struct acpi_mcfg_allocation)) { - ++pci_mmcfg_config_num; - i -= sizeof(struct acpi_mcfg_allocation); - }; - if (pci_mmcfg_config_num == 0) { - printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); - return -ENODEV; - } - - config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); - pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); - if (!pci_mmcfg_config) { - printk(KERN_WARNING PREFIX - "No memory for MCFG config tables\n"); - return -ENOMEM; - } - - memcpy(pci_mmcfg_config, &mcfg[1], config_size); - - acpi_mcfg_oem_check(mcfg); - - for (i = 0; i < pci_mmcfg_config_num; ++i) { - if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && - !acpi_mcfg_64bit_base_addr) { - printk(KERN_ERR PREFIX - "MMCONFIG not in low 4GB of memory\n"); - kfree(pci_mmcfg_config); - pci_mmcfg_config_num = 0; - return -ENODEV; - } - } - - return 0; -} -#endif /* CONFIG_PCI_MMCONFIG */ - #ifdef CONFIG_X86_LOCAL_APIC static int __init acpi_parse_madt(struct acpi_table_header *table) { diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 8766b0e216c..712443ec6d4 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -523,6 +523,69 @@ reject: static int __initdata known_bridge; +static int acpi_mcfg_64bit_base_addr __initdata = FALSE; + +/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ +struct acpi_mcfg_allocation *pci_mmcfg_config; +int pci_mmcfg_config_num; + +static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) +{ + if (!strcmp(mcfg->header.oem_id, "SGI")) + acpi_mcfg_64bit_base_addr = TRUE; + + return 0; +} + +static int __init pci_parse_mcfg(struct acpi_table_header *header) +{ + struct acpi_table_mcfg *mcfg; + unsigned long i; + int config_size; + + if (!header) + return -EINVAL; + + mcfg = (struct acpi_table_mcfg *)header; + + /* how many config structures do we have */ + pci_mmcfg_config_num = 0; + i = header->length - sizeof(struct acpi_table_mcfg); + while (i >= sizeof(struct acpi_mcfg_allocation)) { + ++pci_mmcfg_config_num; + i -= sizeof(struct acpi_mcfg_allocation); + }; + if (pci_mmcfg_config_num == 0) { + printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); + return -ENODEV; + } + + config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); + pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); + if (!pci_mmcfg_config) { + printk(KERN_WARNING PREFIX + "No memory for MCFG config tables\n"); + return -ENOMEM; + } + + memcpy(pci_mmcfg_config, &mcfg[1], config_size); + + acpi_mcfg_oem_check(mcfg); + + for (i = 0; i < pci_mmcfg_config_num; ++i) { + if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && + !acpi_mcfg_64bit_base_addr) { + printk(KERN_ERR PREFIX + "MMCONFIG not in low 4GB of memory\n"); + kfree(pci_mmcfg_config); + pci_mmcfg_config_num = 0; + return -ENODEV; + } + } + + return 0; +} + static void __init __pci_mmcfg_init(int early) { /* MMCONFIG disabled */ @@ -543,7 +606,7 @@ static void __init __pci_mmcfg_init(int early) } if (!known_bridge) - acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); + acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); pci_mmcfg_reject_broken(early); -- cgit v1.2.3 From ab46feae865c5b96dbf5e261be8638165932bfb1 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Fri, 12 Jun 2009 20:47:50 -0400 Subject: ACPI: #define acpi_disabled 1 for CONFIG_ACPI=n SFI will need to test acpi_disabled no matter the value of CONFIG_ACPI. Signed-off-by: Len Brown --- arch/x86/include/asm/acpi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 4518dc50090..20d1465a2ab 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -144,6 +144,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) #else /* !CONFIG_ACPI */ +#define acpi_disabled 1 #define acpi_lapic 0 #define acpi_ioapic 0 static inline void acpi_noirq_set(void) { } -- cgit v1.2.3 From 97f8a27a5cfb08c9ce3abc90aaafb791759aed94 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Thu, 11 Jun 2009 22:51:12 -0400 Subject: [ARM] orion5x: increment window counter after adding sram mapping Without incrementing the counter the next window setup will overwrite the SRAM mapping. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/addr-map.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 6f3f77d031d..d78731edebb 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) int __init orion5x_setup_sram_win(void) { - return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, + return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); } -- cgit v1.2.3 From 3fade49b734cca2d8c4f1bcd7c3023302b557f3b Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 11 Jun 2009 22:27:20 +0200 Subject: [ARM] orion5x: register the crypto device on SOCs that support it Not all Orion variants do implement the crypto unit. Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion5x/common.c | 10 +++++++++- arch/arm/mach-orion5x/common.h | 1 - 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index eafcc49009e..f87fa125380 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = { .resource = orion5x_crypto_res, }; -int __init orion5x_crypto_init(void) +static int __init orion5x_crypto_init(void) { int ret; @@ -696,6 +696,14 @@ void __init orion5x_init(void) disable_hlt(); } + /* + * The 5082/5181l/5182/6082/6082l/6183 have crypto + * while 5180n/5181/5281 don't have crypto. + */ + if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || + dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) + orion5x_crypto_init(); + /* * Register watchdog driver */ diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index de483e83edd..8f004503c96 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -38,7 +38,6 @@ void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); void orion5x_xor_init(void); -int orion5x_crypto_init(void); /* * PCIe/PCI functions. -- cgit v1.2.3 From 5102aa4acdbde305646ae60c5eec7042b5016a0e Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 25 Mar 2009 17:19:14 +0000 Subject: [ARM] MINI2440: Add machine support The MINI2440 is a chinese made s3c2440 development board with a large set of peripherals. This patch provides machine support for almost all the features of the board. Since it can come with various "options" fitted, a kernel parameter is used to specify the lcd size, backlight control and touchscreen. Signed-off-by: Michel Pollet Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/Kconfig | 10 + arch/arm/mach-s3c2440/Makefile | 1 + arch/arm/mach-s3c2440/mach-mini2440.c | 706 ++++++++++++++++++++++++++++++++++ 3 files changed, 717 insertions(+) create mode 100644 arch/arm/mach-s3c2440/mach-mini2440.c (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 5df73cbf2b4..8cfeaec3730 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -84,5 +84,15 @@ config MACH_AT2440EVB help Say Y here if you are using the AT2440EVB development board +config MACH_MINI2440 + bool "MINI2440 development board" + select CPU_S3C2440 + select EEPROM_AT24 + select LEDS_TRIGGER_BACKLIGHT + select SND_S3C24XX_SOC_S3C24XX_UDA134X + help + Say Y here to select support for the MINI2440. Is a 10cm x 10cm board + available via various sources. It can come with a 3.5" or 7" touch LCD. + endmenu diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index 0b4440e79b9..bfadcf684a2 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o +obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c new file mode 100644 index 00000000000..eb4b24501a9 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -0,0 +1,706 @@ +/* linux/arch/arm/mach-s3c2440/mach-mini2440.c + * + * Copyright (c) 2008 Ramax Lo + * Based on mach-anubis.c by Ben Dooks + * and modifications by SBZ and + * Weibing and + * Michel Pollet + * + * For product information, visit http://code.google.com/p/mini2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) + +static struct map_desc mini2440_iodesc[] __initdata = { + /* nothing to declare, move along */ +}; + +#define UCON S3C2410_UCON_DEFAULT +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + + +static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +/* USB device UDC support */ + +static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) +{ + pr_debug("udc: pullup(%d)\n", cmd); + + switch (cmd) { + case S3C2410_UDC_P_ENABLE : + s3c2410_gpio_setpin(S3C2410_GPC(5), 1); + break; + case S3C2410_UDC_P_DISABLE : + s3c2410_gpio_setpin(S3C2410_GPC(5), 0); + break; + case S3C2410_UDC_P_RESET : + break; + default: + break; + } +} + +static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { + .udc_command = mini2440_udc_pullup, +}; + + +/* LCD timing and setup */ + +/* + * This macro simplifies the table bellow + */ +#define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \ + _yres,margin_top,margin_bottom,vsync, refresh) \ + .width = _xres, \ + .xres = _xres, \ + .height = _yres, \ + .yres = _yres, \ + .left_margin = margin_left, \ + .right_margin = margin_right, \ + .upper_margin = margin_top, \ + .lower_margin = margin_bottom, \ + .hsync_len = hsync, \ + .vsync_len = vsync, \ + .pixclock = ((_clock*100000000000LL) / \ + ((refresh) * \ + (hsync + margin_left + _xres + margin_right) * \ + (vsync + margin_top + _yres + margin_bottom))), \ + .bpp = 16,\ + .type = (S3C2410_LCDCON1_TFT16BPP |\ + S3C2410_LCDCON1_TFT) + +struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { + [0] = { /* mini2440 + 3.5" TFT + touchscreen */ + _LCD_DECLARE( + 7, /* The 3.5 is quite fast */ + 240, 21, 38, 6, /* x timing */ + 320, 4, 4, 2, /* y timing */ + 60), /* refresh rate */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_INVVDEN | + S3C2410_LCDCON5_PWREN), + }, + [1] = { /* mini2440 + 7" TFT + touchscreen */ + _LCD_DECLARE( + 10, /* the 7" runs slower */ + 800, 40, 40, 48, /* x timing */ + 480, 29, 3, 3, /* y timing */ + 50), /* refresh rate */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN), + }, + /* The VGA shield can outout at several resolutions. All share + * the same timings, however, anything smaller than 1024x768 + * will only be displayed in the top left corner of a 1024x768 + * XGA output unless you add optional dip switches to the shield. + * Therefore timings for other resolutions have been ommited here. + */ + [2] = { + _LCD_DECLARE( + 10, + 1024, 1, 2, 2, /* y timing */ + 768, 200, 16, 16, /* x timing */ + 24), /* refresh rate, maximum stable, + tested with the FPGA shield */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_HWSWP), + }, +}; + +/* todo - put into gpio header */ + +#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) +#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) + +struct s3c2410fb_mach_info mini2440_fb_info __initdata = { + .displays = &mini2440_lcd_cfg[0], /* not constant! see init */ + .num_displays = 1, + .default_display = 0, + + /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN + * and disable the pull down resistors on pins we are using for LCD + * data. */ + + .gpcup = (0xf << 1) | (0x3f << 10), + + .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | + S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | + S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 | + S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 | + S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7), + + .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) | + S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) | + S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) | + S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | + S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), + + .gpdup = (0x3f << 2) | (0x3f << 10), + + .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | + S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | + S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | + S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 | + S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 | + S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23), + + .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) | + S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) | + S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) | + S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| + S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| + S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), +}; + +/* MMC/SD */ + +static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = { + .gpio_detect = S3C2410_GPG(8), + .gpio_wprotect = S3C2410_GPH(8), + .set_power = NULL, + .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34, +}; + +/* NAND Flash on MINI2440 board */ + +static struct mtd_partition mini2440_default_nand_part[] __initdata = { + [0] = { + .name = "u-boot", + .size = SZ_256K, + .offset = 0, + }, + [1] = { + .name = "u-boot-env", + .size = SZ_128K, + .offset = SZ_256K, + }, + [2] = { + .name = "kernel", + /* 5 megabytes, for a kernel with no modules + * or a uImage with a ramdisk attached */ + .size = 0x00500000, + .offset = SZ_256K + SZ_128K, + }, + [3] = { + .name = "root", + .offset = SZ_256K + SZ_128K + 0x00500000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = { + [0] = { + .name = "nand", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part), + .partitions = mini2440_default_nand_part, + }, +}; + +static struct s3c2410_platform_nand mini2440_nand_info __initdata = { + .tacls = 0, + .twrph0 = 25, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(mini2440_nand_sets), + .sets = mini2440_nand_sets, + .ignore_unset_ecc = 1, +}; + +/* DM9000AEP 10/100 ethernet controller */ + +static struct resource mini2440_dm9k_resource[] __initdata = { + [0] = { + .start = MACH_MINI2440_DM9K_BASE, + .end = MACH_MINI2440_DM9K_BASE + 3, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = MACH_MINI2440_DM9K_BASE + 4, + .end = MACH_MINI2440_DM9K_BASE + 7, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = IRQ_EINT7, + .end = IRQ_EINT7, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + } +}; + +/* + * The DM9000 has no eeprom, and it's MAC address is set by + * the bootloader before starting the kernel. + */ +static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = { + .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), +}; + +static struct platform_device mini2440_device_eth __initdata = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(mini2440_dm9k_resource), + .resource = mini2440_dm9k_resource, + .dev = { + .platform_data = &mini2440_dm9k_pdata, + }, +}; + +/* CON5 + * +--+ /-----\ + * | | | | + * | | | BAT | + * | | \_____/ + * | | + * | | +----+ +----+ + * | | | K5 | | K1 | + * | | +----+ +----+ + * | | +----+ +----+ + * | | | K4 | | K2 | + * | | +----+ +----+ + * | | +----+ +----+ + * | | | K6 | | K3 | + * | | +----+ +----+ + * ..... + */ +static struct gpio_keys_button mini2440_buttons[] __initdata = { + { + .gpio = S3C2410_GPG(0), /* K1 */ + .code = KEY_F1, + .desc = "Button 1", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(3), /* K2 */ + .code = KEY_F2, + .desc = "Button 2", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(5), /* K3 */ + .code = KEY_F3, + .desc = "Button 3", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(6), /* K4 */ + .code = KEY_POWER, + .desc = "Power", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(7), /* K5 */ + .code = KEY_F5, + .desc = "Button 5", + .active_low = 1, + }, +#if 0 + /* this pin is also known as TCLK1 and seems to already + * marked as "in use" somehow in the kernel -- possibly wrongly */ + { + .gpio = S3C2410_GPG(11), /* K6 */ + .code = KEY_F6, + .desc = "Button 6", + .active_low = 1, + }, +#endif +}; + +static struct gpio_keys_platform_data mini2440_button_data __initdata = { + .buttons = mini2440_buttons, + .nbuttons = ARRAY_SIZE(mini2440_buttons), +}; + +static struct platform_device mini2440_button_device __initdata = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &mini2440_button_data, + } +}; + +/* LEDS */ + +static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = { + .name = "led1", + .gpio = S3C2410_GPB(5), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "heartbeat", +}; + +static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = { + .name = "led2", + .gpio = S3C2410_GPB(6), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "nand-disk", +}; + +static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = { + .name = "led3", + .gpio = S3C2410_GPB(7), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "mmc0", +}; + +static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = { + .name = "led4", + .gpio = S3C2410_GPB(8), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "", +}; + +static struct s3c24xx_led_platdata mini2440_led_backlight_pdata __initdata = { + .name = "backlight", + .gpio = S3C2410_GPG(4), + .def_trigger = "backlight", +}; + +static struct platform_device mini2440_led1 __initdata = { + .name = "s3c24xx_led", + .id = 1, + .dev = { + .platform_data = &mini2440_led1_pdata, + }, +}; + +static struct platform_device mini2440_led2 __initdata = { + .name = "s3c24xx_led", + .id = 2, + .dev = { + .platform_data = &mini2440_led2_pdata, + }, +}; + +static struct platform_device mini2440_led3 __initdata = { + .name = "s3c24xx_led", + .id = 3, + .dev = { + .platform_data = &mini2440_led3_pdata, + }, +}; + +static struct platform_device mini2440_led4 __initdata = { + .name = "s3c24xx_led", + .id = 4, + .dev = { + .platform_data = &mini2440_led4_pdata, + }, +}; + +static struct platform_device mini2440_led_backlight __initdata = { + .name = "s3c24xx_led", + .id = 5, + .dev = { + .platform_data = &mini2440_led_backlight_pdata, + }, +}; + +/* AUDIO */ + +static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = { + .l3_clk = S3C2410_GPB(4), + .l3_mode = S3C2410_GPB(2), + .l3_data = S3C2410_GPB(3), + .model = UDA134X_UDA1341 +}; + +static struct platform_device mini2440_audio __initdata = { + .name = "s3c24xx_uda134x", + .id = 0, + .dev = { + .platform_data = &mini2440_audio_pins, + }, +}; + +/* + * I2C devices + */ +static struct at24_platform_data at24c08 = { + .byte_len = SZ_8K / 8, + .page_size = 16, +}; + +static struct i2c_board_info mini2440_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("24c08", 0x50), + .platform_data = &at24c08, + }, +}; + +static struct platform_device *mini2440_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, +/* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ + &s3c_device_i2c0, + &s3c_device_rtc, + &s3c_device_usbgadget, + &mini2440_device_eth, + &mini2440_led1, + &mini2440_led2, + &mini2440_led3, + &mini2440_led4, + &mini2440_button_device, + &s3c_device_nand, + &s3c_device_sdi, + &s3c_device_iis, + &mini2440_audio, +/* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ + /* remaining devices are optional */ +}; + +static void __init mini2440_map_io(void) +{ + s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); + + s3c_device_nand.dev.platform_data = &mini2440_nand_info; + s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; +} + +/* + * mini2440_features string + * + * t = Touchscreen present + * b = backlight control + * c = camera [TODO] + * 0-9 LCD configuration + * + */ +static char mini2440_features_str[12] __initdata = "0tb"; + +static int __init mini2440_features_setup(char *str) +{ + if (str) + strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str)); + return 1; +} + +__setup("mini2440=", mini2440_features_setup); + +#define FEATURE_SCREEN (1 << 0) +#define FEATURE_BACKLIGHT (1 << 1) +#define FEATURE_TOUCH (1 << 2) +#define FEATURE_CAMERA (1 << 3) + +struct mini2440_features_t { + int count; + int done; + int lcd_index; + struct platform_device *optional[8]; +}; + +static void mini2440_parse_features( + struct mini2440_features_t * features, + const char * features_str ) +{ + const char * fp = features_str; + + features->count = 0; + features->done = 0; + features->lcd_index = -1; + + while (*fp) { + char f = *fp++; + + switch (f) { + case '0'...'9': /* tft screen */ + if (features->done & FEATURE_SCREEN) { + printk(KERN_INFO "MINI2440: '%c' ignored, " + "screen type already set\n", f); + } else { + int li = f - '0'; + if (li >= ARRAY_SIZE(mini2440_lcd_cfg)) + printk(KERN_INFO "MINI2440: " + "'%c' out of range LCD mode\n", f); + else { + features->optional[features->count++] = + &s3c_device_lcd; + features->lcd_index = li; + } + } + features->done |= FEATURE_SCREEN; + break; + case 'b': + if (features->done & FEATURE_BACKLIGHT) + printk(KERN_INFO "MINI2440: '%c' ignored, " + "backlight already set\n", f); + else { + features->optional[features->count++] = + &mini2440_led_backlight; + } + features->done |= FEATURE_BACKLIGHT; + break; + case 't': + printk(KERN_INFO "MINI2440: '%c' ignored, " + "touchscreen not compiled in\n", f); + break; + case 'c': + if (features->done & FEATURE_CAMERA) + printk(KERN_INFO "MINI2440: '%c' ignored, " + "camera already registered\n", f); + else + features->optional[features->count++] = + &s3c_device_camif; + features->done |= FEATURE_CAMERA; + break; + } + } +} + +static void __init mini2440_init(void) +{ + struct mini2440_features_t features = { 0 }; + int i; + + printk(KERN_INFO "MINI2440: Option string mini2440=%s\n", + mini2440_features_str); + + /* Parse the feature string */ + mini2440_parse_features(&features, mini2440_features_str); + + /* turn LCD on */ + s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); + + /* Turn the backlight early on */ + s3c2410_gpio_setpin(S3C2410_GPG(4), 1); + s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT); + + /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ + s3c2410_gpio_pullup(S3C2410_GPB(1), 0); + s3c2410_gpio_setpin(S3C2410_GPB(1), 0); + s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); + + /* Make sure the D+ pullup pin is output */ + s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + + /* mark the key as input, without pullups (there is one on the board) */ + for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { + s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); + s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, + S3C2410_GPIO_INPUT); + } + if (features.lcd_index != -1) { + int li; + + mini2440_fb_info.displays = + &mini2440_lcd_cfg[features.lcd_index]; + + printk(KERN_INFO "MINI2440: LCD"); + for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++) + if (li == features.lcd_index) + printk(" [%d:%dx%d]", li, + mini2440_lcd_cfg[li].width, + mini2440_lcd_cfg[li].height); + else + printk(" %d:%dx%d", li, + mini2440_lcd_cfg[li].width, + mini2440_lcd_cfg[li].height); + printk("\n"); + s3c24xx_fb_set_platdata(&mini2440_fb_info); + } + s3c24xx_udc_set_platdata(&mini2440_udc_cfg); + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, mini2440_i2c_devs, + ARRAY_SIZE(mini2440_i2c_devs)); + + platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); + + if (features.count) /* the optional features */ + platform_add_devices(features.optional, features.count); + +} + + +MACHINE_START(MINI2440, "MINI2440") + /* Maintainer: Michel Pollet */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = mini2440_map_io, + .init_machine = mini2440_init, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END -- cgit v1.2.3 From bf4a59f1524202f887c4595aedb1aa489bcd9b64 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 25 Mar 2009 17:24:08 +0000 Subject: [ARM] MINI2440: Create a mini2440_defconfig file Just a working, starting point config file for the board. Signed-off-by: Michel Pollet Signed-off-by: Ben Dooks --- arch/arm/configs/mini2440_defconfig | 2097 +++++++++++++++++++++++++++++++++++ 1 file changed, 2097 insertions(+) create mode 100644 arch/arm/configs/mini2440_defconfig (limited to 'arch') diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig new file mode 100644 index 00000000000..e49ed40f3be --- /dev/null +++ b/arch/arm/configs/mini2440_defconfig @@ -0,0 +1,2097 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc6 +# Wed May 20 12:29:51 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +CONFIG_ARCH_S3C2410=y +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_PLAT_S3C24XX=y +CONFIG_S3C2410_CLOCK=y +CONFIG_CPU_S3C244X=y +CONFIG_S3C24XX_PWM=y +CONFIG_S3C24XX_GPIO_EXTRA=0 +CONFIG_S3C2410_DMA=y +# CONFIG_S3C2410_DMA_DEBUG is not set +CONFIG_S3C24XX_ADC=y +CONFIG_PLAT_S3C=y +CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y +CONFIG_CPU_LLSERIAL_S3C2440=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_WATCHDOG is not set +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y + +# +# Power management +# +# CONFIG_S3C2410_PM_DEBUG is not set +# CONFIG_S3C2410_PM_CHECK is not set +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_S3C_GPIO_SPACE=0 + +# +# S3C2400 Machines +# +CONFIG_S3C2410_PM=y +CONFIG_S3C2410_GPIO=y + +# +# S3C2410 Machines +# +# CONFIG_ARCH_SMDK2410 is not set +# CONFIG_ARCH_H1940 is not set +# CONFIG_MACH_N30 is not set +# CONFIG_ARCH_BAST is not set +# CONFIG_MACH_OTOM is not set +# CONFIG_MACH_AML_M5900 is not set +# CONFIG_MACH_TCT_HAMMER is not set +# CONFIG_MACH_VR1000 is not set +# CONFIG_MACH_QT2410 is not set + +# +# S3C2412 Machines +# +# CONFIG_MACH_JIVE is not set +# CONFIG_MACH_SMDK2413 is not set +# CONFIG_MACH_SMDK2412 is not set +# CONFIG_MACH_VSTMS is not set +CONFIG_CPU_S3C2440=y +CONFIG_S3C2440_DMA=y + +# +# S3C2440 Machines +# +# CONFIG_MACH_ANUBIS is not set +# CONFIG_MACH_OSIRIS is not set +# CONFIG_MACH_RX3715 is not set +# CONFIG_ARCH_S3C2440 is not set +# CONFIG_MACH_NEXCODER_2440 is not set +# CONFIG_MACH_AT2440EVB is not set +CONFIG_MACH_MINI2440=y + +# +# S3C2442 Machines +# + +# +# S3C2443 Machines +# +# CONFIG_MACH_SMDK2443 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +CONFIG_INFTL=y +CONFIG_RFD_FTL=y +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_S3C2410=y +# CONFIG_MTD_NAND_S3C2410_DEBUG is not set +# CONFIG_MTD_NAND_S3C2410_HWECC is not set +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +CONFIG_MTD_LPDDR=y +CONFIG_MTD_QINFO_PROBE=y + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +CONFIG_DM9000_DEBUGLEVEL=4 +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_AR9170_USB is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_ZD1211RW=m +CONFIG_ZD1211RW_DEBUG=y +# CONFIG_RT2X00 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=3 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C2440=y +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=128 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_S3C2410=y +CONFIG_I2C_SIMTEC=y + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_SENSORS_TSL2550=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_S3C24XX=y +# CONFIG_SPI_S3C24XX_GPIO is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IBMAEM is not set +# CONFIG_SENSORS_IBMPEX is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM75=y +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_THERMAL=m +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_S3C2410_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_SOC_CAMERA=m +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +CONFIG_SOC_CAMERA_PLATFORM=m +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_SIANO_SMS1XXX is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S3C2410=y +# CONFIG_FB_S3C2410_DEBUG is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_SOC=y +CONFIG_SND_S3C24XX_SOC=y +CONFIG_SND_S3C24XX_SOC_I2S=y +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set +CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_L3=y +CONFIG_SND_SOC_UDA134X=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_TOPSEED=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_FREECOM is not set +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=m +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +CONFIG_USB_SERIAL_SPCP8X5=m +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +CONFIG_USB_GADGET_S3C2410=y +CONFIG_USB_S3C2410=y +# CONFIG_USB_S3C2410_DEBUG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SPI=y +CONFIG_MMC_S3C=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_S3C24XX=y +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_S3C_UART=0 + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- cgit v1.2.3 From 799ca065213ab5df92d787c36c99cb4222f4e717 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 15 Jun 2009 22:07:48 +0100 Subject: [ARM] MINI2440: Cleanup duplicated header includes Remove duplicate mach headers for gpio. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-mini2440.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index eb4b24501a9..6a5bc3021bd 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -49,9 +49,6 @@ #include #include -#include -#include -#include #include #include -- cgit v1.2.3 From eb73e6221c5013b32647bcf44bcc570232ba2804 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 1 Jun 2009 22:34:14 +0200 Subject: [ARM] pxa/palm: various fixes for PalmZ72 (mostly audio asoc and usb) Signed-off-by: Marek Vasut Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/palmz72.h | 5 +-- arch/arm/mach-pxa/palmz72.c | 65 +++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 5032307ebf7..2806ef69ba5 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -21,7 +21,7 @@ /* SD/MMC */ #define GPIO_NR_PALMZ72_SD_DETECT_N 14 #define GPIO_NR_PALMZ72_SD_POWER_N 98 -#define GPIO_NR_PALMZ72_SD_RO 115 +#define GPIO_NR_PALMZ72_SD_RO 115 /* Touchscreen */ #define GPIO_NR_PALMZ72_WM9712_IRQ 27 @@ -31,8 +31,7 @@ /* USB */ #define GPIO_NR_PALMZ72_USB_DETECT_N 15 -#define GPIO_NR_PALMZ72_USB_POWER 95 -#define GPIO_NR_PALMZ72_USB_PULLUP 12 +#define GPIO_NR_PALMZ72_USB_PULLUP 95 /* LCD/Backlight */ #define GPIO_NR_PALMZ72_BL_POWER 20 diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index b88eb4dd2c8..c3645aa3fa3 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -27,7 +27,9 @@ #include #include #include +#include #include +#include #include #include @@ -41,6 +43,8 @@ #include #include #include +#include + #include #include "generic.h" @@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO113_AC97_nRESET, /* IrDA */ GPIO49_GPIO, /* ir disable */ @@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = { /* USB */ GPIO15_GPIO, /* usb detect */ - GPIO12_GPIO, /* usb pullup */ - GPIO95_GPIO, /* usb power */ + GPIO95_GPIO, /* usb pullup */ /* Matrix keypad */ GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, @@ -354,6 +359,22 @@ static struct platform_device palmz72_leds = { } }; +/****************************************************************************** + * UDC + ******************************************************************************/ +static struct gpio_vbus_mach_info palmz72_udc_info = { + .gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N, + .gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP, +}; + +static struct platform_device palmz72_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmz72_udc_info, + }, +}; + /****************************************************************************** * Power supply ******************************************************************************/ @@ -421,6 +442,31 @@ static struct platform_device power_supply = { }, }; +/****************************************************************************** + * WM97xx battery + ******************************************************************************/ +static struct wm97xx_batt_info wm97xx_batt_pdata = { + .batt_aux = WM97XX_AUX_ID3, + .temp_aux = WM97XX_AUX_ID2, + .charge_gpio = -1, + .max_voltage = PALMZ72_BAT_MAX_VOLTAGE, + .min_voltage = PALMZ72_BAT_MIN_VOLTAGE, + .batt_mult = 1000, + .batt_div = 414, + .temp_mult = 1, + .temp_div = 1, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, + .batt_name = "main-batt", +}; + +/****************************************************************************** + * aSoC audio + ******************************************************************************/ +static struct platform_device palmz72_asoc = { + .name = "palm27x-asoc", + .id = -1, +}; + /****************************************************************************** * Framebuffer ******************************************************************************/ @@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init); static struct platform_device *devices[] __initdata = { &palmz72_backlight, &palmz72_leds, + &palmz72_asoc, &power_supply, + &palmz72_gpio_vbus, }; +/* setup udc GPIOs initial state */ +static void __init palmz72_udc_init(void) +{ + if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) { + gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0); + gpio_free(GPIO_NR_PALMZ72_USB_PULLUP); + } +} + static void __init palmz72_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); + set_pxa_fb_info(&palmz72_lcd_screen); pxa_set_mci_info(&palmz72_mci_platform_data); + palmz72_udc_init(); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&palmz72_ficp_platform_data); pxa_set_keypad_info(&palmz72_keypad_platform_data); + wm97xx_bat_set_pdata(&wm97xx_batt_pdata); + platform_add_devices(devices, ARRAY_SIZE(devices)); } -- cgit v1.2.3 From 3cb05c97ad38aab0858fc176fd1577ac4a947bad Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Tue, 16 Jun 2009 15:19:24 +0300 Subject: [ARM] pxa/em-x270: remove .gpio_cs from em_x270_libertas_pdata Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/em-x270.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 243e0802b5f..b2d5a5394e4 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -735,6 +735,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = { .rx_threshold = 1, .tx_threshold = 1, .timeout = 1000, + .gpio_cs = 14, }; static unsigned long em_x270_libertas_pin_config[] = { @@ -803,7 +804,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi) struct libertas_spi_platform_data em_x270_libertas_pdata = { .use_dummy_writes = 1, - .gpio_cs = 14, .setup = em_x270_libertas_setup, .teardown = em_x270_libertas_teardown, }; -- cgit v1.2.3 From a37ed43115b70e832c7e8cc7dabd026d127ad9db Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Mon, 18 May 2009 08:53:56 +0300 Subject: [ARM] pxa/em-x270: add ability to control GPS and GPRS power Register userspace-consumer devices to allow userspace control of voltage regulators supplying GPS and GPRS modules Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/em-x270.c | 53 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index b2d5a5394e4..5184a570ac5 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -30,6 +30,7 @@ #include #include #include +#include #include @@ -1038,6 +1039,52 @@ static void __init em_x270_init_camera(void) static inline void em_x270_init_camera(void) {} #endif +static struct regulator_bulk_data em_x270_gps_consumer_supply = { + .supply = "vcc gps", +}; + +static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = { + .name = "vcc gps", + .num_supplies = 1, + .supplies = &em_x270_gps_consumer_supply, +}; + +static struct platform_device em_x270_gps_userspace_consumer = { + .name = "reg-userspace-consumer", + .id = 0, + .dev = { + .platform_data = &em_x270_gps_consumer_data, + }, +}; + +static struct regulator_bulk_data em_x270_gprs_consumer_supply = { + .supply = "vcc gprs", +}; + +static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = { + .name = "vcc gprs", + .num_supplies = 1, + .supplies = &em_x270_gprs_consumer_supply +}; + +static struct platform_device em_x270_gprs_userspace_consumer = { + .name = "reg-userspace-consumer", + .id = 1, + .dev = { + .platform_data = &em_x270_gprs_consumer_data, + } +}; + +static struct platform_device *em_x270_userspace_consumers[] = { + &em_x270_gps_userspace_consumer, + &em_x270_gprs_userspace_consumer, +}; + +static void __init em_x270_userspace_consumers_init(void) +{ + platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers)); +} + /* DA9030 related initializations */ #define REGULATOR_CONSUMER(_name, _dev, _supply) \ static struct regulator_consumer_supply _name##_consumers[] = { \ @@ -1047,11 +1094,11 @@ static inline void em_x270_init_camera(void) {} }, \ } -REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); +REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps"); REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); -REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); +REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs"); #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ static struct regulator_init_data _ldo##_data = { \ @@ -1062,6 +1109,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); .enabled = 0, \ }, \ .valid_ops_mask = _ops_mask, \ + .apply_uV = 1, \ }, \ .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ .consumer_supplies = _ldo##_consumers, \ @@ -1240,6 +1288,7 @@ static void __init em_x270_init(void) em_x270_init_spi(); em_x270_init_i2c(); em_x270_init_camera(); + em_x270_userspace_consumers_init(); } MACHINE_START(EM_X270, "Compulab EM-X270") -- cgit v1.2.3 From c63a5751d971b07d8cd80f4d4aae75c676665a3b Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Mon, 11 May 2009 15:06:16 +0300 Subject: [ARM] pxa/em-x270: always register AC97 controller device After commit 6b849bcff0004aa5dd216b4d3eb56f51c9df8a72 (ASoC: Convert PXA AC97 driver to probe with the platform device) AC97 controller device should be registered explicitly for both ASoC and generic AC97 drivers Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/em-x270.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 5184a570ac5..5343d1f339d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -839,10 +839,14 @@ static void __init em_x270_init_spi(void) static inline void em_x270_init_spi(void) {} #endif -#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) +#if defined(CONFIG_SND_PXA2XX_AC97_LIB) +static pxa2xx_audio_ops_t em_x270_ac97_info = { + .reset_gpio = 113, +}; + static void __init em_x270_init_ac97(void) { - pxa_set_ac97_info(NULL); + pxa_set_ac97_info(&em_x270_ac97_info); } #else static inline void em_x270_init_ac97(void) {} -- cgit v1.2.3 From 303f2d7dc8eddc65de27d97eab0fc1c04ec4d2e1 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 14 Jun 2009 12:04:19 +0300 Subject: [ARM] pxa/em-x270: fix type in SND_PXA2XX_LIB_AC97 Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/em-x270.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 5343d1f339d..63b10d9bb1d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -839,7 +839,7 @@ static void __init em_x270_init_spi(void) static inline void em_x270_init_spi(void) {} #endif -#if defined(CONFIG_SND_PXA2XX_AC97_LIB) +#if defined(CONFIG_SND_PXA2XX_LIB_AC97) static pxa2xx_audio_ops_t em_x270_ac97_info = { .reset_gpio = 113, }; -- cgit v1.2.3 From e6c3f4b89bf3698a6994d30de7a16ae395a81dab Mon Sep 17 00:00:00 2001 From: Tomas 'Sleep_Walker' Cech Date: Mon, 18 May 2009 15:24:14 +0200 Subject: [ARM] pxa/treo680: initial support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Tomáš Čech Acked-by: Marek Vasut Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 10 + arch/arm/mach-pxa/Makefile | 1 + arch/arm/mach-pxa/include/mach/treo680.h | 49 +++ arch/arm/mach-pxa/treo680.c | 612 +++++++++++++++++++++++++++++++ arch/arm/mm/mmu.c | 7 + 5 files changed, 679 insertions(+) create mode 100644 arch/arm/mach-pxa/include/mach/treo680.h create mode 100644 arch/arm/mach-pxa/treo680.c (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index f4533f8ff4e..89c992b8f75 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -401,6 +401,16 @@ config MACH_PALMZ72 Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. +config MACH_TREO680 + bool "Palm Treo 680" + default y + depends on ARCH_PXA_PALM + select PXA27x + select IWMMXT + help + Say Y here if you intend to run this kernel on Palm Treo 680 + smartphone. + config MACH_PALMLD bool "Palm LifeDrive" default y diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d18ffef44b8..d4c6122a342 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o +obj-$(CONFIG_MACH_TREO680) += treo680.o obj-$(CONFIG_ARCH_VIPER) += viper.o ifeq ($(CONFIG_MACH_ZYLONITE),y) diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h new file mode 100644 index 00000000000..af443b24d99 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/treo680.h @@ -0,0 +1,49 @@ +/* + * GPIOs and interrupts for Palm Treo 680 smartphone + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_TREO680_H_ +#define _INCLUDE_TREO680_H_ + +/* GPIOs */ +#define GPIO_NR_TREO680_POWER_DETECT 0 +#define GPIO_NR_TREO680_AMP_EN 27 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_GREEN_LED 20 +#define GPIO_NR_TREO680_RED_LED 79 +#define GPIO_NR_TREO680_SD_DETECT_N 113 +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_EP_DETECT_N 116 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_USB_DETECT 1 +#define GPIO_NR_TREO680_USB_PULLUP 114 +#define GPIO_NR_TREO680_GSM_POWER 40 +#define GPIO_NR_TREO680_GSM_RESET 87 +#define GPIO_NR_TREO680_GSM_WAKE 57 +#define GPIO_NR_TREO680_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO680_GSM_TRIGGER 10 +#define GPIO_NR_TREO680_BT_EN 43 +#define GPIO_NR_TREO680_IR_EN 115 +#define GPIO_NR_TREO680_IR_TXD 47 +#define GPIO_NR_TREO680_BL_POWER 38 +#define GPIO_NR_TREO680_LCD_POWER 25 + +/* Various addresses */ +#define TREO680_PHYS_RAM_START 0xa0000000 +#define TREO680_PHYS_IO_START 0x40000000 +#define TREO680_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO680_MAX_INTENSITY 254 +#define TREO680_DEFAULT_INTENSITY 160 +#define TREO680_LIMIT_MASK 0x7F +#define TREO680_PRESCALER 63 +#define TREO680_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c new file mode 100644 index 00000000000..a06f19edebb --- /dev/null +++ b/arch/arm/mach-pxa/treo680.c @@ -0,0 +1,612 @@ +/* + * Hardware definitions for Palm Treo 680 + * + * Author: Tomas Cech + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (find more info at www.hackndev.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long treo680_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO33_GPIO, /* SD read only */ + GPIO113_GPIO, /* SD detect */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO95_AC97_nRESET, + + /* IrDA */ + GPIO46_FICP_RXD, + GPIO47_FICP_TXD, + + /* PWM */ + GPIO16_PWM0_OUT, + + /* USB */ + GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ + + /* MATRIX KEYPAD */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO97_KP_MKIN_3, + GPIO98_KP_MKIN_4, + GPIO99_KP_MKIN_5, + GPIO91_KP_MKIN_6, + GPIO13_KP_MKIN_7, + GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, + GPIO96_KP_MKOUT_6, + GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + + /* Quick Capture Interface */ + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO81_CIF_DD_0, + GPIO55_CIF_DD_1, + GPIO51_CIF_DD_2, + GPIO50_CIF_DD_3, + GPIO52_CIF_DD_4, + GPIO48_CIF_DD_5, + GPIO17_CIF_DD_6, + GPIO12_CIF_DD_7, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* GSM */ + GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO39_FFUART_TXD, + GPIO41_FFUART_RTS, + + /* MISC. */ + GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */ + GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */ + GPIO116_GPIO, /* headphone detect */ + GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ +}; + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +static int treo680_mci_init(struct device *dev, + irq_handler_t treo680_detect_int, void *data) +{ + int err = 0; + + /* Setup an interrupt for detecting card insert/remove events */ + err = gpio_request(GPIO_NR_TREO680_SD_DETECT_N, "SD IRQ"); + + if (err) + goto err; + + err = gpio_direction_input(GPIO_NR_TREO680_SD_DETECT_N); + if (err) + goto err2; + + err = request_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), + treo680_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "SD/MMC card detect", data); + + if (err) { + dev_err(dev, "%s: cannot request SD/MMC card detect IRQ\n", + __func__); + goto err2; + } + + err = gpio_request(GPIO_NR_TREO680_SD_POWER, "SD_POWER"); + if (err) + goto err3; + + err = gpio_direction_output(GPIO_NR_TREO680_SD_POWER, 1); + if (err) + goto err4; + + err = gpio_request(GPIO_NR_TREO680_SD_READONLY, "SD_READONLY"); + if (err) + goto err4; + + err = gpio_direction_input(GPIO_NR_TREO680_SD_READONLY); + if (err) + goto err5; + + return 0; + +err5: + gpio_free(GPIO_NR_TREO680_SD_READONLY); +err4: + gpio_free(GPIO_NR_TREO680_SD_POWER); +err3: + free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); +err2: + gpio_free(GPIO_NR_TREO680_SD_DETECT_N); +err: + return err; +} + +static void treo680_mci_exit(struct device *dev, void *data) +{ + gpio_free(GPIO_NR_TREO680_SD_READONLY); + gpio_free(GPIO_NR_TREO680_SD_POWER); + free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); + gpio_free(GPIO_NR_TREO680_SD_DETECT_N); +} + +static void treo680_mci_power(struct device *dev, unsigned int vdd) +{ + struct pxamci_platform_data *p_d = dev->platform_data; + gpio_set_value(GPIO_NR_TREO680_SD_POWER, p_d->ocr_mask & (1 << vdd)); +} + +static int treo680_mci_get_ro(struct device *dev) +{ + return gpio_get_value(GPIO_NR_TREO680_SD_READONLY); +} + +static struct pxamci_platform_data treo680_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .setpower = treo680_mci_power, + .get_ro = treo680_mci_get_ro, + .init = treo680_mci_init, + .exit = treo680_mci_exit, +}; + +/****************************************************************************** + * GPIO keyboard + ******************************************************************************/ +static unsigned int treo680_matrix_keys[] = { + KEY(0, 0, KEY_F8), /* Red/Off/Power */ + KEY(0, 1, KEY_LEFT), + KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ + KEY(0, 3, KEY_L), + KEY(0, 4, KEY_A), + KEY(0, 5, KEY_Q), + KEY(0, 6, KEY_P), + + KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ + KEY(1, 1, KEY_RIGHT), + KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ + KEY(1, 3, KEY_Z), + KEY(1, 4, KEY_S), + KEY(1, 5, KEY_W), + + KEY(2, 0, KEY_F1), /* Phone */ + KEY(2, 1, KEY_UP), + KEY(2, 2, KEY_0), + KEY(2, 3, KEY_X), + KEY(2, 4, KEY_D), + KEY(2, 5, KEY_E), + + KEY(3, 0, KEY_F10), /* Calendar */ + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_SPACE), + KEY(3, 3, KEY_C), + KEY(3, 4, KEY_F), + KEY(3, 5, KEY_R), + + KEY(4, 0, KEY_F12), /* Mail */ + KEY(4, 1, KEY_KPENTER), + KEY(4, 2, KEY_RIGHTALT), /* Alt */ + KEY(4, 3, KEY_V), + KEY(4, 4, KEY_G), + KEY(4, 5, KEY_T), + + KEY(5, 0, KEY_F9), /* Home */ + KEY(5, 1, KEY_PAGEUP), /* Side up */ + KEY(5, 2, KEY_DOT), + KEY(5, 3, KEY_B), + KEY(5, 4, KEY_H), + KEY(5, 5, KEY_Y), + + KEY(6, 0, KEY_TAB), /* Side Activate */ + KEY(6, 1, KEY_PAGEDOWN), /* Side down */ + KEY(6, 2, KEY_ENTER), + KEY(6, 3, KEY_N), + KEY(6, 4, KEY_J), + KEY(6, 5, KEY_U), + + KEY(7, 0, KEY_F6), /* Green/Call */ + KEY(7, 1, KEY_O), + KEY(7, 2, KEY_BACKSPACE), + KEY(7, 3, KEY_M), + KEY(7, 4, KEY_K), + KEY(7, 5, KEY_I), +}; + +static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { + .matrix_key_rows = 8, + .matrix_key_cols = 7, + .matrix_key_map = treo680_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), + .direct_key_map = { KEY_CONNECT }, + .direct_key_num = 1, + + .debounce_interval = 30, +}; + +/****************************************************************************** + * aSoC audio + ******************************************************************************/ + +static pxa2xx_audio_ops_t treo680_ac97_pdata = { + .reset_gpio = 95, +}; + +/****************************************************************************** + * Backlight + ******************************************************************************/ +static int treo680_backlight_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER"); + if (ret) + goto err; + ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0); + if (ret) + goto err2; + ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER"); + if (ret) + goto err2; + ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0); + if (ret) + goto err3; + + return 0; +err3: + gpio_free(GPIO_NR_TREO680_LCD_POWER); +err2: + gpio_free(GPIO_NR_TREO680_BL_POWER); +err: + return ret; +} + +static int treo680_backlight_notify(int brightness) +{ + gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness); + return TREO680_MAX_INTENSITY - brightness; +}; + +static void treo680_backlight_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_BL_POWER); + gpio_free(GPIO_NR_TREO680_LCD_POWER); +} + +static struct platform_pwm_backlight_data treo680_backlight_data = { + .pwm_id = 0, + .max_brightness = TREO680_MAX_INTENSITY, + .dft_brightness = TREO680_DEFAULT_INTENSITY, + .pwm_period_ns = TREO680_PERIOD_NS, + .init = treo680_backlight_init, + .notify = treo680_backlight_notify, + .exit = treo680_backlight_exit, +}; + +static struct platform_device treo680_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &treo680_backlight_data, + }, +}; + +/****************************************************************************** + * IrDA + ******************************************************************************/ +static void treo680_transceiver_mode(struct device *dev, int mode) +{ + gpio_set_value(GPIO_NR_TREO680_IR_EN, mode & IR_OFF); + pxa2xx_transceiver_mode(dev, mode); +} + +static int treo680_irda_startup(struct device *dev) +{ + int err; + + err = gpio_request(GPIO_NR_TREO680_IR_EN, "Ir port disable"); + if (err) + goto err1; + + err = gpio_direction_output(GPIO_NR_TREO680_IR_EN, 1); + if (err) + goto err2; + + return 0; + +err2: + dev_err(dev, "treo680_irda: cannot change IR gpio direction\n"); + gpio_free(GPIO_NR_TREO680_IR_EN); +err1: + dev_err(dev, "treo680_irda: cannot allocate IR gpio\n"); + return err; +} + +static void treo680_irda_shutdown(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_AMP_EN); +} + +static struct pxaficp_platform_data treo680_ficp_info = { + .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF, + .startup = treo680_irda_startup, + .shutdown = treo680_irda_shutdown, + .transceiver_mode = treo680_transceiver_mode, +}; + +/****************************************************************************** + * UDC + ******************************************************************************/ +static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = { + .gpio_vbus = GPIO_NR_TREO680_USB_DETECT, + .gpio_vbus_inverted = 1, + .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP, +}; + + +/****************************************************************************** + * USB host + ******************************************************************************/ +static struct pxaohci_platform_data treo680_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | ENABLE_PORT3, + .power_budget = 0, +}; + +/****************************************************************************** + * Power supply + ******************************************************************************/ +static int power_supply_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC"); + if (ret) + goto err1; + ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT); + if (ret) + goto err2; + + return 0; + +err2: + gpio_free(GPIO_NR_TREO680_POWER_DETECT); +err1: + return ret; +} + +static int treo680_is_ac_online(void) +{ + return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT); +} + +static void power_supply_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_POWER_DETECT); +} + +static char *treo680_supplicants[] = { + "main-battery", +}; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = treo680_is_ac_online, + .exit = power_supply_exit, + .supplied_to = treo680_supplicants, + .num_supplicants = ARRAY_SIZE(treo680_supplicants), +}; + +static struct platform_device power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &power_supply_info, + }, +}; + +/****************************************************************************** + * Vibra and LEDs + ******************************************************************************/ +static struct gpio_led gpio_leds[] = { + { + .name = "treo680:vibra:vibra", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_VIBRATE_EN, + }, + { + .name = "treo680:green:led", + .default_trigger = "mmc0", + .gpio = GPIO_NR_TREO680_GREEN_LED, + }, + { + .name = "treo680:keybbl:keybbl", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_KEYB_BL, + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device treo680_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + } +}; + + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +/* TODO: add support for 324x324 */ +static struct pxafb_mode_info treo680_lcd_modes[] = { +{ + .pixclock = 86538, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 20, + .right_margin = 8, + .upper_margin = 8, + .lower_margin = 5, + + .hsync_len = 4, + .vsync_len = 1, +}, +}; + +static struct pxafb_mach_info treo680_lcd_screen = { + .modes = treo680_lcd_modes, + .num_modes = ARRAY_SIZE(treo680_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +/****************************************************************************** + * Power management - standby + ******************************************************************************/ +static void __init treo680_pm_init(void) +{ + static u32 resume[] = { + 0xe3a00101, /* mov r0, #0x40000000 */ + 0xe380060f, /* orr r0, r0, #0x00f00000 */ + 0xe590f008, /* ldr pc, [r0, #0x08] */ + }; + + /* this is where the bootloader jumps */ + memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume)); +} + +/****************************************************************************** + * Machine init + ******************************************************************************/ +static struct platform_device *devices[] __initdata = { + &treo680_backlight, + &treo680_leds, + &power_supply, +}; + +/* setup udc GPIOs initial state */ +static void __init treo680_udc_init(void) +{ + if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) { + gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1); + gpio_free(GPIO_NR_TREO680_USB_PULLUP); + } +} + +static void __init treo680_init(void) +{ + treo680_pm_init(); + pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); + pxa_set_keypad_info(&treo680_keypad_platform_data); + set_pxa_fb_info(&treo680_lcd_screen); + pxa_set_mci_info(&treo680_mci_platform_data); + treo680_udc_init(); + pxa_set_udc_info(&treo680_udc_info); + pxa_set_ac97_info(&treo680_ac97_pdata); + pxa_set_ficp_info(&treo680_ficp_info); + pxa_set_ohci_info(&treo680_ohci_info); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +MACHINE_START(TREO680, "Palm Treo 680") + .phys_io = TREO680_PHYS_IO_START, + .io_pg_offst = io_p2v(0x40000000), + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = treo680_init, +MACHINE_END diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e6344ece00c..0b91bb20cf9 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -835,6 +835,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) BOOTMEM_EXCLUSIVE); } + if (machine_is_treo680()) { + reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, + BOOTMEM_EXCLUSIVE); + reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, + BOOTMEM_EXCLUSIVE); + } + if (machine_is_palmt5()) reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, BOOTMEM_EXCLUSIVE); -- cgit v1.2.3 From 6ea0414fc748ab5b1d83a414c7ee3a60190363aa Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 28 May 2009 07:15:18 +0200 Subject: [ARM] pxa/hx4700: add Maxim 1587A voltage regulator On this board, the PXA270 CPU voltage VCC_CORE is provided by a Maxim 1587A voltage regulator configured to provide 1.55 V maximum voltage for 624 MHz operation. Signed-off-by: Philipp Zabel Signed-off-by: Eric Miao --- arch/arm/mach-pxa/hx4700.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 7fff467e84f..81359d574f8 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -774,6 +775,45 @@ static struct platform_device strataflash = { }, }; +/* + * Maxim MAX1587A on PI2C + */ + +static struct regulator_consumer_supply max1587a_consumer = { + .supply = "vcc_core", +}; + +static struct regulator_init_data max1587a_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 900000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max1587a_consumer, +}; + +static struct max1586_subdev_data max1587a_subdev = { + .name = "vcc_core", + .id = MAX1586_V3, + .platform_data = &max1587a_v3_info, +}; + +static struct max1586_platform_data max1587a_info = { + .num_subdevs = 1, + .subdevs = &max1587a_subdev, + .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ +}; + +static struct i2c_board_info __initdata pi2c_board_info[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &max1587a_info, + }, +}; + /* * PCMCIA */ @@ -828,6 +868,7 @@ static void __init hx4700_init(void) pxa_set_ficp_info(&ficp_info); pxa27x_set_i2c_power_info(NULL); pxa_set_i2c_info(NULL); + i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info)); pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); -- cgit v1.2.3 From 9752e14898102063a67b44e6db5b758092e769a4 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Thu, 30 Apr 2009 11:53:30 +0800 Subject: [ARM] pxa/mioa701: add Maxim 1586 voltage regulator On this board, the PXA272 CPU voltage VCC_CORE is provided by a Maxim 1586 voltage regulator. Use the regulator framework to provide VCC_CORE control. When cpufreq will be updated to ask for vcc_core, this will optimize power drained by the board. Signed-off-by: Robert Jarzmik Acked-by: Mark Brown Signed-off-by: Eric Miao --- arch/arm/mach-pxa/mioa701.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 4dc8c2ec40a..99e5a880a4a 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -716,6 +717,37 @@ static struct wm97xx_batt_info mioa701_battery_data = { .batt_name = "mioa701_battery", }; +/* + * Voltage regulation + */ +static struct regulator_consumer_supply max1586_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data max1586_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 1000000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max1586_consumers), + .consumer_supplies = max1586_consumers, +}; + +static struct max1586_subdev_data max1586_subdevs[] = { + { .name = "vcc_core", .id = MAX1586_V3, + .platform_data = &max1586_v3_info }, +}; + +static struct max1586_platform_data max1586_info = { + .subdevs = max1586_subdevs, + .num_subdevs = ARRAY_SIZE(max1586_subdevs), +}; + /* * Camera interface */ @@ -725,6 +757,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = { .mclk_10khz = 5000, }; +static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &max1586_info, + }, +}; + static struct soc_camera_link iclink = { .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ }; @@ -825,7 +864,9 @@ static void __init mioa701_machine_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); gsm_init(); + i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices)); pxa_set_i2c_info(&i2c_pdata); + pxa27x_set_i2c_power_info(NULL); pxa_set_camera_info(&mioa701_pxacamera_platform_data); i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); } -- cgit v1.2.3 From e567b74caff03c0ed66b3d3e11c0acd17fbcfb9a Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 28 May 2009 07:15:17 +0200 Subject: [ARM] pxa/mioa701: add V3 gain configuration for Maxim 1586 voltage regulator Maxim 1586 V3 gain can be configured by external resistors (R24, R25) connected to the FB3 pin. To avoid accidental overvoltage, it now requires this gain to be configured explicitly. Signed-off-by: Philipp Zabel Acked-by: Robert Jarzmik Signed-off-by: Eric Miao --- arch/arm/mach-pxa/mioa701.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 99e5a880a4a..2d28132c725 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -746,6 +746,7 @@ static struct max1586_subdev_data max1586_subdevs[] = { static struct max1586_platform_data max1586_info = { .subdevs = max1586_subdevs, .num_subdevs = ARRAY_SIZE(max1586_subdevs), + .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */ }; /* -- cgit v1.2.3 From 8776b268c6b0b671c2c744b06fee021b6da3e45f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 26 Apr 2009 12:53:58 +0100 Subject: [ARM] pxa: register wm8731 explicitly for corgi and poodle The wm8731 driver has been converted to register using the standard I2C device registration mechanism so we can now do the registration in the arch/arm code as normal. Signed-off-by: Mark Brown Signed-off-by: Eric Miao --- arch/arm/mach-pxa/corgi.c | 6 ++++++ arch/arm/mach-pxa/poodle.c | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 962dda2e154..5363e1aea3f 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = { &sharpsl_rom_device, }; +static struct i2c_board_info __initdata corgi_i2c_devices[] = { + { I2C_BOARD_INFO("wm8731", 0x1b) }, +}; + static void corgi_poweroff(void) { if (!machine_is_corgi()) @@ -634,6 +639,7 @@ static void __init corgi_init(void) pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices)); platform_scoop_config = &corgi_pcmcia_config; diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index ac431ed1039..9352d4a3483 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = { &sharpsl_rom_device, }; +static struct i2c_board_info __initdata poodle_i2c_devices[] = { + { I2C_BOARD_INFO("wm8731", 0x1b) }, +}; + static void poodle_poweroff(void) { arm_machine_restart('h', NULL); @@ -519,6 +524,7 @@ static void __init poodle_init(void) pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices)); poodle_init_spi(); } -- cgit v1.2.3 From 70298c6e6c1ba68346336b4ea54bd5c0abbf73c8 Mon Sep 17 00:00:00 2001 From: "Zhang, Yanmin" Date: Tue, 16 Jun 2009 13:34:38 +0800 Subject: PCI AER: support Multiple Error Received and no error source id Based on PCI Express AER specs, a root port might receive multiple TLP errors while it could only save a correctable error source id and an uncorrectable error source id at the same time. In addition, some root port hardware might be unable to provide a correct source id, i.e., the source id, or the bus id part of the source id provided by root port might be equal to 0. The patchset implements the support in kernel by searching the device tree under the root port. Patch 1 changes parameter cb of function pci_walk_bus to return a value. When cb return non-zero, pci_walk_bus stops more searching on the device tree. Reviewed-by: Andrew Patterson Signed-off-by: Zhang Yanmin Signed-off-by: Jesse Barnes --- arch/powerpc/platforms/pseries/eeh_driver.c | 38 ++++++++++++++++++----------- 1 file changed, 24 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c index 9a2a6e32f00..0e8db677125 100644 --- a/arch/powerpc/platforms/pseries/eeh_driver.c +++ b/arch/powerpc/platforms/pseries/eeh_driver.c @@ -122,7 +122,7 @@ static void eeh_enable_irq(struct pci_dev *dev) * passed back in "userdata". */ -static void eeh_report_error(struct pci_dev *dev, void *userdata) +static int eeh_report_error(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; @@ -130,19 +130,21 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) dev->error_state = pci_channel_io_frozen; if (!driver) - return; + return 0; eeh_disable_irq(dev); if (!driver->err_handler || !driver->err_handler->error_detected) - return; + return 0; rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); /* A driver that needs a reset trumps all others */ if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; if (*res == PCI_ERS_RESULT_NONE) *res = rc; + + return 0; } /** @@ -153,7 +155,7 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) * Cumulative response passed back in "userdata". */ -static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) +static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; @@ -161,26 +163,28 @@ static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) if (!driver || !driver->err_handler || !driver->err_handler->mmio_enabled) - return; + return 0; rc = driver->err_handler->mmio_enabled (dev); /* A driver that needs a reset trumps all others */ if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; if (*res == PCI_ERS_RESULT_NONE) *res = rc; + + return 0; } /** * eeh_report_reset - tell device that slot has been reset */ -static void eeh_report_reset(struct pci_dev *dev, void *userdata) +static int eeh_report_reset(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; if (!driver) - return; + return 0; dev->error_state = pci_channel_io_normal; @@ -188,35 +192,39 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata) if (!driver->err_handler || !driver->err_handler->slot_reset) - return; + return 0; rc = driver->err_handler->slot_reset(dev); if ((*res == PCI_ERS_RESULT_NONE) || (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; if (*res == PCI_ERS_RESULT_DISCONNECT && rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; + + return 0; } /** * eeh_report_resume - tell device to resume normal operations */ -static void eeh_report_resume(struct pci_dev *dev, void *userdata) +static int eeh_report_resume(struct pci_dev *dev, void *userdata) { struct pci_driver *driver = dev->driver; dev->error_state = pci_channel_io_normal; if (!driver) - return; + return 0; eeh_enable_irq(dev); if (!driver->err_handler || !driver->err_handler->resume) - return; + return 0; driver->err_handler->resume(dev); + + return 0; } /** @@ -226,22 +234,24 @@ static void eeh_report_resume(struct pci_dev *dev, void *userdata) * dead, and that no further recovery attempts will be made on it. */ -static void eeh_report_failure(struct pci_dev *dev, void *userdata) +static int eeh_report_failure(struct pci_dev *dev, void *userdata) { struct pci_driver *driver = dev->driver; dev->error_state = pci_channel_io_perm_failure; if (!driver) - return; + return 0; eeh_disable_irq(dev); if (!driver->err_handler || !driver->err_handler->error_detected) - return; + return 0; driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); + + return 0; } /* ------------------------------------------------------- */ -- cgit v1.2.3 From f9cde5ffed17bf74f6bef042d99edb0622f58576 Mon Sep 17 00:00:00 2001 From: Gary Hade Date: Wed, 27 May 2009 12:41:44 -0700 Subject: x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded Issue a warning if _CRS returns too many resource descriptors to be accommodated by the fixed size resource array instances. If there is no transparent bridge on the root bus "too many" is the PCI_BUS_NUM_RESOURCES size of the resource array. Otherwise, the last 3 slots of the resource array must be excluded making the maximum (PCI_BUS_NUM_RESOURCES - 3). The current code: - is silent when _CRS returns too many resource descriptors and - incorrectly allows use of the last 3 slots of the resource array for a root bus with a transparent bridge Signed-off-by: Gary Hade Signed-off-by: Jesse Barnes --- arch/x86/pci/acpi.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index 8d898e0d360..16c3fda85bb 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -38,15 +38,26 @@ count_resource(struct acpi_resource *acpi_res, void *data) struct acpi_resource_address64 addr; acpi_status status; - if (info->res_num >= PCI_BUS_NUM_RESOURCES) - return AE_OK; - status = resource_to_addr(acpi_res, &addr); if (ACPI_SUCCESS(status)) info->res_num++; return AE_OK; } +static int +bus_has_transparent_bridge(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + u16 class = dev->class >> 8; + + if (class == PCI_CLASS_BRIDGE_PCI && dev->transparent) + return true; + } + return false; +} + static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data) { @@ -56,9 +67,7 @@ setup_resource(struct acpi_resource *acpi_res, void *data) acpi_status status; unsigned long flags; struct resource *root; - - if (info->res_num >= PCI_BUS_NUM_RESOURCES) - return AE_OK; + int max_root_bus_resources = PCI_BUS_NUM_RESOURCES; status = resource_to_addr(acpi_res, &addr); if (!ACPI_SUCCESS(status)) @@ -82,6 +91,18 @@ setup_resource(struct acpi_resource *acpi_res, void *data) res->end = res->start + addr.address_length - 1; res->child = NULL; + if (bus_has_transparent_bridge(info->bus)) + max_root_bus_resources -= 3; + if (info->res_num >= max_root_bus_resources) { + printk(KERN_WARNING "PCI: Failed to allocate 0x%lx-0x%lx " + "from %s for %s due to _CRS returning more than " + "%d resource descriptors\n", (unsigned long) res->start, + (unsigned long) res->end, root->name, info->name, + max_root_bus_resources); + info->res_num++; + return AE_OK; + } + if (insert_resource(root, res)) { printk(KERN_ERR "PCI: Failed to allocate 0x%lx-0x%lx " "from %s for %s\n", (unsigned long) res->start, -- cgit v1.2.3 From 3f1a567d8a4ed7a5d105bd049343606f5273b603 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 2 Jun 2009 09:31:03 +0100 Subject: [ARM] VIC: Fix resume sources usage The resume_mask wasn't being checked in vic_set_wake() to see if the IRQ was a valid wakeup source. Signed-off-by: Ben Dooks --- arch/arm/common/vic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 887c6eb3a18..6ed89836e90 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on) { struct vic_device *v = vic_from_irq(irq); unsigned int off = irq & 31; + u32 bit = 1 << off; if (!v) return -EINVAL; + if (!(bit & v->resume_sources)) + return -EINVAL; + if (on) - v->resume_irqs |= 1 << off; + v->resume_irqs |= bit; else - v->resume_irqs &= ~(1 << off); + v->resume_irqs &= ~bit; return 0; } -- cgit v1.2.3 From 9492b272820ac8f32a6ad4fcabd571d8305a6d47 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Tue, 16 Jun 2009 16:56:34 +0800 Subject: [ARM] S3C24XX: remove duplicated #include Remove duplicated #include in arch/arm/mach-s3c2410/usb-simtec.c. Signed-off-by: Huang Weiyi Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/usb-simtec.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 6cd9377ddb8..50e25fc5f8a 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From 52da219e9664e537a745877b0efa7cf2b1ff2996 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 3 Jun 2009 20:08:38 +0100 Subject: [ARM] S3C64XX: Provide device for IIS ports This allows the S3C64XX IIS drivers to be converted to the standard driver model and allows fixes there for problems with attempting to acquire the clocks for the IIS blocks via the clock API. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 1 + arch/arm/plat-s3c/dev-audio.c | 52 +++++++++++++++++++++++++++++++++++ arch/arm/plat-s3c/include/plat/devs.h | 4 ++- 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-s3c/dev-audio.c (limited to 'arch') diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 610651455a7..74bb7cb5da4 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c/dev-audio.c new file mode 100644 index 00000000000..ccdd8158431 --- /dev/null +++ b/arch/arm/plat-s3c/dev-audio.c @@ -0,0 +1,52 @@ +/* linux/arch/arm/plat-s3c/dev-audio.c + * + * Copyright 2009 Wolfson Microelectronics + * Mark Brown + * + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include + + +static struct resource s3c64xx_iis0_resource[] = { + [0] = { + .start = S3C64XX_PA_IIS0, + .end = S3C64XX_PA_IIS0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iis0 = { + .name = "s3c64xx-iis", + .id = 0, + .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), + .resource = s3c64xx_iis0_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iis0); + +static struct resource s3c64xx_iis1_resource[] = { + [0] = { + .start = S3C64XX_PA_IIS1, + .end = S3C64XX_PA_IIS1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), + .resource = s3c64xx_iis1_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iis1); diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index a0b6768fddc..91de11be274 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -24,13 +24,15 @@ extern struct platform_device *s3c24xx_uart_src[]; extern struct platform_device s3c_device_timer[]; +extern struct platform_device s3c64xx_device_iis0; +extern struct platform_device s3c64xx_device_iis1; + extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; -extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; -- cgit v1.2.3 From d06a49eec97718949acfdc26110701d28b1872c0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 3 Jun 2009 20:08:39 +0100 Subject: [ARM] S3C64XX: Add device for IISv4 port Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/dev-audio.c | 16 ++++++++++++++++ arch/arm/plat-s3c/include/plat/devs.h | 1 + 2 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c/dev-audio.c index ccdd8158431..1322beb40dd 100644 --- a/arch/arm/plat-s3c/dev-audio.c +++ b/arch/arm/plat-s3c/dev-audio.c @@ -50,3 +50,19 @@ struct platform_device s3c64xx_device_iis1 = { .resource = s3c64xx_iis1_resource, }; EXPORT_SYMBOL(s3c64xx_device_iis1); + +static struct resource s3c64xx_iisv4_resource[] = { + [0] = { + .start = S3C64XX_PA_IISV4, + .end = S3C64XX_PA_IISV4 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iisv4 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), + .resource = s3c64xx_iisv4_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iisv4); diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 91de11be274..b5b9c4d46e9 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -26,6 +26,7 @@ extern struct platform_device s3c_device_timer[]; extern struct platform_device s3c64xx_device_iis0; extern struct platform_device s3c64xx_device_iis1; +extern struct platform_device s3c64xx_device_iisv4; extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_usb; -- cgit v1.2.3 From b3748ddd80569ec753f62e709629b8c639143222 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 15 Jun 2009 11:23:20 +0100 Subject: [ARM] S3C64XX: Initial support for DVFS This patch provides initial support for CPU frequency scaling on the Samsung S3C ARM processors. Currently only S3C6410 processors are supported, though addition of another data table with supported clock rates should be sufficient to enable support for further CPUs. Use the regulator framework to provide optional support for DVFS in the S3C cpufreq driver. When a software controllable regulator is configured the driver will use it to lower the supply voltage when running at a lower frequency, giving improved power savings. When regulator support is disabled or no regulator can be obtained for VDDARM the driver will fall back to scaling only the frequency. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 6 +- arch/arm/plat-s3c64xx/Makefile | 1 + arch/arm/plat-s3c64xx/cpufreq.c | 262 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-s3c64xx/cpufreq.c (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 29475101a7b..aef63c8e3d2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1241,7 +1241,7 @@ endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX) source "drivers/cpufreq/Kconfig" @@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA default y select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_S3C64XX + bool "CPUfreq support for Samsung S3C64XX CPUs" + depends on CPU_FREQ && CPU_S3C6410 + endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 2ed5df34f9e..3c8882cd626 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -23,6 +23,7 @@ obj-y += gpiolib.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o +obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o # PM support diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c new file mode 100644 index 00000000000..e6e0843215d --- /dev/null +++ b/arch/arm/plat-s3c64xx/cpufreq.c @@ -0,0 +1,262 @@ +/* linux/arch/arm/plat-s3c64xx/cpufreq.c + * + * Copyright 2009 Wolfson Microelectronics plc + * + * S3C64xx CPUfreq Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct clk *armclk; +static struct regulator *vddarm; + +#ifdef CONFIG_CPU_S3C6410 +struct s3c64xx_dvfs { + unsigned int vddarm_min; + unsigned int vddarm_max; +}; + +static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { + [0] = { 1000000, 1000000 }, + [1] = { 1000000, 1050000 }, + [2] = { 1050000, 1100000 }, + [3] = { 1050000, 1150000 }, + [4] = { 1250000, 1350000 }, +}; + +static struct cpufreq_frequency_table s3c64xx_freq_table[] = { + { 0, 66000 }, + { 0, 133000 }, + { 1, 222000 }, + { 1, 266000 }, + { 2, 333000 }, + { 2, 400000 }, + { 3, 532000 }, + { 3, 533000 }, + { 4, 667000 }, + { 0, CPUFREQ_TABLE_END }, +}; +#endif + +static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table); +} + +static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) +{ + if (cpu != 0) + return 0; + + return clk_get_rate(armclk) / 1000; +} + +static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int ret; + unsigned int i; + struct cpufreq_freqs freqs; + struct s3c64xx_dvfs *dvfs; + + ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table, + target_freq, relation, &i); + if (ret != 0) + return ret; + + freqs.cpu = 0; + freqs.old = clk_get_rate(armclk) / 1000; + freqs.new = s3c64xx_freq_table[i].frequency; + freqs.flags = 0; + dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; + + if (freqs.old == freqs.new) + return 0; + + pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new > freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err; + } + } +#endif + + ret = clk_set_rate(armclk, freqs.new * 1000); + if (ret < 0) { + pr_err("cpufreq: Failed to set rate %dkHz: %d\n", + freqs.new, ret); + goto err; + } + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new < freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err_clk; + } + } +#endif + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + pr_debug("cpufreq: Set actual frequency %lukHz\n", + clk_get_rate(armclk) / 1000); + + return 0; + +err_clk: + if (clk_set_rate(armclk, freqs.old * 1000) < 0) + pr_err("Failed to restore original clock rate\n"); +err: + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +#ifdef CONFIG_REGULATOR +static void __init s3c64xx_cpufreq_constrain_voltages(void) +{ + int count, v, i, found; + struct cpufreq_frequency_table *freq; + struct s3c64xx_dvfs *dvfs; + + count = regulator_count_voltages(vddarm); + if (count < 0) { + pr_err("cpufreq: Unable to check supported voltages\n"); + return; + } + + freq = s3c64xx_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + if (freq->frequency == CPUFREQ_ENTRY_INVALID) + continue; + + dvfs = &s3c64xx_dvfs_table[freq->index]; + found = 0; + + for (i = 0; i < count; i++) { + v = regulator_list_voltage(vddarm, i); + if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) + found = 1; + } + + if (!found) { + pr_debug("cpufreq: %dkHz unsupported by regulator\n", + freq->frequency); + freq->frequency = CPUFREQ_ENTRY_INVALID; + } + + freq++; + } +} +#endif + +static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret; + struct cpufreq_frequency_table *freq; + + if (policy->cpu != 0) + return -EINVAL; + + if (s3c64xx_freq_table == NULL) { + pr_err("cpufreq: No frequency information for this CPU\n"); + return -ENODEV; + } + + armclk = clk_get(NULL, "armclk"); + if (IS_ERR(armclk)) { + pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", + PTR_ERR(armclk)); + return PTR_ERR(armclk); + } + +#ifdef CONFIG_REGULATOR + vddarm = regulator_get(NULL, "vddarm"); + if (IS_ERR(vddarm)) { + ret = PTR_ERR(vddarm); + pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); + pr_err("cpufreq: Only frequency scaling available\n"); + vddarm = NULL; + } else { + s3c64xx_cpufreq_constrain_voltages(); + } +#endif + + freq = s3c64xx_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + unsigned long r; + + /* Check for frequencies we can generate */ + r = clk_round_rate(armclk, freq->frequency * 1000); + r /= 1000; + if (r != freq->frequency) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + /* If we have no regulator then assume startup + * frequency is the maximum we can support. */ + if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + freq++; + } + + policy->cur = clk_get_rate(armclk) / 1000; + + /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI + * write plus clock reprogramming. */ + policy->cpuinfo.transition_latency = 2 * 1000 * 1000; + + ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); + if (ret != 0) { + pr_err("cpufreq: Failed to configure frequency table: %d\n", + ret); + regulator_put(vddarm); + clk_put(armclk); + } + + return ret; +} + +static struct cpufreq_driver s3c64xx_cpufreq_driver = { + .owner = THIS_MODULE, + .flags = 0, + .verify = s3c64xx_cpufreq_verify_speed, + .target = s3c64xx_cpufreq_set_target, + .get = s3c64xx_cpufreq_get_speed, + .init = s3c64xx_cpufreq_driver_init, + .name = "s3c", +}; + +static int __init s3c64xx_cpufreq_init(void) +{ + return cpufreq_register_driver(&s3c64xx_cpufreq_driver); +} +module_init(s3c64xx_cpufreq_init); -- cgit v1.2.3 From 9d76295ac6082449a64fd6fa981d2615a34e243d Mon Sep 17 00:00:00 2001 From: Andy Green Date: Tue, 19 May 2009 06:41:42 -0300 Subject: [ARM] GTA02/FreeRunner: Add machine definition This patch introduces the Openmoko GTA02 machine definition. Much of the code is based on Harald Welte's work, although it has been largely rewritten several times. This is intended to be the minimum machine definition to boot and be able to run a rootfs from NAND on GTA02 / FreeRunner. It does not bring up the framebuffer / Glamo and lacks many other peripheral drivers from outside the SoC. But once we have this basis in mainline kernel, we will be able to introduce the other drivers and add them here. Thanks to Sven Rebhan for his fixes to this patch (Kconfig and defconfig files). Signed-off-by: Andy Green Signed-off-by: Nelson Castillo [ben-linux@fluff.org: Fix the GPIO definitions] Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2442/Kconfig | 12 + arch/arm/mach-s3c2442/Makefile | 2 + arch/arm/mach-s3c2442/include/mach/gta02.h | 84 ++++ arch/arm/mach-s3c2442/mach-gta02.c | 646 +++++++++++++++++++++++++++++ 4 files changed, 744 insertions(+) create mode 100644 arch/arm/mach-s3c2442/include/mach/gta02.h create mode 100644 arch/arm/mach-s3c2442/mach-gta02.c (limited to 'arch') diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index b289d198020..103e913f225 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -24,6 +24,18 @@ config SMDK2440_CPU2442 depends on ARCH_S3C2440 select CPU_S3C2442 +config MACH_NEO1973_GTA02 + bool "Openmoko GTA02 / Freerunner phone" + select CPU_S3C2442 + select MFD_PCF50633 + select PCF50633_GPIO + select I2C + select POWER_SUPPLY + select MACH_NEO1973 + select S3C2410_PWM + help + Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone + endmenu diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile index 2a909c6c579..2a19113a576 100644 --- a/arch/arm/mach-s3c2442/Makefile +++ b/arch/arm/mach-s3c2442/Makefile @@ -12,5 +12,7 @@ obj- := obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C2442) += clock.o +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o + # Machine support diff --git a/arch/arm/mach-s3c2442/include/mach/gta02.h b/arch/arm/mach-s3c2442/include/mach/gta02.h new file mode 100644 index 00000000000..953331d8d56 --- /dev/null +++ b/arch/arm/mach-s3c2442/include/mach/gta02.h @@ -0,0 +1,84 @@ +#ifndef _GTA02_H +#define _GTA02_H + +#include + +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */ +#define GTA02v1_SYSTEM_REV 0x00000310 +#define GTA02v2_SYSTEM_REV 0x00000320 +#define GTA02v3_SYSTEM_REV 0x00000330 +#define GTA02v4_SYSTEM_REV 0x00000340 +#define GTA02v5_SYSTEM_REV 0x00000350 +/* since A7 is basically same as A6, we use A6 PCB ID */ +#define GTA02v6_SYSTEM_REV 0x00000360 + +#define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */ + +#define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0) +#define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1) +#define GTA02_GPIO_AUX_LED S3C2410_GPB(2) +#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3) +#define GTA02_GPIO_MODEM_RST S3C2410_GPB(5) +#define GTA02_GPIO_BT_EN S3C2410_GPB(6) +#define GTA02_GPIO_MODEM_ON S3C2410_GPB(7) +#define GTA02_GPIO_EXTINT8 S3C2410_GPB(8) +#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) + +#define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */ + +#define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */ +#define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */ +#define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */ + +#define GTA02_GPIO_nG1_INT S3C2410_GPF(0) +#define GTA02_GPIO_IO1 S3C2410_GPF(1) +#define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */ +#define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4) +#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */ +#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) +#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) + +#define GTA02_GPIO_3D_IRQ S3C2410_GPG(4) +#define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */ +#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */ +#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */ +#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */ + +#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */ +#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2 +#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4 +#define GTA02_GPIO_3D_RESET S3C2440_GPJ5 +#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */ +#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7 +#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8 +#define GTA02_GPIO_KEEPACT S3C2440_GPJ8 +#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10 +#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */ + +#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0 +#define GTA02_IRQ_MODEM IRQ_EINT1 +#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */ +#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4 +#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5 +#define GTA02_IRQ_AUX IRQ_EINT6 +#define GTA02_IRQ_nHOLD IRQ_EINT7 +#define GTA02_IRQ_PCF50633 IRQ_EINT9 +#define GTA02_IRQ_3D IRQ_EINT12 +#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */ +#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */ +#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */ +#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */ + +/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */ +#define GTA02_PCB_ID1_0 S3C2410_GPC(13) +#define GTA02_PCB_ID1_1 S3C2410_GPC(15) +#define GTA02_PCB_ID1_2 S3C2410_GPD(0) +#define GTA02_PCB_ID2_0 S3C2410_GPD(3) +#define GTA02_PCB_ID2_1 S3C2410_GPD(4) + +int gta02_get_pcb_revision(void); + +#endif /* _GTA02_H */ diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c new file mode 100644 index 00000000000..e23b581aa0e --- /dev/null +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -0,0 +1,646 @@ +/* + * linux/arch/arm/mach-s3c2442/mach-gta02.c + * + * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner. + * + * Copyright (C) 2006-2009 by Openmoko, Inc. + * Authors: Harald Welte + * Andy Green + * Werner Almesberger + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct pcf50633 *gta02_pcf; + +/* + * This gets called every 1ms when we paniced. + */ + +static long gta02_panic_blink(long count) +{ + long delay = 0; + static long last_blink; + static char led; + + /* Fast blink: 200ms period. */ + if (count - last_blink < 100) + return 0; + + led ^= 1; + gpio_direction_output(GTA02_GPIO_AUX_LED, led); + + last_blink = count; + + return delay; +} + + +static struct map_desc gta02_iodesc[] __initdata = { + { + .virtual = 0xe0000000, + .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000), + .length = SZ_1M, + .type = MT_DEVICE + }, +}; + +#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN) +#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) +#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) + +static struct s3c2410_uartcfg gta02_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +#ifdef CONFIG_CHARGER_PCF50633 +/* + * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin. + * We use this to recognize that we can pull 1A from the USB socket. + * + * These constants are the measured pcf50633 ADC levels with the 1A + * charger / 48K resistor, and with no pulldown resistor. + */ + +#define ADC_NOM_CHG_DETECT_1A 6 +#define ADC_NOM_CHG_DETECT_USB 43 + +static void +gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res) +{ + int ma; + + /* Interpret charger type */ + if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) { + + /* + * Sanity - stop GPO driving out now that we have a 1A charger + * GPO controls USB Host power generation on GTA02 + */ + pcf50633_gpio_set(pcf, PCF50633_GPO, 0); + + ma = 1000; + } else + ma = 100; + + pcf50633_mbc_usb_curlim_set(pcf, ma); +} + +static struct delayed_work gta02_charger_work; +static int gta02_usb_vbus_draw; + +static void gta02_charger_worker(struct work_struct *work) +{ + if (gta02_usb_vbus_draw) { + pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw); + return; + } + +#ifdef CONFIG_PCF50633_ADC + pcf50633_adc_async_read(gta02_pcf, + PCF50633_ADCC1_MUX_ADCIN1, + PCF50633_ADCC1_AVERAGE_16, + gta02_configure_pmu_for_charger, + NULL); +#else + /* + * If the PCF50633 ADC is disabled we fallback to a + * 100mA limit for safety. + */ + pcf50633_mbc_usb_curlim_set(pcf, 100); +#endif +} + +#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000) + +static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq) +{ + if (irq == PCF50633_IRQ_USBINS) { + schedule_delayed_work(>a02_charger_work, + GTA02_CHARGER_CONFIGURE_TIMEOUT); + + return; + } + + if (irq == PCF50633_IRQ_USBREM) { + cancel_delayed_work_sync(>a02_charger_work); + gta02_usb_vbus_draw = 0; + } +} + +static void gta02_udc_vbus_draw(unsigned int ma) +{ + if (!gta02_pcf) + return; + + gta02_usb_vbus_draw = ma; + + schedule_delayed_work(>a02_charger_work, + GTA02_CHARGER_CONFIGURE_TIMEOUT); +} +#else /* !CONFIG_CHARGER_PCF50633 */ +#define gta02_pmu_event_callback NULL +#define gta02_udc_vbus_draw NULL +#endif + +/* + * This is called when pc50633 is probed, unfortunately quite late in the + * day since it is an I2C bus device. Here we can belatedly define some + * platform devices with the advantage that we can mark the pcf50633 as the + * parent. This makes them get suspended and resumed with their parent + * the pcf50633 still around. + */ + +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf); + + +static char *gta02_batteries[] = { + "battery", +}; + +struct pcf50633_platform_data gta02_pcf_pdata = { + .resumers = { + [0] = PCF50633_INT1_USBINS | + PCF50633_INT1_USBREM | + PCF50633_INT1_ALARM, + [1] = PCF50633_INT2_ONKEYF, + [2] = PCF50633_INT3_ONKEY1S, + [3] = PCF50633_INT4_LOWSYS | + PCF50633_INT4_LOWBAT | + PCF50633_INT4_HIGHTMP, + }, + + .batteries = gta02_batteries, + .num_batteries = ARRAY_SIZE(gta02_batteries), + .reg_init_data = { + [PCF50633_REGULATOR_AUTO] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_DOWN1] = { + .constraints = { + .min_uV = 1300000, + .max_uV = 1600000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_DOWN2] = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_HCLDO] = { + .constraints = { + .min_uV = 2000000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + }, + }, + [PCF50633_REGULATOR_LDO1] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .state_mem = { + .enabled = 0, + }, + }, + }, + [PCF50633_REGULATOR_LDO2] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO3] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO4] = { + .constraints = { + .min_uV = 3200000, + .max_uV = 3200000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO5] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_LDO6] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + }, + }, + [PCF50633_REGULATOR_MEMLDO] = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .state_mem = { + .enabled = 1, + }, + }, + }, + + }, + .probe_done = gta02_pmu_attach_child_devices, + .mbc_event_callback = gta02_pmu_event_callback, +}; + + +/* NOR Flash. */ + +#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */ +#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */ + +static struct physmap_flash_data gta02_nor_flash_data = { + .width = 2, +}; + +static struct resource gta02_nor_flash_resource = { + .start = GTA02_FLASH_BASE, + .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gta02_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = >a02_nor_flash_data, + }, + .resource = >a02_nor_flash_resource, + .num_resources = 1, +}; + + +struct platform_device s3c24xx_pwm_device = { + .name = "s3c24xx_pwm", + .num_resources = 0, +}; + +static struct i2c_board_info gta02_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("pcf50633", 0x73), + .irq = GTA02_IRQ_PCF50633, + .platform_data = >a02_pcf_pdata, + }, + { + I2C_BOARD_INFO("wm8753", 0x1a), + }, +}; + +static struct s3c2410_nand_set gta02_nand_sets[] = { + [0] = { + /* + * This name is also hard-coded in the boot loaders, so + * changing it would would require all users to upgrade + * their boot loaders, some of which are stored in a NOR + * that is considered to be immutable. + */ + .name = "neo1973-nand", + .nr_chips = 1, + .use_bbt = 1, + .force_soft_ecc = 1, + }, +}; + +/* + * Choose a set of timings derived from S3C@2442B MCP54 + * data sheet (K5D2G13ACM-D075 MCP Memory). + */ + +static struct s3c2410_platform_nand gta02_nand_info = { + .tacls = 0, + .twrph0 = 25, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(gta02_nand_sets), + .sets = gta02_nand_sets, +}; + + +static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd) +{ + switch (cmd) { + case S3C2410_UDC_P_ENABLE: + pr_debug("%s S3C2410_UDC_P_ENABLE\n", __func__); + gpio_direction_output(GTA02_GPIO_USB_PULLUP, 1); + break; + case S3C2410_UDC_P_DISABLE: + pr_debug("%s S3C2410_UDC_P_DISABLE\n", __func__); + gpio_direction_output(GTA02_GPIO_USB_PULLUP, 0); + break; + case S3C2410_UDC_P_RESET: + pr_debug("%s S3C2410_UDC_P_RESET\n", __func__); + /* FIXME: Do something here. */ + } +} + +/* Get PMU to set USB current limit accordingly. */ +static struct s3c2410_udc_mach_info gta02_udc_cfg = { + .vbus_draw = gta02_udc_vbus_draw, + .udc_command = gta02_udc_command, + +}; + + + +static void gta02_bl_set_intensity(int intensity) +{ + struct pcf50633 *pcf = gta02_pcf; + int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); + + /* We map 8-bit intensity to 6-bit intensity in hardware. */ + intensity >>= 2; + + /* + * This can happen during, eg, print of panic on blanked console, + * but we can't service i2c without interrupts active, so abort. + */ + if (in_atomic()) { + printk(KERN_ERR "gta02_bl_set_intensity called while atomic\n"); + return; + } + + old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); + if (intensity == old_intensity) + return; + + /* We can't do this anywhere else. */ + pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5); + + if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3)) + old_intensity = 0; + + /* + * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60) + * if seen, you have to re-enable the LED unit. + */ + if (!intensity || !old_intensity) + pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0); + + /* Illegal to set LEDOUT to 0. */ + if (!intensity) + pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, 2); + else + pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, + intensity); + + if (intensity) + pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2); + +} + +static struct generic_bl_info gta02_bl_info = { + .name = "gta02-bl", + .max_intensity = 0xff, + .default_intensity = 0xff, + .set_bl_intensity = gta02_bl_set_intensity, +}; + +static struct platform_device gta02_bl_dev = { + .name = "generic-bl", + .id = 1, + .dev = { + .platform_data = >a02_bl_info, + }, +}; + + + +/* USB */ +static struct s3c2410_hcd_info gta02_usb_info = { + .port[0] = { + .flags = S3C_HCDFLG_USED, + }, + .port[1] = { + .flags = 0, + }, +}; + + +static void __init gta02_map_io(void) +{ + s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); +} + + +/* These are the guys that don't need to be children of PMU. */ + +static struct platform_device *gta02_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_sdi, + &s3c_device_usbgadget, + &s3c_device_nand, + >a02_nor_flash, + &s3c24xx_pwm_device, + &s3c_device_iis, + &s3c_device_i2c0, +}; + +/* These guys DO need to be children of PMU. */ + +static struct platform_device *gta02_devices_pmu_children[] = { + >a02_bl_dev, +}; + + +/* + * This is called when pc50633 is probed, quite late in the day since it is an + * I2C bus device. Here we can define platform devices with the advantage that + * we can mark the pcf50633 as the parent. This makes them get suspended and + * resumed with their parent the pcf50633 still around. All devices whose + * operation depends on something from pcf50633 must have this relationship + * made explicit like this, or suspend and resume will become an unreliable + * hellworld. + */ + +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf) +{ + int n; + + /* Grab a copy of the now probed PMU pointer. */ + gta02_pcf = pcf; + + for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++) + gta02_devices_pmu_children[n]->dev.parent = pcf->dev; + + platform_add_devices(gta02_devices_pmu_children, + ARRAY_SIZE(gta02_devices_pmu_children)); +} + +static void gta02_poweroff(void) +{ + pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1); +} + +static void __init gta02_machine_init(void) +{ + /* Set the panic callback to make AUX LED blink at ~5Hz. */ + panic_blink = gta02_panic_blink; + + s3c_pm_init(); + +#ifdef CONFIG_CHARGER_PCF50633 + INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); +#endif + + s3c_device_usb.dev.platform_data = >a02_usb_info; + s3c_device_nand.dev.platform_data = >a02_nand_info; + + s3c24xx_udc_set_platdata(>a02_udc_cfg); + s3c_i2c0_set_platdata(NULL); + + i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); + + platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); + pm_power_off = gta02_poweroff; +} + + +MACHINE_START(NEO1973_GTA02, "GTA02") + /* Maintainer: Nelson Castillo */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = gta02_map_io, + .init_irq = s3c24xx_init_irq, + .init_machine = gta02_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END -- cgit v1.2.3 From c3c2174031def62eeb8433dee8ef7e8d9493b1cf Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 19 Jun 2009 11:28:48 +0100 Subject: [ARM] 5555/1: RealView: Include asm/smp_twd.h in realview-pbx.c This header file is needed for twd_base. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/realview_pbx.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 1fe294d0bf9..ede2a57240a 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 41184f6a5ef0d88529904d54f06f88b67fb76f4a Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 19 Jun 2009 11:30:12 +0100 Subject: [ARM] 5556/1: Fix the irq_desc.cpu references The cpu member of struct irq_desc was recently renamed to node. The patch renames the ARM references to the old member. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/common/gic.c | 2 +- arch/arm/kernel/irq.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 664c7b8b1ba..337741f734a 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) u32 val; spin_lock(&irq_controller_lock); - irq_desc[irq].cpu = cpu; + irq_desc[irq].node = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 6874c7dca75..096f600dc8d 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -167,7 +167,7 @@ void __init init_IRQ(void) #ifdef CONFIG_SMP cpumask_setall(bad_irq_desc.affinity); - bad_irq_desc.cpu = smp_processor_id(); + bad_irq_desc.node = smp_processor_id(); #endif init_arch_irq(); } @@ -176,7 +176,7 @@ void __init init_IRQ(void) static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) { - pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); + pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); spin_lock_irq(&desc->lock); desc->chip->set_affinity(irq, cpumask_of(cpu)); @@ -195,7 +195,7 @@ void migrate_irqs(void) for (i = 0; i < NR_IRQS; i++) { struct irq_desc *desc = irq_desc + i; - if (desc->cpu == cpu) { + if (desc->node == cpu) { unsigned int newcpu = cpumask_any_and(desc->affinity, cpu_online_mask); if (newcpu >= nr_cpu_ids) { -- cgit v1.2.3 From c2860d43f5dfab599fc1308ab61b1d3e30801ceb Mon Sep 17 00:00:00 2001 From: "George G. Davis" Date: Thu, 4 Jun 2009 17:16:04 +0100 Subject: [ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup support From: Min Zhang Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP, PUSH, STM and STRD instructions. Alignment fault fixup support for the remaining 32-bit Thumb-2 load/store instruction cases is not included since ARMv6 and later processors include hardware support for loads and stores of unaligned words and halfwords. Signed-off-by: Min Zhang Signed-off-by: George G. Davis Signed-off-by: Russell King --- arch/arm/mm/alignment.c | 139 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 119 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 3a398befed4..03cd27d917b 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -62,6 +62,12 @@ #define SHIFT_ASR 0x40 #define SHIFT_RORRRX 0x60 +#define BAD_INSTR 0xdeadc0de + +/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ +#define IS_T32(hi16) \ + (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800)) + static unsigned long ai_user; static unsigned long ai_sys; static unsigned long ai_skipped; @@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, struct pt_regs *regs) { unsigned int rd = RD_BITS(instr); - - if (((rd & 1) == 1) || (rd == 14)) + unsigned int rd2; + int load; + + if ((instr & 0xfe000000) == 0xe8000000) { + /* ARMv7 Thumb-2 32-bit LDRD/STRD */ + rd2 = (instr >> 8) & 0xf; + load = !!(LDST_L_BIT(instr)); + } else if (((rd & 1) == 1) || (rd == 14)) goto bad; + else { + load = ((instr & 0xf0) == 0xd0); + rd2 = rd + 1; + } ai_dword += 1; if (user_mode(regs)) goto user; - if ((instr & 0xf0) == 0xd0) { + if (load) { unsigned long val; get32_unaligned_check(val, addr); regs->uregs[rd] = val; get32_unaligned_check(val, addr + 4); - regs->uregs[rd + 1] = val; + regs->uregs[rd2] = val; } else { put32_unaligned_check(regs->uregs[rd], addr); - put32_unaligned_check(regs->uregs[rd + 1], addr + 4); + put32_unaligned_check(regs->uregs[rd2], addr + 4); } return TYPE_LDST; user: - if ((instr & 0xf0) == 0xd0) { + if (load) { unsigned long val; get32t_unaligned_check(val, addr); regs->uregs[rd] = val; get32t_unaligned_check(val, addr + 4); - regs->uregs[rd + 1] = val; + regs->uregs[rd2] = val; } else { put32t_unaligned_check(regs->uregs[rd], addr); - put32t_unaligned_check(regs->uregs[rd + 1], addr + 4); + put32t_unaligned_check(regs->uregs[rd2], addr + 4); } return TYPE_LDST; @@ -616,8 +632,72 @@ thumb2arm(u16 tinstr) /* Else fall through for illegal instruction case */ default: - return 0xdeadc0de; + return BAD_INSTR; + } +} + +/* + * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction + * handlable by ARM alignment handler, also find the corresponding handler, + * so that we can reuse ARM userland alignment fault fixups for Thumb. + * + * @pinstr: original Thumb-2 instruction; returns new handlable instruction + * @regs: register context. + * @poffset: return offset from faulted addr for later writeback + * + * NOTES: + * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. + * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt) + */ +static void * +do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, + union offset_union *poffset) +{ + unsigned long instr = *pinstr; + u16 tinst1 = (instr >> 16) & 0xffff; + u16 tinst2 = instr & 0xffff; + poffset->un = 0; + + switch (tinst1 & 0xffe0) { + /* A6.3.5 Load/Store multiple */ + case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ + case 0xe8a0: /* ...above writeback version */ + case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ + case 0xe920: /* ...above writeback version */ + /* no need offset decision since handler calculates it */ + return do_alignment_ldmstm; + + case 0xf840: /* POP/PUSH T3 (single register) */ + if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { + u32 L = !!(LDST_L_BIT(instr)); + const u32 subset[2] = { + 0xe92d0000, /* STMDB sp!,{registers} */ + 0xe8bd0000, /* LDMIA sp!,{registers} */ + }; + *pinstr = subset[L] | (1<un = (tinst2 & 0xff) << 2; + case 0xe940: + case 0xe9c0: + return do_alignment_ldrdstrd; + + /* + * No need to handle load/store instructions up to word size + * since ARMv6 and later CPUs can perform unaligned accesses. + */ + default: + break; } + return NULL; } static int @@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) mm_segment_t fs; unsigned int fault; u16 tinstr = 0; + int isize = 4; + int thumb2_32b = 0; instrptr = instruction_pointer(regs); @@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) set_fs(KERNEL_DS); if (thumb_mode(regs)) { fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); - if (!(fault)) - instr = thumb2arm(tinstr); + if (!fault) { + if (cpu_architecture() >= CPU_ARCH_ARMv7 && + IS_T32(tinstr)) { + /* Thumb-2 32-bit */ + u16 tinst2 = 0; + fault = __get_user(tinst2, (u16 *)(instrptr+2)); + instr = (tinstr << 16) | tinst2; + thumb2_32b = 1; + } else { + isize = 2; + instr = thumb2arm(tinstr); + } + } } else fault = __get_user(instr, (u32 *)instrptr); set_fs(fs); @@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) fixup: - regs->ARM_pc += thumb_mode(regs) ? 2 : 4; + regs->ARM_pc += isize; switch (CODING_BITS(instr)) { case 0x00000000: /* 3.13.4 load/store instruction extensions */ @@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) handler = do_alignment_ldrstr; break; - case 0x08000000: /* ldm or stm */ - handler = do_alignment_ldmstm; + case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ + if (thumb2_32b) + handler = do_alignment_t32_to_handler(&instr, regs, &offset); + else + handler = do_alignment_ldmstm; break; default: goto bad; } + if (!handler) + goto bad; type = handler(addr, instr, regs); - if (type == TYPE_ERROR || type == TYPE_FAULT) + if (type == TYPE_ERROR || type == TYPE_FAULT) { + regs->ARM_pc -= isize; goto bad_or_fault; + } if (type == TYPE_LDST) do_alignment_finish_ldst(addr, instr, regs, offset); @@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) bad_or_fault: if (type == TYPE_ERROR) goto bad; - regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; /* * We got a fault - fix it up, or die. */ @@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) */ printk(KERN_ERR "Alignment trap: not handling instruction " "%0*lx at [<%08lx>]\n", - thumb_mode(regs) ? 4 : 8, - thumb_mode(regs) ? tinstr : instr, instrptr); + isize << 1, + isize == 2 ? tinstr : instr, instrptr); ai_skipped += 1; return 1; @@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " "Address=0x%08lx FSR 0x%03x\n", current->comm, task_pid_nr(current), instrptr, - thumb_mode(regs) ? 4 : 8, - thumb_mode(regs) ? tinstr : instr, + isize << 1, + isize == 2 ? tinstr : instr, addr, fsr); if (ai_usermode & UM_FIXUP) -- cgit v1.2.3 From 7436127ce9042f95a10bb5423f726fd63a61934d Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 19 Jun 2009 16:39:29 +0100 Subject: [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU Not discarding these sections when hotplug isn't available prevents the kernel from building. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/vmlinux.lds.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 6c077979254..4340bf3d2c8 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -84,6 +84,14 @@ SECTIONS *(.exitcall.exit) *(.ARM.exidx.exit.text) *(.ARM.extab.exit.text) +#ifndef CONFIG_HOTPLUG_CPU + *(.ARM.exidx.cpuexit.text) + *(.ARM.extab.cpuexit.text) +#endif +#ifndef CONFIG_HOTPLUG + *(.ARM.exidx.devexit.text) + *(.ARM.extab.devexit.text) +#endif #ifndef CONFIG_MMU *(.fixup) *(__ex_table) -- cgit v1.2.3 From c894ed6956f126d60d888e8efc5fb3a595ba89ae Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 19 Jun 2009 16:42:11 +0100 Subject: [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks There are situations where the unwinder goes beyond stack boundaries and unwinds random data. This patch moves the stack boundaries check after the unwind_exec_insn() call and adds an extra check for possible infinite loops (like "mov pc, lr" with pc == lr). The patch also fixes a bug in the unwind instructions interpreter. The 0xb0 instruction can only set PC to LR if this wasn't already set by a previous instruction (this is used on exceptions taken while in kernel mode where svc_entry is annotated with ".save {r0 - pc}"). Tested-by: Tony Lindgren Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/unwind.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 1dedc2c7ff4..dd56e11f339 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -212,7 +212,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) ctrl->vrs[14] = *vsp++; ctrl->vrs[SP] = (unsigned long)vsp; } else if (insn == 0xb0) { - ctrl->vrs[PC] = ctrl->vrs[LR]; + if (ctrl->vrs[PC] == 0) + ctrl->vrs[PC] = ctrl->vrs[LR]; /* no further processing */ ctrl->entries = 0; } else if (insn == 0xb1) { @@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame) } while (ctrl.entries > 0) { - int urc; - - if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) - return -URC_FAILURE; - urc = unwind_exec_insn(&ctrl); + int urc = unwind_exec_insn(&ctrl); if (urc < 0) return urc; + if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) + return -URC_FAILURE; } if (ctrl.vrs[PC] == 0) ctrl.vrs[PC] = ctrl.vrs[LR]; + /* check for infinite loop */ + if (frame->pc == ctrl.vrs[PC]) + return -URC_FAILURE; + frame->fp = ctrl.vrs[FP]; frame->sp = ctrl.vrs[SP]; frame->lr = ctrl.vrs[LR]; @@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame) void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) { struct stackframe frame; - unsigned long high, low; register unsigned long current_sp asm ("sp"); pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); @@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) frame.pc = thread_saved_pc(tsk); } - low = frame.sp & ~(THREAD_SIZE - 1); - high = low + THREAD_SIZE; - while (1) { int urc; unsigned long where = frame.pc; -- cgit v1.2.3 From feb97c3644a560ffdf9a17c65b1df807b5b4432f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 19 Jun 2009 16:43:08 +0100 Subject: [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit When a kthread function returns, it branches to do_exit(). However, the unwinding information isn't valid anymore and any stack trace caused by do_exit() may be incorrect. This patch adds a kernel_thread_exit() function and annotated with '.cantunwind' so that the unwinder stops when reaching it. Tested-by: Tony Lindgren Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/process.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 1585423699e..56820cce91a 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -352,6 +352,23 @@ asm( ".section .text\n" " .size kernel_thread_helper, . - kernel_thread_helper\n" " .previous"); +#ifdef CONFIG_ARM_UNWIND +extern void kernel_thread_exit(long code); +asm( ".section .text\n" +" .align\n" +" .type kernel_thread_exit, #function\n" +"kernel_thread_exit:\n" +" .fnstart\n" +" .cantunwind\n" +" bl do_exit\n" +" nop\n" +" .fnend\n" +" .size kernel_thread_exit, . - kernel_thread_exit\n" +" .previous"); +#else +#define kernel_thread_exit do_exit +#endif + /* * Create a kernel thread. */ @@ -363,7 +380,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) regs.ARM_r1 = (unsigned long)arg; regs.ARM_r2 = (unsigned long)fn; - regs.ARM_r3 = (unsigned long)do_exit; + regs.ARM_r3 = (unsigned long)kernel_thread_exit; regs.ARM_pc = (unsigned long)kernel_thread_helper; regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; -- cgit v1.2.3 From 5587931c30dcf778cf7071d1cbac8ea584706dd8 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Tue, 16 Jun 2009 20:05:57 +0900 Subject: [ARM] Add old Feroceon support to compressed/head.S This patch supports the cache handling for some old Feroceon cores for which the CPU ID is like 0x41159260. This is a complement to commit ab6d15d50637fc25ee941710b23fed09ceb28db3. Signed-off-by: Joonyoung Shim Signed-off-by: Nicolas Pitre --- arch/arm/boot/compressed/head.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 01d49be3b2c..4515728c534 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -674,6 +674,15 @@ proc_types: b __armv4_mmu_cache_off b __armv5tej_mmu_cache_flush +#ifdef CONFIG_CPU_FEROCEON_OLD_ID + /* this conflicts with the standard ARMv5TE entry */ + .long 0x41009260 @ Old Feroceon + .long 0xff00fff0 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush +#endif + .word 0x66015261 @ FA526 .word 0xff01fff1 b __fa526_cache_on -- cgit v1.2.3 From 6adb8f388ef2f23d4a81e1e42d15f22d62749a06 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:24 -0600 Subject: OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index c080c82521e..84781a6cd26 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -102,9 +102,6 @@ configure_core_dpll: orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val str r12, [r11] ldr r12, [r11] @ posted-write barrier for CM - mov r12, #0x800 @ wait for the clock to stabilise - cmp r3, #2 - bne wait_clk_stable bx lr wait_clk_stable: subs r12, r12, #1 -- cgit v1.2.3 From 2f135eaf182761bb9a5cbd5138a447b0ad2a1fef Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:25 -0600 Subject: OMAP3 clock: initialize SDRC timings at kernel start On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c | 3 --- arch/arm/mach-omap2/io.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 9e43fe5209d..5458ab3bf65 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -718,9 +718,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (clk != &dpll3_m2_ck) return -EINVAL; - if (rate == clk->rate) - return 0; - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 32afd944821..3a86b0f6603 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -21,6 +21,7 @@ #include #include #include +#include #include @@ -241,6 +242,40 @@ void __init omap2_map_common_io(void) omapfb_reserve_sdram(); } +/* + * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters + * + * Sets the CORE DPLL3 M2 divider to the same value that it's at + * currently. This has the effect of setting the SDRC SDRAM AC timing + * registers to the values currently defined by the kernel. Currently + * only defined for OMAP3; will return 0 if called on OMAP2. Returns + * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, + * or passes along the return value of clk_set_rate(). + */ +static int __init _omap2_init_reprogram_sdrc(void) +{ + struct clk *dpll3_m2_ck; + int v = -EINVAL; + long rate; + + if (!cpu_is_omap34xx()) + return 0; + + dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); + if (!dpll3_m2_ck) + return -EINVAL; + + rate = clk_get_rate(dpll3_m2_ck); + pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); + v = clk_set_rate(dpll3_m2_ck, rate); + if (v) + pr_err("dpll3_m2_clk rate change failed: %d\n", v); + + clk_put(dpll3_m2_ck); + + return v; +} + void __init omap2_init_common_hw(struct omap_sdrc_params *sp) { omap2_mux_init(); @@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp) clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); omap2_clk_init(); omap2_sdrc_init(sp); + _omap2_init_reprogram_sdrc(); #endif gpmc_init(); } -- cgit v1.2.3 From c9812d042a21eb492a36cfabf9f41107f5ecee3d Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:26 -0600 Subject: OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c | 30 ++++++++++++++++++++++++++++-- arch/arm/mach-omap2/sram34xx.S | 20 +++++++++----------- arch/arm/plat-omap/include/mach/sram.h | 4 ++-- arch/arm/plat-omap/sram.c | 8 +++++--- 4 files changed, 44 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 5458ab3bf65..4bfa650bb34 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = { #define MIN_SDRC_DLL_LOCK_FREQ 83000000 +#define CYCLES_PER_MHZ 1000000 + +/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ +#define SDRC_MPURATE_SCALE 8 + +/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ +#define SDRC_MPURATE_BASE_SHIFT 9 + +/* + * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at + * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize + */ +#define SDRC_MPURATE_LOOPS 96 + /** * omap3_dpll_recalc - recalculate DPLL rate * @clk: DPLL struct clk @@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; u32 unlock_dll = 0; - unsigned long validrate, sdrcrate; + u32 c; + unsigned long validrate, sdrcrate, mpurate; struct omap_sdrc_params *sp; if (!clk || !rate) @@ -737,6 +752,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } + /* + * XXX This only needs to be done when the CPU frequency changes + */ + mpurate = arm_fck.rate / CYCLES_PER_MHZ; + c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; + c += 1; /* for safety */ + c *= SDRC_MPURATE_LOOPS; + c >>= SDRC_MPURATE_SCALE; + if (c == 0) + c = 1; + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", @@ -747,7 +773,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div, unlock_dll); + sp->actim_ctrlb, new_div, unlock_dll, c); return 0; } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 84781a6cd26..8d4a88c3071 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -42,10 +42,14 @@ * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for * SDRC rates < 83MHz + * r5 = number of MPU cycles to wait for SDRC to stabilize after + * reprogramming the SDRC when switching to a slower MPU speed + * */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack ldr r4, [sp, #52] @ pull extra args off the stack + ldr r5, [sp, #56] @ load extra args from the stack dsb @ flush buffered writes to interconnect cmp r3, #0x2 blne configure_sdrc @@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll) bleq wait_dll_unlock blne wait_dll_lock cmp r3, #0x1 - blne configure_sdrc + beq return_to_sdram + bl configure_sdrc + mov r12, r5 @ if slowing, wait for SDRC to stabilize + bl wait_clk_stable +return_to_sdram: isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return @@ -106,16 +114,6 @@ configure_core_dpll: wait_clk_stable: subs r12, r12, #1 bne wait_clk_stable - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop bx lr enable_sdrc: ldr r11, omap3_cm_iclken1_core diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index dca7c16ae90..c32fa0a220d 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index a5b9bcd6b10..79c0f025442 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void) static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, - u32 m2, u32 unlock_dll); + u32 m2, u32 unlock_dll, + u32 f); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) + u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, + u32 f) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll); + unlock_dll, f); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3 From d0ba3922ae241a87d22a1c3ffad72b96fe993c9a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:27 -0600 Subject: OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c | 4 ++-- arch/arm/mach-omap2/sram34xx.S | 8 +++++++- arch/arm/plat-omap/include/mach/sram.h | 4 ++-- arch/arm/plat-omap/sram.c | 6 +++--- 4 files changed, 14 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 4bfa650bb34..cf41ab55fa9 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -771,9 +771,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* REVISIT: SRAM code doesn't support other M2 divisors yet */ WARN_ON(new_div != 1 && new_div != 2); - /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div, unlock_dll, c); + sp->actim_ctrlb, new_div, unlock_dll, c, + sp->mr); return 0; } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 8d4a88c3071..d13f1cc4bd5 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -44,12 +44,14 @@ * SDRC rates < 83MHz * r5 = number of MPU cycles to wait for SDRC to stabilize after * reprogramming the SDRC when switching to a slower MPU speed + * r6 = SDRC_MR_0 register value * */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack ldr r4, [sp, #52] @ pull extra args off the stack ldr r5, [sp, #56] @ load extra args from the stack + ldr r6, [sp, #60] @ load extra args from the stack dsb @ flush buffered writes to interconnect cmp r3, #0x2 blne configure_sdrc @@ -151,7 +153,9 @@ configure_sdrc: str r1, [r11] ldr r11, omap3_sdrc_actim_ctrlb str r2, [r11] - ldr r2, [r11] @ posted-write barrier for SDRC + ldr r11, omap3_sdrc_mr_0 + str r6, [r11] + ldr r6, [r11] @ posted-write barrier for SDRC bx lr omap3_sdrc_power: @@ -168,6 +172,8 @@ omap3_sdrc_actim_ctrla: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) omap3_sdrc_actim_ctrlb: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) +omap3_sdrc_mr_0: + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) omap3_sdrc_dlla_status: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) omap3_sdrc_dlla_ctrl: diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index c32fa0a220d..4f87056a367 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 79c0f025442..7dadf1a59fb 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f); + u32 f, u32 sdrc_mr); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f) + u32 f, u32 sdrc_mr) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll, f); + unlock_dll, f, sdrc_mr); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3 From 4267b5d15269ea6b26736a2ccd4c213e63e547ab Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:27 -0600 Subject: OMAP3 SRAM: add more comments on the SRAM code Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 45 ++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index d13f1cc4bd5..37a1e1fc0ab 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -3,13 +3,12 @@ * * Omap3 specific functions that need to be run in internal SRAM * - * (C) Copyright 2007 - * Texas Instruments Inc. - * Rajendra Nayak + * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. + * Copyright (C) 2008 Nokia Corporation * - * (C) Copyright 2004 - * Texas Instruments, + * Rajendra Nayak * Richard Woodruff + * Paul Walmsley * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -38,13 +37,16 @@ .text /* - * Change frequency of core dpll - * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 - * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for + * omap3_sram_configure_core_dpll - change DPLL3 M2 divider + * r0 = new SDRC_RFR_CTRL register contents + * r1 = new SDRC_ACTIM_CTRLA register contents + * r2 = new SDRC_ACTIM_CTRLB register contents + * r3 = new M2 divider setting (only 1 and 2 supported right now) + * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for * SDRC rates < 83MHz * r5 = number of MPU cycles to wait for SDRC to stabilize after * reprogramming the SDRC when switching to a slower MPU speed - * r6 = SDRC_MR_0 register value + * r6 = new SDRC_MR_0 register value * */ ENTRY(omap3_sram_configure_core_dpll) @@ -53,22 +55,22 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r5, [sp, #56] @ load extra args from the stack ldr r6, [sp, #60] @ load extra args from the stack dsb @ flush buffered writes to interconnect - cmp r3, #0x2 - blne configure_sdrc - cmp r4, #0x1 + cmp r3, #0x2 @ if increasing SDRC clk rate, + blne configure_sdrc @ program the SDRC regs early (for RFR) + cmp r4, #0x1 @ set the intended DLL state bleq unlock_dll blne lock_dll - bl sdram_in_selfrefresh @ put the SDRAM in self refresh - bl configure_core_dpll - bl enable_sdrc - cmp r4, #0x1 + bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC + bl configure_core_dpll @ change the DPLL3 M2 divider + bl enable_sdrc @ take SDRC out of idle + cmp r4, #0x1 @ wait for DLL status to change bleq wait_dll_unlock blne wait_dll_lock - cmp r3, #0x1 - beq return_to_sdram - bl configure_sdrc - mov r12, r5 @ if slowing, wait for SDRC to stabilize - bl wait_clk_stable + cmp r3, #0x1 @ if increasing SDRC clk rate, + beq return_to_sdram @ return to SDRAM code, otherwise, + bl configure_sdrc @ reprogram SDRC regs now + mov r12, r5 + bl wait_clk_stable @ wait for SDRC to stabilize return_to_sdram: isb @ prevent speculative exec past here mov r0, #0 @ return value @@ -93,6 +95,7 @@ sdram_in_selfrefresh: bic r12, r12, #0x4 @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC +idle_sdrc: ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg ldr r12, [r11] bic r12, r12, #0x2 @ disable iclk bit for SDRC -- cgit v1.2.3 From df14e4747aa58126a508ae26661c73d83127c831 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:28 -0600 Subject: OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 53 ++++++++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 37a1e1fc0ab..16eb4efa8b7 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -36,6 +36,29 @@ .text +/* r4 parameters */ +#define SDRC_NO_UNLOCK_DLL 0x0 +#define SDRC_UNLOCK_DLL 0x1 + +/* SDRC_DLLA_CTRL bit settings */ +#define DLLIDLE_MASK 0x4 + +/* SDRC_DLLA_STATUS bit settings */ +#define LOCKSTATUS_MASK 0x4 + +/* SDRC_POWER bit settings */ +#define SRFRONIDLEREQ_MASK 0x40 +#define PWDENA_MASK 0x4 + +/* CM_IDLEST1_CORE bit settings */ +#define ST_SDRC_MASK 0x2 + +/* CM_ICLKEN1_CORE bit settings */ +#define EN_SDRC_MASK 0x2 + +/* CM_CLKSEL1_PLL bit settings */ +#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b + /* * omap3_sram_configure_core_dpll - change DPLL3 M2 divider * r0 = new SDRC_RFR_CTRL register contents @@ -57,13 +80,13 @@ ENTRY(omap3_sram_configure_core_dpll) dsb @ flush buffered writes to interconnect cmp r3, #0x2 @ if increasing SDRC clk rate, blne configure_sdrc @ program the SDRC regs early (for RFR) - cmp r4, #0x1 @ set the intended DLL state + cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state bleq unlock_dll blne lock_dll bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC bl configure_core_dpll @ change the DPLL3 M2 divider bl enable_sdrc @ take SDRC out of idle - cmp r4, #0x1 @ wait for DLL status to change + cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change bleq wait_dll_unlock blne wait_dll_lock cmp r3, #0x1 @ if increasing SDRC clk rate, @@ -78,33 +101,33 @@ return_to_sdram: unlock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - orr r12, r12, #0x4 + orr r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) bx lr lock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - bic r12, r12, #0x4 + bic r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) bx lr sdram_in_selfrefresh: ldr r11, omap3_sdrc_power @ read the SDRC_POWER register ldr r12, [r11] @ read the contents of SDRC_POWER mov r9, r12 @ keep a copy of SDRC_POWER bits - orr r12, r12, #0x40 @ enable self refresh on idle req - bic r12, r12, #0x4 @ clear PWDENA + orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle + bic r12, r12, #PWDENA_MASK @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC idle_sdrc: ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg ldr r12, [r11] - bic r12, r12, #0x2 @ disable iclk bit for SDRC + bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC str r12, [r11] wait_sdrc_idle: ldr r11, omap3_cm_idlest1_core ldr r12, [r11] - and r12, r12, #0x2 @ check for SDRC idle - cmp r12, #2 + and r12, r12, #ST_SDRC_MASK @ check for SDRC idle + cmp r12, #ST_SDRC_MASK bne wait_sdrc_idle bx lr configure_core_dpll: @@ -112,7 +135,7 @@ configure_core_dpll: ldr r12, [r11] ldr r10, core_m2_mask_val @ modify m2 for core dpll and r12, r12, r10 - orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val + orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT str r12, [r11] ldr r12, [r11] @ posted-write barrier for CM bx lr @@ -123,12 +146,12 @@ wait_clk_stable: enable_sdrc: ldr r11, omap3_cm_iclken1_core ldr r12, [r11] - orr r12, r12, #0x2 @ enable iclk bit for SDRC + orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC str r12, [r11] wait_sdrc_idle1: ldr r11, omap3_cm_idlest1_core ldr r12, [r11] - and r12, r12, #0x2 + and r12, r12, #ST_SDRC_MASK cmp r12, #0 bne wait_sdrc_idle1 restore_sdrc_power_val: @@ -138,14 +161,14 @@ restore_sdrc_power_val: wait_dll_lock: ldr r11, omap3_sdrc_dlla_status ldr r12, [r11] - and r12, r12, #0x4 - cmp r12, #0x4 + and r12, r12, #LOCKSTATUS_MASK + cmp r12, #LOCKSTATUS_MASK bne wait_dll_lock bx lr wait_dll_unlock: ldr r11, omap3_sdrc_dlla_status ldr r12, [r11] - and r12, r12, #0x4 + and r12, r12, #LOCKSTATUS_MASK cmp r12, #0x0 bne wait_dll_unlock bx lr -- cgit v1.2.3 From 3afec6332e1e7cf2d74e0bf08160a68f43a59073 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 19 Jun 2009 19:08:29 -0600 Subject: OMAP3: Add support for DPLL3 divisor values higher than 2 Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c | 9 +++------ arch/arm/mach-omap2/sram34xx.S | 8 +++++--- arch/arm/plat-omap/include/mach/sram.h | 6 ++++-- arch/arm/plat-omap/sram.c | 6 +++--- 4 files changed, 15 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index cf41ab55fa9..045da923e75 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -739,9 +739,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrcrate = sdrc_ick.rate; if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) - 1); + sdrcrate <<= ((rate / clk->rate) >> 1); else - sdrcrate >>= ((clk->rate / rate) - 1); + sdrcrate >>= ((clk->rate / rate) >> 1); sp = omap2_sdrc_get_params(sdrcrate); if (!sp) @@ -768,12 +768,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); - /* REVISIT: SRAM code doesn't support other M2 divisors yet */ - WARN_ON(new_div != 1 && new_div != 2); - omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb, new_div, unlock_dll, c, - sp->mr); + sp->mr, rate > clk->rate); return 0; } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 16eb4efa8b7..487fa8609cd 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -70,6 +70,7 @@ * r5 = number of MPU cycles to wait for SDRC to stabilize after * reprogramming the SDRC when switching to a slower MPU speed * r6 = new SDRC_MR_0 register value + * r7 = increasing SDRC rate? (1 = yes, 0 = no) * */ ENTRY(omap3_sram_configure_core_dpll) @@ -77,9 +78,10 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #52] @ pull extra args off the stack ldr r5, [sp, #56] @ load extra args from the stack ldr r6, [sp, #60] @ load extra args from the stack + ldr r7, [sp, #64] @ load extra args from the stack dsb @ flush buffered writes to interconnect - cmp r3, #0x2 @ if increasing SDRC clk rate, - blne configure_sdrc @ program the SDRC regs early (for RFR) + cmp r7, #1 @ if increasing SDRC clk rate, + bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state bleq unlock_dll blne lock_dll @@ -89,7 +91,7 @@ ENTRY(omap3_sram_configure_core_dpll) cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change bleq wait_dll_unlock blne wait_dll_lock - cmp r3, #0x1 @ if increasing SDRC clk rate, + cmp r7, #1 @ if increasing SDRC clk rate, beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now mov r12, r5 diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index 4f87056a367..4d53cc59d7a 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f, u32 sdrc_mr); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f, u32 sdrc_mr); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 7dadf1a59fb..65006df3f1b 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f, u32 sdrc_mr); + u32 f, u32 sdrc_mr, u32 inc); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f, u32 sdrc_mr) + u32 f, u32 sdrc_mr, u32 inc) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll, f, sdrc_mr); + unlock_dll, f, sdrc_mr, inc); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3 From 7b7bcefa35d62fec64c3615a6bef7866f34c7cc9 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:29 -0600 Subject: OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz). Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 487fa8609cd..f41f8d96ddb 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -41,8 +41,18 @@ #define SDRC_UNLOCK_DLL 0x1 /* SDRC_DLLA_CTRL bit settings */ +#define FIXEDDELAY_SHIFT 24 +#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) #define DLLIDLE_MASK 0x4 +/* + * SDRC_DLLA_CTRL default values: TI hardware team indicates that + * FIXEDDELAY should be initialized to 0xf. This apparently was + * empirically determined during process testing, so no derivation + * was provided. + */ +#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) + /* SDRC_DLLA_STATUS bit settings */ #define LOCKSTATUS_MASK 0x4 @@ -103,6 +113,8 @@ return_to_sdram: unlock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] + and r12, r12, #FIXEDDELAY_MASK + orr r12, r12, #FIXEDDELAY_DEFAULT orr r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) bx lr -- cgit v1.2.3 From 2687069f3ac297b820c58de7222e4d16adbca498 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Fri, 19 Jun 2009 19:08:30 -0600 Subject: OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: Roel Kluin Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/powerdomain.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ba528f85749..b0665f161c0 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) udelay(1); } - if (i < MAX_CLOCK_ENABLE_WAIT) + if (i <= MAX_CLOCK_ENABLE_WAIT) pr_debug("Clock %s stable after %d loops\n", name, i); else printk(KERN_ERR "Clock %s didn't enable in %d tries\n", diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 73e2971b175..983f1cb676b 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); - if (c >= PWRDM_TRANSITION_BAILOUT) { + if (c > PWRDM_TRANSITION_BAILOUT) { printk(KERN_ERR "powerdomain: waited too long for " "powerdomain %s to complete transition\n", pwrdm->name); return -EAGAIN; -- cgit v1.2.3 From 7b768f07dce463a054c9dd84862d15ccc3d2b712 Mon Sep 17 00:00:00 2001 From: "Pallipadi, Venkatesh" Date: Fri, 19 Jun 2009 17:14:59 -0700 Subject: ACPI: pdc init related memory leak with physical CPU hotplug arch_acpi_processor_cleanup_pdc() in x86 and ia64 results in memory allocated for _PDC objects that is never freed and will cause memory leak in case of physical CPU remove and add. Patch fixes the memory leak by freeing the objects soon after _PDC is evaluated. Reported-by: Bjorn Helgaas Signed-off-by: Venkatesh Pallipadi Signed-off-by: Len Brown --- arch/ia64/kernel/acpi-processor.c | 12 ++++++++++++ arch/x86/kernel/acpi/processor.c | 13 +++++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/ia64/kernel/acpi-processor.c b/arch/ia64/kernel/acpi-processor.c index cbe6cee5a55..dbda7bde611 100644 --- a/arch/ia64/kernel/acpi-processor.c +++ b/arch/ia64/kernel/acpi-processor.c @@ -71,3 +71,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) } EXPORT_SYMBOL(arch_acpi_processor_init_pdc); + +void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr) +{ + if (pr->pdc) { + kfree(pr->pdc->pointer->buffer.pointer); + kfree(pr->pdc->pointer); + kfree(pr->pdc); + pr->pdc = NULL; + } +} + +EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc); diff --git a/arch/x86/kernel/acpi/processor.c b/arch/x86/kernel/acpi/processor.c index 7c074eec39f..d296f4a195c 100644 --- a/arch/x86/kernel/acpi/processor.c +++ b/arch/x86/kernel/acpi/processor.c @@ -72,6 +72,7 @@ static void init_intel_pdc(struct acpi_processor *pr, struct cpuinfo_x86 *c) return; } + /* Initialize _PDC data based on the CPU vendor */ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) { @@ -85,3 +86,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) } EXPORT_SYMBOL(arch_acpi_processor_init_pdc); + +void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr) +{ + if (pr->pdc) { + kfree(pr->pdc->pointer->buffer.pointer); + kfree(pr->pdc->pointer); + kfree(pr->pdc); + pr->pdc = NULL; + } +} + +EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc); -- cgit v1.2.3 From e01916e3e7834cb51327e5e4983ff76bfce8a91f Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 20 Jun 2009 22:25:45 +0100 Subject: [ARM] wire up rt_tgsigqueueinfo and perf_counter_open Signed-off-by: Russell King --- arch/arm/include/asm/unistd.h | 2 ++ arch/arm/kernel/calls.S | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 94cc58ef61a..0e97b8cb77d 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -389,6 +389,8 @@ #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) #define __NR_preadv (__NR_SYSCALL_BASE+361) #define __NR_pwritev (__NR_SYSCALL_BASE+362) +#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) +#define __NR_perf_counter_open (__NR_SYSCALL_BASE+364) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 1680e9e9c83..f776e72a4cb 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -372,6 +372,8 @@ /* 360 */ CALL(sys_inotify_init1) CALL(sys_preadv) CALL(sys_pwritev) + CALL(sys_rt_tgsigqueueinfo) + CALL(sys_perf_counter_open) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted -- cgit v1.2.3 From 3eadd3b21cec340dacdc24dd1f9735344290ca62 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 20 Jun 2009 22:28:41 +0100 Subject: [ARM] Update mach-types Signed-off-by: Russell King --- arch/arm/tools/mach-types | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index fec64678a63..33026eff2aa 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Fri May 29 10:14:20 2009 +# Last update: Sat Jun 20 22:28:39 2009 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1455,7 +1455,7 @@ gba MACH_GBA GBA 1457 h6044 MACH_H6044 H6044 1458 app MACH_APP APP 1459 tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 -herald MACH_HERMES HERMES 1461 +herald MACH_HERALD HERALD 1461 artemis MACH_ARTEMIS ARTEMIS 1462 htctitan MACH_HTCTITAN HTCTITAN 1463 qranium MACH_QRANIUM QRANIUM 1464 @@ -2245,3 +2245,38 @@ str9 MACH_STR9 STR9 2257 omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 simcom MACH_SIMCOM SIMCOM 2259 mcwebio MACH_MCWEBIO MCWEBIO 2260 +omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 +darwin MACH_DARWIN DARWIN 2262 +oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 +rtsbc20 MACH_RTSBC20 RTSBC20 2264 +i780 MACH_I780 I780 2265 +gemini324 MACH_GEMINI324 GEMINI324 2266 +oratislan MACH_ORATISLAN ORATISLAN 2267 +oratisalog MACH_ORATISALOG ORATISALOG 2268 +oratismadi MACH_ORATISMADI ORATISMADI 2269 +oratisot16 MACH_ORATISOT16 ORATISOT16 2270 +oratisdesk MACH_ORATISDESK ORATISDESK 2271 +v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272 +sintexo MACH_SINTEXO SINTEXO 2273 +cm3389 MACH_CM3389 CM3389 2274 +omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 +sgh_i900 MACH_SGH_I900 SGH_I900 2276 +bst100 MACH_BST100 BST100 2277 +passion MACH_PASSION PASSION 2278 +indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279 +c4_badger MACH_C4_BADGER C4_BADGER 2280 +c4_viper MACH_C4_VIPER C4_VIPER 2281 +d2net MACH_D2NET D2NET 2282 +bigdisk MACH_BIGDISK BIGDISK 2283 +notalvision MACH_NOTALVISION NOTALVISION 2284 +omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285 +cyclone MACH_CYCLONE CYCLONE 2286 +ninja MACH_NINJA NINJA 2287 +at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 +bcmring MACH_BCMRING BCMRING 2289 +resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290 +ifosw MACH_IFOSW IFOSW 2291 +htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 +htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 +matrix504 MACH_MATRIX504 MATRIX504 2294 +mrfsa MACH_MRFSA MRFSA 2295 -- cgit v1.2.3 From 99bd0c0fc4b04da54cb311953ef9489931c19c63 Mon Sep 17 00:00:00 2001 From: Andreas Herrmann Date: Fri, 19 Jun 2009 10:59:09 +0200 Subject: x86: Set cpu_llc_id on AMD CPUs This counts when building sched domains in case NUMA information is not available. ( See cpu_coregroup_mask() which uses llc_shared_map which in turn is created based on cpu_llc_id. ) Currently Linux builds domains as follows: (example from a dual socket quad-core system) CPU0 attaching sched-domain: domain 0: span 0-7 level CPU groups: 0 1 2 3 4 5 6 7 ... CPU7 attaching sched-domain: domain 0: span 0-7 level CPU groups: 7 0 1 2 3 4 5 6 Ever since that is borked for multi-core AMD CPU systems. This patch fixes that and now we get a proper: CPU0 attaching sched-domain: domain 0: span 0-3 level MC groups: 0 1 2 3 domain 1: span 0-7 level CPU groups: 0-3 4-7 ... CPU7 attaching sched-domain: domain 0: span 4-7 level MC groups: 7 4 5 6 domain 1: span 0-7 level CPU groups: 4-7 0-3 This allows scheduler to assign tasks to cores on different sockets (i.e. that don't share last level cache) for performance reasons. Signed-off-by: Andreas Herrmann LKML-Reference: <20090619085909.GJ5218@alberich.amd.com> Cc: Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/amd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e5b27d8f1b4..28e5f595604 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -258,13 +258,15 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_HT unsigned bits; + int cpu = smp_processor_id(); bits = c->x86_coreid_bits; - /* Low order bits define the core id (index of core in socket) */ c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ c->phys_proc_id = c->initial_apicid >> bits; + /* use socket ID also for last level cache */ + per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; #endif } -- cgit v1.2.3 From d9f2a5ecb2846d0fd368fb4c45182e43f38e4471 Mon Sep 17 00:00:00 2001 From: Jaswinder Singh Rajput Date: Sat, 20 Jun 2009 13:19:25 +0530 Subject: perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD Fix AMD's Data Cache Refills from System event. After this patch : ./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null Performance counter stats for 'ls /dev/': 2499484 L1-data-Cache-Load-Referencees (scaled from 3.97%) 70347 L1-data-Cache-Load-Misses (scaled from 7.30%) 9360 L1-data-Cache-Store-Referencees (scaled from 8.64%) 32804 L1-data-Cache-Prefetch-Referencees (scaled from 17.72%) 7693 L1-data-Cache-Prefetch-Misses (scaled from 22.97%) 2180945 L1-instruction-Cache-Load-Referencees (scaled from 28.48%) 14518 L1-instruction-Cache-Load-Misses (scaled from 35.00%) 2405 L1-instruction-Cache-Prefetch-Referencees (scaled from 34.89%) 71387 L2-Cache-Load-Referencees (scaled from 34.94%) 18732 L2-Cache-Load-Misses (scaled from 34.92%) 79918 L2-Cache-Store-Referencees (scaled from 36.02%) 1295294 Data-TLB-Cache-Load-Referencees (scaled from 35.99%) 30896 Data-TLB-Cache-Load-Misses (scaled from 33.36%) 1222030 Instruction-TLB-Cache-Load-Referencees (scaled from 29.46%) 357 Instruction-TLB-Cache-Load-Misses (scaled from 20.46%) 530888 Branch-Cache-Load-Referencees (scaled from 11.48%) 8638 Branch-Cache-Load-Misses (scaled from 5.09%) 0.011295149 seconds time elapsed. Earlier it always shows value 0. Signed-off-by: Jaswinder Singh Rajput LKML-Reference: <1245484165.3102.6.camel@localhost.localdomain> Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_counter.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 76dfef23f78..22eb3a1d4f9 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ + [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { -- cgit v1.2.3 From bd974240c9a7c6c560504bf390cd8985a16b68f6 Mon Sep 17 00:00:00 2001 From: Oskar Schirmer Date: Wed, 10 Jun 2009 12:58:45 -0700 Subject: xtensa: cache inquiry and unaligned cache handling functions The existing xtensa cache handling functions work on page-aligned memory regions. These functions are needed for the s6000 dma engine which can work on a byte-granularity. Signed-off-by: Oskar Schirmer Cc: Johannes Weiner Cc: Daniel Glockner Signed-off-by: Andrew Morton Signed-off-by: Chris Zankel --- arch/xtensa/include/asm/cacheflush.h | 95 ++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'arch') diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h index 8fc1c0c8de0..b7b8fbe47c7 100644 --- a/arch/xtensa/include/asm/cacheflush.h +++ b/arch/xtensa/include/asm/cacheflush.h @@ -155,5 +155,100 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*, #endif +#define XTENSA_CACHEBLK_LOG2 29 +#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2) +#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2) + +#if XCHAL_HAVE_CACHEATTR +static inline u32 xtensa_get_cacheattr(void) +{ + u32 r; + asm volatile(" rsr %0, CACHEATTR" : "=a"(r)); + return r; +} + +static inline u32 xtensa_get_dtlb1(u32 addr) +{ + u32 r = addr & XTENSA_CACHEBLK_MASK; + return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2))) + & 0xF); +} +#else +static inline u32 xtensa_get_dtlb1(u32 addr) +{ + u32 r; + asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr)); + asm volatile(" dsync"); + return r; +} + +static inline u32 xtensa_get_cacheattr(void) +{ + u32 r = 0; + u32 a = 0; + do { + a -= XTENSA_CACHEBLK_SIZE; + r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF); + } while (a); + return r; +} +#endif + +static inline int xtensa_need_flush_dma_source(u32 addr) +{ + return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4; +} + +static inline int xtensa_need_invalidate_dma_destination(u32 addr) +{ + return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2; +} + +static inline void flush_dcache_unaligned(u32 addr, u32 size) +{ + u32 cnt; + if (size) { + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt--) { + asm volatile(" dhwb %0, 0" : : "a"(addr)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dsync"); + } +} + +static inline void invalidate_dcache_unaligned(u32 addr, u32 size) +{ + int cnt; + if (size) { + asm volatile(" dhwbi %0, 0 ;" : : "a"(addr)); + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + - XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt-- > 0) { + asm volatile(" dhi %0, %1" : : "a"(addr), + "n"(XCHAL_DCACHE_LINESIZE)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dhwbi %0, %1" : : "a"(addr), + "n"(XCHAL_DCACHE_LINESIZE)); + asm volatile(" dsync"); + } +} + +static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size) +{ + u32 cnt; + if (size) { + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt--) { + asm volatile(" dhwbi %0, 0" : : "a"(addr)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dsync"); + } +} + #endif /* __KERNEL__ */ #endif /* _XTENSA_CACHEFLUSH_H */ -- cgit v1.2.3 From 1beee21030ed3dc39a41c7b524dbc1a318b518bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Gl=C3=B6ckner?= Date: Tue, 5 May 2009 15:03:21 +0000 Subject: xtensa: allow variant to initialize own irq chips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There was already a PLATFORM_NR_IRQS define, which is now accompanied by a VARIANT_NR_IRQS. To be able to initialize these interrupts, init_IRQ now calls a variant specific hook. Changes compared to v1: - adapted to new CONFIG_VARIANT_IRQ_EXT - removed definition and call of platform_init_IRQ as there already is a platform_init_irq defined in asm/platform.h with a weak default in kernel/platform.c - renamed variant_init_IRQ to variant_init_irq Note that I could not find the call site of platform_init_irq although it is stated in platform.h that it is called from init_IRQ. Signed-off-by: Daniel Glöckner Signed-off-by: Chris Zankel --- arch/xtensa/include/asm/irq.h | 12 +++++++++++- arch/xtensa/kernel/irq.c | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h index dfac82dc52a..4c0ccc9c4f4 100644 --- a/arch/xtensa/include/asm/irq.h +++ b/arch/xtensa/include/asm/irq.h @@ -11,6 +11,7 @@ #ifndef _XTENSA_IRQ_H #define _XTENSA_IRQ_H +#include #include #include @@ -21,11 +22,20 @@ static inline void variant_irq_enable(unsigned int irq) { } static inline void variant_irq_disable(unsigned int irq) { } #endif +#ifndef VARIANT_NR_IRQS +# define VARIANT_NR_IRQS 0 +#endif #ifndef PLATFORM_NR_IRQS # define PLATFORM_NR_IRQS 0 #endif #define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS -#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS) +#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS) + +#if VARIANT_NR_IRQS == 0 +static inline void variant_init_irq(void) { } +#else +void variant_init_irq(void) __init; +#endif static __inline__ int irq_canonicalize(int irq) { diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index a36c85edd04..a1badb32fcd 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -197,4 +197,6 @@ void __init init_IRQ(void) } cached_irq_mask = 0; + + variant_init_irq(); } -- cgit v1.2.3 From f24e552c2dc3221dc7bd2296fd8a705283c4b2d7 Mon Sep 17 00:00:00 2001 From: Oskar Schirmer Date: Wed, 10 Jun 2009 12:58:45 -0700 Subject: xtensa: s6000 dma engine support There are four slightly different dma engines on the s6000 family. One for memory-memory transfers, the other three for memory-device. This patch implements a platform-specific kernel-API to control these engines. It is needed for the network, video, audio peripherals on s6000. Signed-off-by: Oskar Schirmer Signed-off-by: Daniel Glockner Signed-off-by: Fabian Godehardt Cc: Daniel Glockner Signed-off-by: Andrew Morton Signed-off-by: Chris Zankel --- arch/xtensa/variants/s6000/Makefile | 2 +- arch/xtensa/variants/s6000/dmac.c | 173 ++++++++++ arch/xtensa/variants/s6000/include/variant/dmac.h | 387 ++++++++++++++++++++++ 3 files changed, 561 insertions(+), 1 deletion(-) create mode 100644 arch/xtensa/variants/s6000/dmac.c create mode 100644 arch/xtensa/variants/s6000/include/variant/dmac.h (limited to 'arch') diff --git a/arch/xtensa/variants/s6000/Makefile b/arch/xtensa/variants/s6000/Makefile index d83f3805130..3e7ef0a0c49 100644 --- a/arch/xtensa/variants/s6000/Makefile +++ b/arch/xtensa/variants/s6000/Makefile @@ -1,4 +1,4 @@ # s6000 Makefile -obj-y += irq.o gpio.o +obj-y += irq.o gpio.o dmac.o obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o diff --git a/arch/xtensa/variants/s6000/dmac.c b/arch/xtensa/variants/s6000/dmac.c new file mode 100644 index 00000000000..dc7f7c57351 --- /dev/null +++ b/arch/xtensa/variants/s6000/dmac.c @@ -0,0 +1,173 @@ +/* + * Authors: Oskar Schirmer + * Daniel Gloeckner + * (c) 2008 emlix GmbH http://www.emlix.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* DMA engine lookup */ + +struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB]; + + +/* DMA control, per engine */ + +void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size) +{ + if (xtensa_need_flush_dma_source(src)) { + u32 base = src; + u32 span = size; + u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + if (chunk && (size > chunk)) { + s32 skip = + readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); + u32 gaps = (size+chunk-1)/chunk - 1; + if (skip >= 0) { + span += gaps * skip; + } else if (-skip > chunk) { + s32 decr = gaps * (chunk + skip); + base += decr; + span = chunk - decr; + } else { + span = max(span + gaps * skip, + (chunk + skip) * gaps - skip); + } + } + flush_dcache_unaligned(base, span); + } + if (xtensa_need_invalidate_dma_destination(dst)) { + u32 base = dst; + u32 span = size; + u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + if (chunk && (size > chunk)) { + s32 skip = + readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); + u32 gaps = (size+chunk-1)/chunk - 1; + if (skip >= 0) { + span += gaps * skip; + } else if (-skip > chunk) { + s32 decr = gaps * (chunk + skip); + base += decr; + span = chunk - decr; + } else { + span = max(span + gaps * skip, + (chunk + skip) * gaps - skip); + } + } + invalidate_dcache_unaligned(base, span); + } + s6dmac_put_fifo(dmac, chan, src, dst, size); +} + +void s6dmac_disable_error_irqs(u32 dmac, u32 mask) +{ + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + _s6dmac_disable_error_irqs(dmac, mask); + spin_unlock_irqrestore(spinl, flags); +} + +u32 s6dmac_int_sources(u32 dmac, u32 channel) +{ + u32 mask, ret, tmp; + mask = 1 << channel; + + tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR); + ret = tmp >> channel; + + tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR); + ret |= (tmp >> channel) << 1; + + tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR); + ret |= (tmp >> channel) << 2; + + tmp = readl(dmac + S6_DMA_INTRAW0); + tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER); + writel(tmp, dmac + S6_DMA_INTCLEAR0); + + if (tmp & (mask << S6_DMA_INT0_UNDER)) + ret |= 1 << 3; + if (tmp & (mask << S6_DMA_INT0_OVER)) + ret |= 1 << 4; + + tmp = readl(dmac + S6_DMA_MASTERERRINFO); + mask <<= S6_DMA_INT1_CHANNEL; + if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << S6_DMA_INT1_MASTER; + if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << (S6_DMA_INT1_MASTER + 1); + if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << (S6_DMA_INT1_MASTER + 2); + + tmp = readl(dmac + S6_DMA_INTRAW1) & mask; + writel(tmp, dmac + S6_DMA_INTCLEAR1); + ret |= ((tmp >> channel) & 1) << 5; + ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6; + + return ret; +} + +void s6dmac_release_chan(u32 dmac, int chan) +{ + if (chan >= 0) + s6dmac_disable_chan(dmac, chan); +} + + +/* global init */ + +static inline void __init dmac_init(u32 dmac, u8 chan_nb) +{ + s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac; + spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock); + s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb; + writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER, + dmac + S6_DMA_INTCLEAR1); +} + +static inline void __init dmac_master(u32 dmac, + u32 m0start, u32 m0end, u32 m1start, u32 m1end) +{ + writel(m0start, dmac + S6_DMA_MASTER0START); + writel(m0end - 1, dmac + S6_DMA_MASTER0END); + writel(m1start, dmac + S6_DMA_MASTER1START); + writel(m1end - 1, dmac + S6_DMA_MASTER1END); +} + +static void __init s6_dmac_init(void) +{ + dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB); + dmac_master(S6_REG_LMSDMA, + S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC); + dmac_init(S6_REG_NIDMA, S6_NIDMA_NB); + dmac_init(S6_REG_DPDMA, S6_DPDMA_NB); + dmac_master(S6_REG_DPDMA, + S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA); + dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB); + dmac_master(S6_REG_HIFDMA, + S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX); +} + +arch_initcall(s6_dmac_init); diff --git a/arch/xtensa/variants/s6000/include/variant/dmac.h b/arch/xtensa/variants/s6000/include/variant/dmac.h new file mode 100644 index 00000000000..89ab9484fb7 --- /dev/null +++ b/arch/xtensa/variants/s6000/include/variant/dmac.h @@ -0,0 +1,387 @@ +/* + * include/asm-xtensa/variant-s6000/dmac.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Tensilica Inc. + * Copyright (C) 2008 Emlix GmbH + * Authors: Fabian Godehardt + * Oskar Schirmer + * Daniel Gloeckner + */ + +#ifndef __ASM_XTENSA_S6000_DMAC_H +#define __ASM_XTENSA_S6000_DMAC_H +#include +#include + +/* DMA global */ + +#define S6_DMA_INTSTAT0 0x000 +#define S6_DMA_INTSTAT1 0x004 +#define S6_DMA_INTENABLE0 0x008 +#define S6_DMA_INTENABLE1 0x00C +#define S6_DMA_INTRAW0 0x010 +#define S6_DMA_INTRAW1 0x014 +#define S6_DMA_INTCLEAR0 0x018 +#define S6_DMA_INTCLEAR1 0x01C +#define S6_DMA_INTSET0 0x020 +#define S6_DMA_INTSET1 0x024 +#define S6_DMA_INT0_UNDER 0 +#define S6_DMA_INT0_OVER 16 +#define S6_DMA_INT1_CHANNEL 0 +#define S6_DMA_INT1_MASTER 16 +#define S6_DMA_INT1_MASTER_MASK 7 +#define S6_DMA_TERMCNTIRQSTAT 0x028 +#define S6_DMA_TERMCNTIRQCLR 0x02C +#define S6_DMA_TERMCNTIRQSET 0x030 +#define S6_DMA_PENDCNTIRQSTAT 0x034 +#define S6_DMA_PENDCNTIRQCLR 0x038 +#define S6_DMA_PENDCNTIRQSET 0x03C +#define S6_DMA_LOWWMRKIRQSTAT 0x040 +#define S6_DMA_LOWWMRKIRQCLR 0x044 +#define S6_DMA_LOWWMRKIRQSET 0x048 +#define S6_DMA_MASTERERRINFO 0x04C +#define S6_DMA_MASTERERR_CHAN(n) (4*(n)) +#define S6_DMA_MASTERERR_CHAN_MASK 0xF +#define S6_DMA_DESCRFIFO0 0x050 +#define S6_DMA_DESCRFIFO1 0x054 +#define S6_DMA_DESCRFIFO2 0x058 +#define S6_DMA_DESCRFIFO2_AUTODISABLE 24 +#define S6_DMA_DESCRFIFO3 0x05C +#define S6_DMA_MASTER0START 0x060 +#define S6_DMA_MASTER0END 0x064 +#define S6_DMA_MASTER1START 0x068 +#define S6_DMA_MASTER1END 0x06C +#define S6_DMA_NEXTFREE 0x070 +#define S6_DMA_NEXTFREE_CHAN 0 +#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F +#define S6_DMA_NEXTFREE_ENA 16 +#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1) +#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074) +#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0 +#define S6_DMA_DPORTCTRLGRP_NRCHANS 1 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3 +#define S6_DMA_DPORTCTRLGRP_ENA 31 + + +/* DMA per channel */ + +#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100) +#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF) +#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000) +#define S6_DMA_CHNCTRL 0x000 +#define S6_DMA_CHNCTRL_ENABLE 0 +#define S6_DMA_CHNCTRL_PAUSE 1 +#define S6_DMA_CHNCTRL_PRIO 2 +#define S6_DMA_CHNCTRL_PRIO_MASK 3 +#define S6_DMA_CHNCTRL_PERIPHXFER 4 +#define S6_DMA_CHNCTRL_PERIPHENA 5 +#define S6_DMA_CHNCTRL_SRCINC 6 +#define S6_DMA_CHNCTRL_DSTINC 7 +#define S6_DMA_CHNCTRL_BURSTLOG 8 +#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7 +#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12 +#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F +#define S6_DMA_CHNCTRL_DESCFIFOFULL 17 +#define S6_DMA_CHNCTRL_BWCONSEL 18 +#define S6_DMA_CHNCTRL_BWCONENA 19 +#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20 +#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F +#define S6_DMA_CHNCTRL_LOWWMARK 26 +#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF +#define S6_DMA_CHNCTRL_TSTAMP 30 +#define S6_DMA_TERMCNTNB 0x004 +#define S6_DMA_TERMCNTNB_MASK 0xFFFF +#define S6_DMA_TERMCNTTMO 0x008 +#define S6_DMA_TERMCNTSTAT 0x00C +#define S6_DMA_TERMCNTSTAT_MASK 0xFF +#define S6_DMA_CMONCHUNK 0x010 +#define S6_DMA_SRCSKIP 0x014 +#define S6_DMA_DSTSKIP 0x018 +#define S6_DMA_CUR_SRC 0x024 +#define S6_DMA_CUR_DST 0x028 +#define S6_DMA_TIMESTAMP 0x030 + +/* DMA channel lists */ + +#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel)) +#define S6_DPDMA_NB 16 + +#define S6_HIFDMA_GMACTX 0 +#define S6_HIFDMA_GMACRX 1 +#define S6_HIFDMA_I2S0 2 +#define S6_HIFDMA_I2S1 3 +#define S6_HIFDMA_EGIB 4 +#define S6_HIFDMA_PCITX 5 +#define S6_HIFDMA_PCIRX 6 +#define S6_HIFDMA_NB 7 + +#define S6_NIDMA_NB 4 + +#define S6_LMSDMA_NB 12 + +/* controller access */ + +#define S6_DMAC_NB 4 +#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB) + +struct s6dmac_ctrl { + u32 dmac; + spinlock_t lock; + u8 chan_nb; +}; + +extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB]; + + +/* DMA control, per channel */ + +static inline int s6dmac_fifo_full(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + & (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1; +} + +static inline int s6dmac_termcnt_irq(u32 dmac, int chan) +{ + u32 m = 1 << chan; + int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1; + if (r) + writel(m, dmac + S6_DMA_TERMCNTIRQCLR); + return r; +} + +static inline int s6dmac_pendcnt_irq(u32 dmac, int chan) +{ + u32 m = 1 << chan; + int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1; + if (r) + writel(m, dmac + S6_DMA_PENDCNTIRQCLR); + return r; +} + +static inline int s6dmac_lowwmark_irq(u32 dmac, int chan) +{ + int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0; + if (r) + writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR); + return r; +} + +static inline u32 s6dmac_pending_count(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + >> S6_DMA_CHNCTRL_PENDGCNTSTAT) + & S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK; +} + +static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n) +{ + n &= S6_DMA_TERMCNTNB_MASK; + n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB) + & ~S6_DMA_TERMCNTNB_MASK; + writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); +} + +static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)) + & S6_DMA_TERMCNTNB_MASK; +} + +static inline u32 s6dmac_timestamp(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP); +} + +static inline u32 s6dmac_cur_src(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC); +} + +static inline u32 s6dmac_cur_dst(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST); +} + +static inline void s6dmac_disable_chan(u32 dmac, int chan) +{ + u32 ctrl; + writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + & ~(1 << S6_DMA_CHNCTRL_ENABLE), + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + do + ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE)); +} + +static inline void s6dmac_set_stride_skip(u32 dmac, int chan, + int comchunk, /* 0: disable scatter/gather */ + int srcskip, int dstskip) +{ + writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); + writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); +} + +static inline void s6dmac_enable_chan(u32 dmac, int chan, + int prio, /* 0 (highest) .. 3 (lowest) */ + int periphxfer, /* <0: disable p.req.line, 0..1: mode */ + int srcinc, int dstinc, /* 0: dont increment src/dst address */ + int comchunk, /* 0: disable scatter/gather */ + int srcskip, int dstskip, + int burstsize, /* 4 for I2S, 7 for everything else */ + int bandwidthconserve, /* <0: disable, 0..1: select */ + int lowwmark, /* 0..15 */ + int timestamp, /* 0: disable timestamp */ + int enable) /* 0: disable for now */ +{ + writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); + writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO); + writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK, + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip); + writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) | + (prio << S6_DMA_CHNCTRL_PRIO) | + (((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) | + (((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) | + ((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) | + ((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) | + (burstsize << S6_DMA_CHNCTRL_BURSTLOG) | + (((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) | + (((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) | + (lowwmark << S6_DMA_CHNCTRL_LOWWMARK) | + ((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP), + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); +} + + +/* DMA control, per engine */ + +static inline unsigned _dmac_addr_index(u32 dmac) +{ + unsigned i = S6_DMAC_INDEX(dmac); + if (s6dmac_ctrl[i].dmac != dmac) + BUG(); + return i; +} + +static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask) +{ + writel(mask, dmac + S6_DMA_TERMCNTIRQCLR); + writel(mask, dmac + S6_DMA_PENDCNTIRQCLR); + writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR); + writel(readl(dmac + S6_DMA_INTENABLE0) + & ~((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER)), + dmac + S6_DMA_INTENABLE0); + writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL), + dmac + S6_DMA_INTENABLE1); + writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER), + dmac + S6_DMA_INTCLEAR0); + writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1); +} + +/* + * request channel from specified engine + * with chan<0, accept any channel + * further parameters see s6dmac_enable_chan + * returns < 0 upon error, channel nb otherwise + */ +static inline int s6dmac_request_chan(u32 dmac, int chan, + int prio, + int periphxfer, + int srcinc, int dstinc, + int comchunk, + int srcskip, int dstskip, + int burstsize, + int bandwidthconserve, + int lowwmark, + int timestamp, + int enable) +{ + int r = chan; + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + if (r < 0) { + r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN) + & S6_DMA_NEXTFREE_CHAN_MASK; + } + if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) { + if (chan < 0) + r = -EBUSY; + else + r = -ENXIO; + } else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA) + >> r) & 1) { + r = -EBUSY; + } else { + s6dmac_enable_chan(dmac, r, prio, periphxfer, + srcinc, dstinc, comchunk, srcskip, dstskip, burstsize, + bandwidthconserve, lowwmark, timestamp, enable); + } + spin_unlock_irqrestore(spinl, flags); + return r; +} + +static inline void s6dmac_put_fifo(u32 dmac, int chan, + u32 src, u32 dst, u32 size) +{ + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + writel(src, dmac + S6_DMA_DESCRFIFO0); + writel(dst, dmac + S6_DMA_DESCRFIFO1); + writel(size, dmac + S6_DMA_DESCRFIFO2); + writel(chan, dmac + S6_DMA_DESCRFIFO3); + spin_unlock_irqrestore(spinl, flags); +} + +static inline u32 s6dmac_channel_enabled(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) & + (1 << S6_DMA_CHNCTRL_ENABLE); +} + +/* + * group 1-4 data port channels + * with port=0..3, nrch=1-4 channels, + * frrep=0/1 (dis- or enable frame repeat) + */ +static inline void s6dmac_dp_setup_group(u32 dmac, int port, + int nrch, int frrep) +{ + const static u8 mask[4] = {0, 3, 1, 2}; + BUG_ON(dmac != S6_REG_DPDMA); + if ((port < 0) || (port > 3) || (nrch < 1) || (nrch > 4)) + return; + writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS) + | ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP), + dmac + S6_DMA_DPORTCTRLGRP(port)); +} + +static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable) +{ + u32 tmp; + BUG_ON(dmac != S6_REG_DPDMA); + tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port)); + if (enable) + tmp |= (1 << S6_DMA_DPORTCTRLGRP_ENA); + else + tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA); + writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port)); +} + +extern void s6dmac_put_fifo_cache(u32 dmac, int chan, + u32 src, u32 dst, u32 size); +extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask); +extern u32 s6dmac_int_sources(u32 dmac, u32 channel); +extern void s6dmac_release_chan(u32 dmac, int chan); + +#endif /* __ASM_XTENSA_S6000_DMAC_H */ -- cgit v1.2.3 From 0b3eb21b2f2222c4c1e3e21fc3cd427404d3991a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Gl=C3=B6ckner?= Date: Tue, 5 May 2009 15:03:22 +0000 Subject: xtensa: support s6000 gpio irqs and alternate function selection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement an irq chip to handle interrupts via gpio. The GPIO chip initialization function now takes a bitmask denoting pins that should be configured for their alternate function. changes compared to v1: - fixed bug on edge interrupt configuration - accommodated to function name change - moved definition of VARIANT_NR_IRQS to this patch - renamed __XTENSA_S6000_IRQ_H to _XTENSA_S6000_IRQ_H as requested Signed-off-by: Daniel Glöckner Signed-off-by: Johannes Weiner Signed-off-by: Chris Zankel --- arch/xtensa/include/asm/gpio.h | 8 +- arch/xtensa/platforms/s6105/setup.c | 2 +- arch/xtensa/variants/s6000/gpio.c | 163 +++++++++++++++++++++- arch/xtensa/variants/s6000/include/variant/gpio.h | 2 +- arch/xtensa/variants/s6000/include/variant/irq.h | 6 +- 5 files changed, 171 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h index 0763b076396..a8c9fc46c79 100644 --- a/arch/xtensa/include/asm/gpio.h +++ b/arch/xtensa/include/asm/gpio.h @@ -38,14 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio) return __gpio_cansleep(gpio); } -/* - * Not implemented, yet. - */ static inline int gpio_to_irq(unsigned int gpio) { - return -ENOSYS; + return __gpio_to_irq(gpio); } +/* + * Not implemented, yet. + */ static inline int irq_to_gpio(unsigned int irq) { return -EINVAL; diff --git a/arch/xtensa/platforms/s6105/setup.c b/arch/xtensa/platforms/s6105/setup.c index 855ddeadc43..95fa23c8e63 100644 --- a/arch/xtensa/platforms/s6105/setup.c +++ b/arch/xtensa/platforms/s6105/setup.c @@ -49,7 +49,7 @@ void __init platform_setup(char **cmdline) void __init platform_init(bp_tag_t *first) { - s6_gpio_init(); + s6_gpio_init(0); gpio_request(GPIO_LED1_NGREEN, "led1_green"); gpio_request(GPIO_LED1_RED, "led1_red"); gpio_direction_output(GPIO_LED1_NGREEN, 1); diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c index 79317fdcf14..380a70fff75 100644 --- a/arch/xtensa/variants/s6000/gpio.c +++ b/arch/xtensa/variants/s6000/gpio.c @@ -4,15 +4,20 @@ * Copyright (c) 2009 emlix GmbH * Authors: Oskar Schirmer * Johannes Weiner + * Daniel Gloeckner */ +#include #include #include #include #include +#include #include #include +#define IRQ_BASE XTENSA_NR_IRQS + #define S6_GPIO_DATA 0x000 #define S6_GPIO_IS 0x404 #define S6_GPIO_IBE 0x408 @@ -52,19 +57,175 @@ static void set(struct gpio_chip *chip, unsigned int off, int val) writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off)); } +static int to_irq(struct gpio_chip *chip, unsigned offset) +{ + if (offset < 8) + return offset + IRQ_BASE; + return -EINVAL; +} + static struct gpio_chip gpiochip = { .owner = THIS_MODULE, .direction_input = direction_input, .get = get, .direction_output = direction_output, .set = set, + .to_irq = to_irq, .base = 0, .ngpio = 24, .can_sleep = 0, /* no blocking io needed */ .exported = 0, /* no exporting to userspace */ }; -int s6_gpio_init(void) +int s6_gpio_init(u32 afsel) { + writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL); + writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL); + writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL); return gpiochip_add(&gpiochip); } + +static void ack(unsigned int irq) +{ + writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); +} + +static void mask(unsigned int irq) +{ + u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); + r &= ~(1 << (irq - IRQ_BASE)); + writeb(r, S6_REG_GPIO + S6_GPIO_IE); +} + +static void unmask(unsigned int irq) +{ + u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); + m |= 1 << (irq - IRQ_BASE); + writeb(m, S6_REG_GPIO + S6_GPIO_IE); +} + +static int set_type(unsigned int irq, unsigned int type) +{ + const u8 m = 1 << (irq - IRQ_BASE); + irq_flow_handler_t handler; + struct irq_desc *desc; + u8 reg; + + if (type == IRQ_TYPE_PROBE) { + if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m) + || (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m) + || readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR + + S6_GPIO_MASK(irq - IRQ_BASE))) + return 0; + type = IRQ_TYPE_EDGE_BOTH; + } + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { + reg |= m; + handler = handle_level_irq; + } else { + reg &= ~m; + handler = handle_edge_irq; + } + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); + desc = irq_to_desc(irq); + desc->handle_irq = handler; + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); + if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) + reg |= m; + else + reg &= ~m; + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE); + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + reg |= m; + else + reg &= ~m; + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE); + return 0; +} + +static struct irq_chip gpioirqs = { + .name = "GPIO", + .ack = ack, + .mask = mask, + .unmask = unmask, + .set_type = set_type, +}; + +static u8 demux_masks[4]; + +static void demux_irqs(unsigned int irq, struct irq_desc *desc) +{ + u8 *mask = get_irq_desc_data(desc); + u8 pending; + int cirq; + + desc->chip->mask(irq); + desc->chip->ack(irq); + pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; + cirq = IRQ_BASE - 1; + while (pending) { + int n = ffs(pending); + cirq += n; + pending >>= n; + generic_handle_irq(cirq); + } + desc->chip->unmask(irq); +} + +extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; + +void __init variant_init_irq(void) +{ + int irq, n; + writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE); + for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) { + const signed char *mapping = platform_irq_mappings[irq]; + int alone = 1; + u8 mask; + if (!mapping) + continue; + for(mask = 0; *mapping != -1; mapping++) + switch (*mapping) { + case S6_INTC_GPIO(0): + mask |= 1 << 0; + break; + case S6_INTC_GPIO(1): + mask |= 1 << 1; + break; + case S6_INTC_GPIO(2): + mask |= 1 << 2; + break; + case S6_INTC_GPIO(3): + mask |= 0x1f << 3; + break; + default: + alone = 0; + } + if (mask) { + int cirq, i; + if (!alone) { + printk(KERN_ERR "chained irq chips can't share" + " parent irq %i\n", irq); + continue; + } + demux_masks[n] = mask; + cirq = IRQ_BASE - 1; + do { + i = ffs(mask); + cirq += i; + mask >>= i; + set_irq_chip(cirq, &gpioirqs); + set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); + } while (mask); + set_irq_data(irq, demux_masks + n); + set_irq_chained_handler(irq, demux_irqs); + if (++n == ARRAY_SIZE(demux_masks)) + break; + } + } +} diff --git a/arch/xtensa/variants/s6000/include/variant/gpio.h b/arch/xtensa/variants/s6000/include/variant/gpio.h index 8327f62167e..8484ab0df46 100644 --- a/arch/xtensa/variants/s6000/include/variant/gpio.h +++ b/arch/xtensa/variants/s6000/include/variant/gpio.h @@ -1,6 +1,6 @@ #ifndef _XTENSA_VARIANT_S6000_GPIO_H #define _XTENSA_VARIANT_S6000_GPIO_H -extern int s6_gpio_init(void); +extern int s6_gpio_init(u32 afsel); #endif /* _XTENSA_VARIANT_S6000_GPIO_H */ diff --git a/arch/xtensa/variants/s6000/include/variant/irq.h b/arch/xtensa/variants/s6000/include/variant/irq.h index fa031cb0acc..97d6fc48def 100644 --- a/arch/xtensa/variants/s6000/include/variant/irq.h +++ b/arch/xtensa/variants/s6000/include/variant/irq.h @@ -1,9 +1,9 @@ -#ifndef __XTENSA_S6000_IRQ_H -#define __XTENSA_S6000_IRQ_H +#ifndef _XTENSA_S6000_IRQ_H +#define _XTENSA_S6000_IRQ_H #define NO_IRQ (-1) +#define VARIANT_NR_IRQS 8 /* GPIO interrupts */ extern void variant_irq_enable(unsigned int irq); -extern void variant_irq_disable(unsigned int irq); #endif /* __XTENSA_S6000_IRQ_H */ -- cgit v1.2.3 From 059cafe6df5d3b078c4b1be42623c62ab32de6fd Mon Sep 17 00:00:00 2001 From: Oskar Schirmer Date: Wed, 10 Jun 2009 12:58:48 -0700 Subject: xtensa: s6105 specific configuration for s6gmac Platform-specific configuration for the s6gmac driver, including the PHY interrupt line. Signed-off-by: Daniel Glockner Signed-off-by: Oskar Schirmer Cc: "David S. Miller" Cc: Johannes Weiner Signed-off-by: Andrew Morton --- arch/xtensa/platforms/s6105/device.c | 91 ++++++++++++++++++++++++++++++++++++ arch/xtensa/platforms/s6105/setup.c | 9 ++++ 2 files changed, 100 insertions(+) (limited to 'arch') diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c index 78b08be5a92..963634a3463 100644 --- a/arch/xtensa/platforms/s6105/device.c +++ b/arch/xtensa/platforms/s6105/device.c @@ -5,14 +5,27 @@ */ #include +#include #include +#include +#include #include #include #include #include +#include +#include + +#define GPIO3_INTNUM 3 #define UART_INTNUM 4 +#define GMAC_INTNUM 5 + +static const signed char gpio3_irq_mappings[] = { + S6_INTC_GPIO(3), + -1 +}; static const signed char uart_irq_mappings[] = { S6_INTC_UART(0), @@ -20,8 +33,18 @@ static const signed char uart_irq_mappings[] = { -1, }; +static const signed char gmac_irq_mappings[] = { + S6_INTC_GMAC_STAT, + S6_INTC_GMAC_ERR, + S6_INTC_DMA_HOSTTERMCNT(0), + S6_INTC_DMA_HOSTTERMCNT(1), + -1 +}; + const signed char *platform_irq_mappings[NR_IRQS] = { + [GPIO3_INTNUM] = gpio3_irq_mappings, [UART_INTNUM] = uart_irq_mappings, + [GMAC_INTNUM] = gmac_irq_mappings, }; static struct plat_serial8250_port serial_platform_data[] = { @@ -46,6 +69,66 @@ static struct plat_serial8250_port serial_platform_data[] = { { }, }; +static struct resource s6_gmac_resource[] = { + { + .name = "mem", + .start = (resource_size_t)S6_REG_GMAC, + .end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX), + .end = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma", + .start = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX), + .end = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1, + .flags = IORESOURCE_DMA, + }, + { + .name = "io", + .start = (resource_size_t)S6_MEM_GMAC, + .end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "irq", + .start = (resource_size_t)GMAC_INTNUM, + .flags = IORESOURCE_IRQ, + }, + { + .name = "irq", + .start = (resource_size_t)PHY_POLL, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init prepare_phy_irq(int pin) +{ + int irq; + if (gpio_request(pin, "s6gmac_phy") < 0) + goto fail; + if (gpio_direction_input(pin) < 0) + goto free; + irq = gpio_to_irq(pin); + if (irq < 0) + goto free; + if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) + goto free; + return irq; +free: + gpio_free(pin); +fail: + return PHY_POLL; +} + static struct platform_device platform_devices[] = { { .name = "serial8250", @@ -54,12 +137,20 @@ static struct platform_device platform_devices[] = { .platform_data = serial_platform_data, }, }, + { + .name = "s6gmac", + .id = 0, + .resource = s6_gmac_resource, + .num_resources = ARRAY_SIZE(s6_gmac_resource), + }, }; static int __init device_init(void) { int i; + s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ); + for (i = 0; i < ARRAY_SIZE(platform_devices); i++) platform_device_register(&platform_devices[i]); return 0; diff --git a/arch/xtensa/platforms/s6105/setup.c b/arch/xtensa/platforms/s6105/setup.c index 95fa23c8e63..86ce730f791 100644 --- a/arch/xtensa/platforms/s6105/setup.c +++ b/arch/xtensa/platforms/s6105/setup.c @@ -35,12 +35,21 @@ void __init platform_setup(char **cmdline) { unsigned long reg; + reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL); + reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC | + S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII); + reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC | + S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII; + writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL); + reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE); reg &= ~(1 << S6_GREG1_BLOCK_SB); + reg &= ~(1 << S6_GREG1_BLOCK_GMAC); writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE); reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA); reg |= 1 << S6_GREG1_BLOCK_SB; + reg |= 1 << S6_GREG1_BLOCK_GMAC; writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA); printk(KERN_NOTICE "S6105 on Stretch S6000 - " -- cgit v1.2.3 From 607c2add0f3b2cc12567f658e9dfdb07df2b106e Mon Sep 17 00:00:00 2001 From: Daniel Glockner Date: Wed, 10 Jun 2009 12:58:49 -0700 Subject: xtensa: enable s6gmac in s6105_defconfig Signed-off-by: Daniel Glockner Cc: "David S. Miller" Cc: Johannes Weiner Cc: Oskar Schirmer Signed-off-by: Andrew Morton --- arch/xtensa/configs/s6105_defconfig | 49 ++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig index 768bee00603..a1eca01f872 100644 --- a/arch/xtensa/configs/s6105_defconfig +++ b/arch/xtensa/configs/s6105_defconfig @@ -263,7 +263,54 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set -# CONFIG_NETDEVICES is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_S6GMAC=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set -- cgit v1.2.3 From 759c67e87bce54bd08e5fee1fdca975cebe5d3c2 Mon Sep 17 00:00:00 2001 From: Daniel Glockner Date: Wed, 10 Jun 2009 12:58:50 -0700 Subject: xtensa: add m41t62 rtc to s6105 platform Signed-off-by: Daniel Glockner Cc: David Brownell Cc: Alessandro Zummo Signed-off-by: Andrew Morton --- arch/xtensa/platforms/s6105/device.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c index 963634a3463..65333ffefb0 100644 --- a/arch/xtensa/platforms/s6105/device.c +++ b/arch/xtensa/platforms/s6105/device.c @@ -143,6 +143,9 @@ static struct platform_device platform_devices[] = { .resource = s6_gmac_resource, .num_resources = ARRAY_SIZE(s6_gmac_resource), }, + { + I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62), + }, }; static int __init device_init(void) -- cgit v1.2.3 From aafd1255d08fb26cab87d1b28ff35a15bdb2ed68 Mon Sep 17 00:00:00 2001 From: Daniel Glockner Date: Wed, 10 Jun 2009 12:58:51 -0700 Subject: xtensa: enable m41t80 driver in s6105_defconfig Signed-off-by: Daniel Glockner Cc: David Brownell Cc: Alessandro Zummo Signed-off-by: Andrew Morton --- arch/xtensa/configs/s6105_defconfig | 56 +++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig index a1eca01f872..bb84fbc9921 100644 --- a/arch/xtensa/configs/s6105_defconfig +++ b/arch/xtensa/configs/s6105_defconfig @@ -351,8 +351,6 @@ CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set @@ -434,7 +432,59 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +# CONFIG_RTC_INTF_SYSFS is not set +# CONFIG_RTC_INTF_PROC is not set +# CONFIG_RTC_INTF_DEV is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set -- cgit v1.2.3 From d7d1104fa40f66dbe50840f05b34268144f8a17a Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 22 Jun 2009 12:08:03 +0200 Subject: [S390] time: convert from bootmem to slab The slab allocator is earlier available so convert the bootmem allocations to slab/gfp allocations. Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/time.c | 16 ++++------------ arch/s390/kernel/vtime.c | 5 +---- 2 files changed, 5 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 215330a2c12..d4c8e9c47c8 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -62,9 +61,6 @@ u64 sched_clock_base_cc = -1; /* Force to data section. */ -static ext_int_info_t ext_int_info_cc; -static ext_int_info_t ext_int_etr_cc; - static DEFINE_PER_CPU(struct clock_event_device, comparators); /* @@ -255,15 +251,11 @@ void __init time_init(void) stp_reset(); /* request the clock comparator external interrupt */ - if (register_early_external_interrupt(0x1004, - clock_comparator_interrupt, - &ext_int_info_cc) != 0) + if (register_external_interrupt(0x1004, clock_comparator_interrupt)) panic("Couldn't request external interrupt 0x1004"); /* request the timing alert external interrupt */ - if (register_early_external_interrupt(0x1406, - timing_alert_interrupt, - &ext_int_etr_cc) != 0) + if (register_external_interrupt(0x1406, timing_alert_interrupt)) panic("Couldn't request external interrupt 0x1406"); if (clocksource_register(&clocksource_tod) != 0) @@ -1445,14 +1437,14 @@ static void __init stp_reset(void) { int rc; - stp_page = alloc_bootmem_pages(PAGE_SIZE); + stp_page = (void *) get_zeroed_page(GFP_ATOMIC); rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); if (rc == 0) set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); else if (stp_online) { pr_warning("The real or virtual hardware system does " "not provide an STP interface\n"); - free_bootmem((unsigned long) stp_page, PAGE_SIZE); + free_page((unsigned long) stp_page); stp_page = NULL; stp_online = 0; } diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index c8eb7255332..ade17e771f0 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -25,8 +25,6 @@ #include #include -static ext_int_info_t ext_int_info_timer; - static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer); DEFINE_PER_CPU(struct s390_idle_data, s390_idle) = { @@ -557,8 +555,7 @@ void init_cpu_vtimer(void) void __init vtime_init(void) { /* request the cpu timer external interrupt */ - if (register_early_external_interrupt(0x1005, do_cpu_timer_interrupt, - &ext_int_info_timer) != 0) + if (register_external_interrupt(0x1005, do_cpu_timer_interrupt)) panic("Couldn't request external interrupt 0x1005"); /* Enable cpu timer interrupts on the boot cpu. */ -- cgit v1.2.3 From 66d51f3e81b1067bdc836b3aba609eec957c693c Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Mon, 22 Jun 2009 12:08:08 +0200 Subject: [S390] s390: remove DEBUG_MALLOC The kernel now has kmemleak and kmemtrace so there's no reason to keep this ugly s390 hack around. I am not sure how it's supposed to work on SMP anyway as it uses a global variable to temporarily store the return value of all kmalloc() calls: void *b; #define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b) Cc: Cc: Heiko Carstens Signed-off-by: Pekka Enberg Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/debug.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h index 9450ce6e32d..31ed5686a96 100644 --- a/arch/s390/include/asm/debug.h +++ b/arch/s390/include/asm/debug.h @@ -248,14 +248,5 @@ int debug_unregister_view(debug_info_t* id, struct debug_view* view); #define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x ) #endif /* DASD_DEBUG */ -#undef DEBUG_MALLOC -#ifdef DEBUG_MALLOC -void *b; -#define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b) -#define kfree(x) PRINT_INFO(" kfree %p\n",x);kfree(x) -#define get_zeroed_page(x...) (PRINT_INFO(" gfp %p\n",b=get_zeroed_page(x)),b) -#define __get_free_pages(x...) (PRINT_INFO(" gfps %p\n",b=__get_free_pages(x)),b) -#endif /* DEBUG_MALLOC */ - #endif /* __KERNEL__ */ #endif /* DEBUG_H */ -- cgit v1.2.3 From 6618241b47cd131503610d8df68dd6f4948e5c1a Mon Sep 17 00:00:00 2001 From: Jan Glauber Date: Mon, 22 Jun 2009 12:08:15 +0200 Subject: [S390] qdio: Sanitize do_QDIO sanity checks Remove unneeded sanity checks from do_QDIO since this is the hot path. Change the type of bufnr and count to unsigned int so the check for the maximum value works. Reported-by: Roel Kluin Signed-off-by: Jan Glauber Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/qdio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 402d6dcf0d2..79d849f014f 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -380,7 +380,7 @@ extern int qdio_establish(struct qdio_initialize *); extern int qdio_activate(struct ccw_device *); extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, - int q_nr, int bufnr, int count); + int q_nr, unsigned int bufnr, unsigned int count); extern int qdio_cleanup(struct ccw_device*, int); extern int qdio_shutdown(struct ccw_device*, int); extern int qdio_free(struct ccw_device *); -- cgit v1.2.3 From 4a9c75255e1fef4247cf960d3c3eb528c8cd8409 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 22 Jun 2009 12:08:18 +0200 Subject: [S390] pm: fix build error for !SMP Fix build error for !SMP: arch/s390/power/built-in.o: In function `swsusp_arch_resume': (.text+0x1b4): undefined reference to `smp_get_phys_cpu_id' arch/s390/power/built-in.o: In function `swsusp_arch_resume': (.text+0x288): undefined reference to `smp_switch_boot_cpu_in_resume' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/power/swsusp_asm64.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/power/swsusp_asm64.S b/arch/s390/power/swsusp_asm64.S index 3c74e7d827c..76d688da32f 100644 --- a/arch/s390/power/swsusp_asm64.S +++ b/arch/s390/power/swsusp_asm64.S @@ -109,10 +109,11 @@ swsusp_arch_resume: aghi %r15,-STACK_FRAME_OVERHEAD stg %r1,__SF_BACKCHAIN(%r15) +#ifdef CONFIG_SMP /* Save boot cpu number */ brasl %r14,smp_get_phys_cpu_id lgr %r10,%r2 - +#endif /* Deactivate DAT */ stnsm __SF_EMPTY(%r15),0xfb @@ -177,11 +178,12 @@ swsusp_arch_resume: /* Pointer to save arae */ lghi %r13,0x1000 +#ifdef CONFIG_SMP /* Switch CPUs */ lgr %r2,%r10 /* get cpu id */ llgf %r3,0x318(%r13) brasl %r14,smp_switch_boot_cpu_in_resume - +#endif /* Restore prefix register */ spx 0x318(%r13) -- cgit v1.2.3 From e98bbaafcd1c47d30f3245517fb585f1aaaca4db Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Mon, 22 Jun 2009 12:08:20 +0200 Subject: [S390] lockless idle time accounting Replace the spinlock used in the idle time accounting with a sequence counter mechanism analog to seqlock. Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/cputime.h | 2 +- arch/s390/kernel/smp.c | 28 +++++++++++++++++++--------- arch/s390/kernel/vtime.c | 22 +++++++++++++++------- 3 files changed, 35 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h index ec917d42ee6..7a3817a656d 100644 --- a/arch/s390/include/asm/cputime.h +++ b/arch/s390/include/asm/cputime.h @@ -178,7 +178,7 @@ cputime64_to_clock_t(cputime64_t cputime) } struct s390_idle_data { - spinlock_t lock; + unsigned int sequence; unsigned long long idle_count; unsigned long long idle_enter; unsigned long long idle_time; diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index fd8e3111a4e..2270730f535 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -856,13 +856,20 @@ static ssize_t show_idle_count(struct sys_device *dev, { struct s390_idle_data *idle; unsigned long long idle_count; + unsigned int sequence; idle = &per_cpu(s390_idle, dev->id); - spin_lock(&idle->lock); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_count = idle->idle_count; if (idle->idle_enter) idle_count++; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return sprintf(buf, "%llu\n", idle_count); } static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); @@ -872,15 +879,22 @@ static ssize_t show_idle_time(struct sys_device *dev, { struct s390_idle_data *idle; unsigned long long now, idle_time, idle_enter; + unsigned int sequence; idle = &per_cpu(s390_idle, dev->id); - spin_lock(&idle->lock); now = get_clock(); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_time = idle->idle_time; idle_enter = idle->idle_enter; if (idle_enter != 0ULL && idle_enter < now) idle_time += now - idle_enter; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return sprintf(buf, "%llu\n", idle_time >> 12); } static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); @@ -908,11 +922,7 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self, case CPU_ONLINE: case CPU_ONLINE_FROZEN: idle = &per_cpu(s390_idle, cpu); - spin_lock_irq(&idle->lock); - idle->idle_enter = 0; - idle->idle_time = 0; - idle->idle_count = 0; - spin_unlock_irq(&idle->lock); + memset(idle, 0, sizeof(struct s390_idle_data)); if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) return NOTIFY_BAD; break; diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index ade17e771f0..c41bb0d416e 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -27,9 +27,7 @@ static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer); -DEFINE_PER_CPU(struct s390_idle_data, s390_idle) = { - .lock = __SPIN_LOCK_UNLOCKED(s390_idle.lock) -}; +DEFINE_PER_CPU(struct s390_idle_data, s390_idle); static inline __u64 get_vtimer(void) { @@ -151,11 +149,13 @@ void vtime_start_cpu(void) vq->elapsed -= vq->idle - S390_lowcore.async_enter_timer; } - spin_lock(&idle->lock); + idle->sequence++; + smp_wmb(); idle->idle_time += idle_time; idle->idle_enter = 0ULL; idle->idle_count++; - spin_unlock(&idle->lock); + smp_wmb(); + idle->sequence++; } void vtime_stop_cpu(void) @@ -242,15 +242,23 @@ cputime64_t s390_get_idle_time(int cpu) { struct s390_idle_data *idle; unsigned long long now, idle_time, idle_enter; + unsigned int sequence; idle = &per_cpu(s390_idle, cpu); - spin_lock(&idle->lock); + now = get_clock(); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_time = 0; idle_enter = idle->idle_enter; if (idle_enter != 0ULL && idle_enter < now) idle_time = now - idle_enter; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return idle_time; } -- cgit v1.2.3 From 12310e9c1b9a53896e4df0459039dd125f62aa9b Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Mon, 22 Jun 2009 12:08:22 +0200 Subject: [S390] Enable tick based perf_counter on s390. Signed-off-by: Martin Schwidefsky --- arch/s390/Kconfig | 1 + arch/s390/include/asm/perf_counter.h | 8 ++++++++ 2 files changed, 9 insertions(+) create mode 100644 arch/s390/include/asm/perf_counter.h (limited to 'arch') diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index a14dba0e4d6..e577839f307 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -94,6 +94,7 @@ config S390 select HAVE_KVM if 64BIT select HAVE_ARCH_TRACEHOOK select INIT_ALL_POSSIBLE + select HAVE_PERF_COUNTERS source "init/Kconfig" diff --git a/arch/s390/include/asm/perf_counter.h b/arch/s390/include/asm/perf_counter.h new file mode 100644 index 00000000000..a7205a3828c --- /dev/null +++ b/arch/s390/include/asm/perf_counter.h @@ -0,0 +1,8 @@ +/* + * Performance counter support - s390 specific definitions. + * + * Copyright 2009 Martin Schwidefsky, IBM Corporation. + */ + +static inline void set_perf_counter_pending(void) {} +static inline void clear_perf_counter_pending(void) {} -- cgit v1.2.3 From acf018004f76617dbab36ef4b5480d4351f9cdff Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 22 Jun 2009 12:08:23 +0200 Subject: [S390] kprobes: defer setting of ctlblk state get_krobe_ctlblk returns a per cpu kprobe control block which holds the state of the current cpu wrt to kprobe. When inserting/removing a kprobe the state of the cpu which replaces the code is changed to KPROBE_SWAP_INST. This however is done when preemption is still enabled. So the state of the current cpu doesn't necessarily reflect the real state. To fix this move the code that changes the state to non-preemptible context. Reported-by: Ananth N Mavinakayanahalli Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/kprobes.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 9bb2f6241d9..86783efa24e 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -154,39 +154,35 @@ void __kprobes get_instruction_type(struct arch_specific_insn *ainsn) static int __kprobes swap_instruction(void *aref) { + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long status = kcb->kprobe_status; struct ins_replace_args *args = aref; + int rc; - return probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); + kcb->kprobe_status = KPROBE_SWAP_INST; + rc = probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); + kcb->kprobe_status = status; + return rc; } void __kprobes arch_arm_kprobe(struct kprobe *p) { - struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); - unsigned long status = kcb->kprobe_status; struct ins_replace_args args; args.ptr = p->addr; args.old = p->opcode; args.new = BREAKPOINT_INSTRUCTION; - - kcb->kprobe_status = KPROBE_SWAP_INST; stop_machine(swap_instruction, &args, NULL); - kcb->kprobe_status = status; } void __kprobes arch_disarm_kprobe(struct kprobe *p) { - struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); - unsigned long status = kcb->kprobe_status; struct ins_replace_args args; args.ptr = p->addr; args.old = BREAKPOINT_INSTRUCTION; args.new = p->opcode; - - kcb->kprobe_status = KPROBE_SWAP_INST; stop_machine(swap_instruction, &args, NULL); - kcb->kprobe_status = status; } void __kprobes arch_remove_kprobe(struct kprobe *p) -- cgit v1.2.3 From da6330fccc251db73945ee3eb6248985cf2574de Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Mon, 22 Jun 2009 12:08:24 +0200 Subject: [S390] Update default configuration. Signed-off-by: Martin Schwidefsky --- arch/s390/defconfig | 72 +++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 54 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/s390/defconfig b/arch/s390/defconfig index d401d56c255..fcba206529f 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc3 -# Thu Apr 23 09:29:52 2009 +# Linux kernel version: 2.6.30 +# Mon Jun 22 11:08:16 2009 # CONFIG_SCHED_MC=y CONFIG_MMU=y @@ -25,6 +25,7 @@ CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_S390=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -90,7 +91,6 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -103,7 +103,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -119,6 +126,11 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_HAVE_DEFAULT_NO_SPIN_MUTEXES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y @@ -150,7 +162,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_PREEMPT_NOTIFIERS=y -# CONFIG_FREEZER is not set +CONFIG_FREEZER=y # # Base setup @@ -199,6 +211,7 @@ CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -218,9 +231,9 @@ CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # # I/O subsystem configuration @@ -257,6 +270,16 @@ CONFIG_KEXEC=y # CONFIG_ZFCPDUMP is not set CONFIG_S390_GUEST=y CONFIG_SECCOMP=y + +# +# Power Management +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_SLEEP=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" CONFIG_NET=y # @@ -384,6 +407,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # @@ -446,6 +470,7 @@ CONFIG_CAN_BCM=m # CAN Device Drivers # CONFIG_CAN_VCAN=m +# CONFIG_CAN_DEV is not set # CONFIG_CAN_DEBUG_DEVICES is not set # CONFIG_AF_RXRPC is not set # CONFIG_WIMAX is not set @@ -524,10 +549,6 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -578,7 +599,6 @@ CONFIG_DM_MULTIPATH=m # CONFIG_DM_DELAY is not set # CONFIG_DM_UEVENT is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_IFB is not set CONFIG_DUMMY=m CONFIG_BONDING=m @@ -595,6 +615,7 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_KS8842 is not set CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y # CONFIG_TR is not set @@ -674,6 +695,11 @@ CONFIG_S390_TAPE_34XX=m # CONFIG_MONREADER is not set CONFIG_MONWRITER=m CONFIG_S390_VMUR=m + +# +# PPS support +# +# CONFIG_PPS is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set @@ -683,6 +709,10 @@ CONFIG_S390_VMUR=m # CONFIG_NEW_LEDS is not set CONFIG_ACCESSIBILITY=y # CONFIG_AUXDISPLAY is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set # @@ -703,11 +733,12 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -865,19 +896,23 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set @@ -886,6 +921,7 @@ CONFIG_TRACING_SUPPORT=y CONFIG_SAMPLES=y # CONFIG_SAMPLE_KOBJECT is not set # CONFIG_SAMPLE_KPROBES is not set +# CONFIG_KMEMCHECK is not set # # Security options -- cgit v1.2.3 From 6ade7fa7bb4484b4dc78e55700d0f62bacd491e9 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Jun 2009 23:54:43 +0200 Subject: [ARM] S3C64XX: fix HCLK gate defines A few typos seems to have sneaked into the HCLK gate defines, causing the usb host clock to not get enabled. Fix them according to the reference manual and throw in the 3d accel bit for good measure. Signed-off-by: Peter Korsgaard Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d41e33..a8777a755df 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -88,11 +88,11 @@ #define S3C6400_CLKDIV2_SPI0_SHIFT (0) /* HCLK GATE Registers */ -#define S3C_CLKCON_HCLK_BUS (1<<30) -#define S3C_CLKCON_HCLK_SECUR (1<<29) -#define S3C_CLKCON_HCLK_SDMA1 (1<<28) -#define S3C_CLKCON_HCLK_SDMA2 (1<<27) -#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_3DSE (1<<31) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) #define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR0 (1<<23) -- cgit v1.2.3 From 386f43517f8bf026320fd4b9e077140681d7e595 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Jun 2009 23:54:44 +0200 Subject: [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit The usb-host clock was using the wrong define (the SCLK enable for the usb-host-bus) to change the HCLK register instead of the HCLK_UHOST bit. Signed-off-by: Peter Korsgaard Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 0bc2fa1dfc4..7a36e899360 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -191,7 +191,7 @@ static struct clk init_clocks[] = { .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { .name = "hsmmc", .id = 0, -- cgit v1.2.3 From 0b495737f311cb8eb5e66404309ea16e4d7ded8a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 18 Jun 2009 13:30:27 +0200 Subject: [ARM] S3C64XX: add to_irq() support for EINT() GPIO N group Add to_irq() function to onvert gpio to irq for external interrupt group (GPN). Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/gpiolib.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index da7b60ee5e6..92859290ea3 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { .get_pull = s3c_gpio_getpull_updown, }; +int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin) +{ + return IRQ_EINT(0) + pin; +} + static struct s3c_gpio_chip gpio_2bit[] = { { .base = S3C64XX_GPF_BASE, @@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { .base = S3C64XX_GPN(0), .ngpio = S3C64XX_GPIO_N_NR, .label = "GPN", + .to_irq = s3c64xx_gpio2int_gpn, }, }, { .base = S3C64XX_GPO_BASE, -- cgit v1.2.3 From 49fb88af23f3344ba53d6dbe34ac0b1426d81006 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 18 Jun 2009 13:30:16 +0200 Subject: [ARM] S3C: Fix gpio-config off-by-one bug Fix gpio-config off-by-one bug. Without this patch, touching GPA0 pin on S3C64XX platform causes kernel oops. Reviewed-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/gpio-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c index 08044dec973..456969b6fa0 100644 --- a/arch/arm/plat-s3c/gpio-config.c +++ b/arch/arm/plat-s3c/gpio-config.c @@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, unsigned int shift = (off & 7) * 4; u32 con; - if (off < 8 && chip->chip.ngpio >= 8) + if (off < 8 && chip->chip.ngpio > 8) reg -= 4; if (s3c_gpio_is_cfg_special(cfg)) { -- cgit v1.2.3 From 2e8b5a09ebf1f98f02c1988a48415e89d4c25168 Mon Sep 17 00:00:00 2001 From: David Howells Date: Mon, 22 Jun 2009 15:32:36 +0100 Subject: MN10300: Fix the vmlinux ldscript Fix the MN10300 vmlinux ldscript. It needs to use various macros from asm-generic/vmlinux.lds.h to correctly include all that it needs to. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/kernel/vmlinux.lds.S | 60 +++++++++++---------------------------- 1 file changed, 16 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S index 24de6b90f40..bcebcefb4ad 100644 --- a/arch/mn10300/kernel/vmlinux.lds.S +++ b/arch/mn10300/kernel/vmlinux.lds.S @@ -38,14 +38,10 @@ SECTIONS _etext = .; /* End of text section */ - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - + EXCEPTION_TABLE(16) BUG_TABLE - RODATA + RO_DATA(PAGE_SIZE) /* writeable */ .data : { /* Data */ @@ -53,27 +49,19 @@ SECTIONS CONSTRUCTORS } - . = ALIGN(PAGE_SIZE); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(PAGE_SIZE); - __nosave_end = .; - - . = ALIGN(PAGE_SIZE); - .data.page_aligned : { *(.data.idt) } + .data_nosave : { NOSAVE_DATA; } - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } + .data.page_aligned : { PAGE_ALIGNED_DATA(PAGE_SIZE); } + .data.cacheline_aligned : { CACHELINE_ALIGNED_DATA(32); } /* rarely changed data like cpu maps */ . = ALIGN(32); .data.read_mostly : AT(ADDR(.data.read_mostly)) { - *(.data.read_mostly) + READ_MOSTLY_DATA(32); _edata = .; /* End of data section */ } - . = ALIGN(THREAD_SIZE); /* init_task */ - .data.init_task : { *(.data.init_task) } + .data.init_task : { INIT_TASK(THREAD_SIZE); } /* might get freed after init */ . = ALIGN(PAGE_SIZE); @@ -88,23 +76,18 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - *(.init.text) + INIT_TEXT; _einittext = .; } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .setup.init : { KEEP(*(.init.setup)) } - __setup_end = .; + .init.data : { INIT_DATA; } + .setup.init : { INIT_SETUP(16); } __initcall_start = .; .initcall.init : { INITCALLS } __initcall_end = .; - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; + .con_initcall.init : { CON_INITCALL; } SECURITY_INIT . = ALIGN(4); @@ -114,28 +97,17 @@ SECTIONS .altinstr_replacement : { *(.altinstr_replacement) } /* .exit.text is discard at runtime, not link time, to deal with references from .altinstructions and .eh_frame */ - .exit.text : { *(.exit.text) } - .exit.data : { *(.exit.data) } + .exit.text : { EXIT_TEXT; } + .exit.data : { EXIT_DATA; } -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(PAGE_SIZE); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; -#endif + .init.ramfs : { INIT_RAM_FS; } PERCPU(32) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ - __bss_start = .; /* BSS */ - .bss : { - *(.bss.page_aligned) - *(.bss) - } - . = ALIGN(4); - __bss_stop = .; + BSS(4) _end = . ; @@ -145,7 +117,7 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - *(.exitcall.exit) + EXIT_CALL } STABS_DEBUG -- cgit v1.2.3 From 9ccdac3662dbf3c75e8f8851a214bdf7d365a4bd Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 22 Jun 2009 22:34:55 +0100 Subject: [ARM] idle: clean up pm_idle calling, obey hlt_counter pm_idle is used by infrastructure (eg, cpuidle) which expects architectures to call it in a certain way. Arrange for ARM to follow x86's lead on this and call pm_idle() with interrupts already disabled. However, we expect pm_idle() to enable interrupts before it returns. Also, OMAP wants to be able to disable hlt-ing, so allow hlt_counter to prevent all calls to pm_idle. Signed-off-by: Russell King --- arch/arm/kernel/process.c | 58 ++++++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 56820cce91a..39196dff478 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd) /* * Function pointers to optional machine specific functions */ -void (*pm_idle)(void); -EXPORT_SYMBOL(pm_idle); - void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); @@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart); */ static void default_idle(void) { - if (hlt_counter) - cpu_relax(); - else { - local_irq_disable(); - if (!need_resched()) - arch_idle(); - local_irq_enable(); - } + if (!need_resched()) + arch_idle(); + local_irq_enable(); } +void (*pm_idle)(void) = default_idle; +EXPORT_SYMBOL(pm_idle); + /* - * The idle thread. We try to conserve power, while trying to keep - * overall latency low. The architecture specific idle is passed - * a value to indicate the level of "idleness" of the system. + * The idle thread, has rather strange semantics for calling pm_idle, + * but this is what x86 does and we need to do the same, so that + * things like cpuidle get called in the same way. The only difference + * is that we always respect 'hlt_counter' to prevent low power idle. */ void cpu_idle(void) { @@ -151,21 +147,31 @@ void cpu_idle(void) /* endless idle loop with no priority at all */ while (1) { - void (*idle)(void) = pm_idle; - + tick_nohz_stop_sched_tick(1); + leds_event(led_idle_start); + while (!need_resched()) { #ifdef CONFIG_HOTPLUG_CPU - if (cpu_is_offline(smp_processor_id())) { - leds_event(led_idle_start); - cpu_die(); - } + if (cpu_is_offline(smp_processor_id())) + cpu_die(); #endif - if (!idle) - idle = default_idle; - leds_event(led_idle_start); - tick_nohz_stop_sched_tick(1); - while (!need_resched()) - idle(); + local_irq_disable(); + if (hlt_counter) { + local_irq_enable(); + cpu_relax(); + } else { + stop_critical_timings(); + pm_idle(); + start_critical_timings(); + /* + * This will eventually be removed - pm_idle + * functions should always return with IRQs + * enabled. + */ + WARN_ON(irqs_disabled()); + local_irq_enable(); + } + } leds_event(led_idle_end); tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); -- cgit v1.2.3 From e56e03b0cfeb997a4be9ad874c193824364942e0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 7 Jun 2009 16:31:52 -0400 Subject: Blackfin: unify memory region checks between kgdb and traps The kgdb (in multiple places) and traps code developed pretty much identical checks for how to access different regions of the Blackfin memory map, but each wasn't 100%, so unify them to avoid duplication, bitrot, and bugs with edge cases. Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/uaccess.h | 22 +++ arch/blackfin/kernel/kgdb.c | 297 ++++++++++++------------------------ arch/blackfin/kernel/process.c | 151 ++++++++++++++---- arch/blackfin/kernel/traps.c | 60 +++----- 4 files changed, 256 insertions(+), 274 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 8894e9ffbb5..2f469a1f80f 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n) #define clear_user(to, n) __clear_user(to, n) +/* How to interpret these return values: + * CORE: can be accessed by core load or dma memcpy + * CORE_ONLY: can only be accessed by core load + * DMA: can only be accessed by dma memcpy + * IDMA: can only be accessed by interprocessor dma memcpy (BF561) + * ITEST: can be accessed by isram memcpy or dma memcpy + */ +enum { + BFIN_MEM_ACCESS_CORE = 0, + BFIN_MEM_ACCESS_CORE_ONLY, + BFIN_MEM_ACCESS_DMA, + BFIN_MEM_ACCESS_IDMA, + BFIN_MEM_ACCESS_ITEST, +}; +/** + * bfin_mem_access_type() - what kind of memory access is required + * @addr: the address to check + * @size: number of bytes needed + * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above) + */ +int bfin_mem_access_type(unsigned long addr, unsigned long size); + #endif /* _BLACKFIN_UACCESS_H */ diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index da28f796ad7..cce79d05b90 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -34,15 +34,6 @@ int gdb_bfin_vector = -1; #error change the definition of slavecpulocks #endif -#define IN_MEM(addr, size, l1_addr, l1_size) \ -({ \ - unsigned long __addr = (unsigned long)(addr); \ - (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ -}) -#define ASYNC_BANK_SIZE \ - (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ - ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) - void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) { gdb_regs[BFIN_R0] = regs->r0; @@ -463,41 +454,88 @@ static int hex(char ch) static int validate_memory_access_address(unsigned long addr, int size) { - int cpu = raw_smp_processor_id(); - - if (size < 0) + if (size < 0 || addr == 0) return -EFAULT; - if (addr >= 0x1000 && (addr + size) <= physical_mem_end) - return 0; - if (addr >= SYSMMR_BASE) - return 0; - if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) - return 0; - if (cpu == 0) { - if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) - return 0; -#ifdef CONFIG_SMP - } else if (cpu == 1) { - if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return bfin_mem_access_type(addr, size); +} + +static int bfin_probe_kernel_read(char *dst, char *src, int size) +{ + unsigned long lsrc = (unsigned long)src; + int mem_type; + + mem_type = validate_memory_access_address(lsrc, size); + if (mem_type < 0) + return mem_type; + + if (lsrc >= SYSMMR_BASE) { + if (size == 2 && lsrc % 2 == 0) { + u16 mmr = bfin_read16(src); + memcpy(dst, &mmr, sizeof(mmr)); return 0; - if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + } else if (size == 4 && lsrc % 4 == 0) { + u32 mmr = bfin_read32(src); + memcpy(dst, &mmr, sizeof(mmr)); return 0; - if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + } + } else { + switch (mem_type) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + return probe_kernel_read(dst, src, size); + /* XXX: should support IDMA here with SMP */ + case BFIN_MEM_ACCESS_DMA: + if (dma_memcpy(dst, src, size)) + return 0; + break; + case BFIN_MEM_ACCESS_ITEST: + if (isram_memcpy(dst, src, size)) + return 0; + break; + } + } + + return -EFAULT; +} + +static int bfin_probe_kernel_write(char *dst, char *src, int size) +{ + unsigned long ldst = (unsigned long)dst; + int mem_type; + + mem_type = validate_memory_access_address(ldst, size); + if (mem_type < 0) + return mem_type; + + if (ldst >= SYSMMR_BASE) { + if (size == 2 && ldst % 2 == 0) { + u16 mmr; + memcpy(&mmr, src, sizeof(mmr)); + bfin_write16(dst, mmr); return 0; - if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + } else if (size == 4 && ldst % 4 == 0) { + u32 mmr; + memcpy(&mmr, src, sizeof(mmr)); + bfin_write32(dst, mmr); return 0; -#endif + } + } else { + switch (mem_type) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + return probe_kernel_write(dst, src, size); + /* XXX: should support IDMA here with SMP */ + case BFIN_MEM_ACCESS_DMA: + if (dma_memcpy(dst, src, size)) + return 0; + break; + case BFIN_MEM_ACCESS_ITEST: + if (isram_memcpy(dst, src, size)) + return 0; + break; + } } - if (IN_MEM(addr, size, L2_START, L2_LENGTH)) - return 0; - return -EFAULT; } @@ -509,14 +547,6 @@ int kgdb_mem2hex(char *mem, char *buf, int count) { char *tmp; int err; - unsigned char *pch; - unsigned short mmr16; - unsigned long mmr32; - int cpu = raw_smp_processor_id(); - - err = validate_memory_access_address((unsigned long)mem, count); - if (err) - return err; /* * We use the upper half of buf as an intermediate buffer for the @@ -524,44 +554,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count) */ tmp = buf + count; - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (count) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = *(unsigned short *)mem; - pch = (unsigned char *)&mmr16; - *tmp++ = *pch++; - *tmp++ = *pch++; - tmp -= 2; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = *(unsigned long *)mem; - pch = (unsigned char *)&mmr32; - *tmp++ = *pch++; - *tmp++ = *pch++; - *tmp++ = *pch++; - *tmp++ = *pch++; - tmp -= 4; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM*/ - if (dma_memcpy(tmp, mem, count) == NULL) - err = -EFAULT; - } else - err = probe_kernel_read(tmp, mem, count); - + err = bfin_probe_kernel_read(tmp, mem, count); if (!err) { while (count > 0) { buf = pack_hex_byte(buf, *tmp); @@ -582,13 +575,8 @@ int kgdb_mem2hex(char *mem, char *buf, int count) */ int kgdb_ebin2mem(char *buf, char *mem, int count) { - char *tmp_old; - char *tmp_new; - unsigned short *mmr16; - unsigned long *mmr32; - int err; + char *tmp_old, *tmp_new; int size; - int cpu = raw_smp_processor_id(); tmp_old = tmp_new = buf; @@ -601,41 +589,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) tmp_old++; } - err = validate_memory_access_address((unsigned long)mem, size); - if (err) - return err; - - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (size) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = (unsigned short *)buf; - *(unsigned short *)mem = *mmr16; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = (unsigned long *)buf; - *(unsigned long *)mem = *mmr32; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(mem, buf, size) == NULL) - err = -EFAULT; - } else - err = probe_kernel_write(mem, buf, size); - - return err; + return bfin_probe_kernel_write(mem, buf, count); } /* @@ -645,16 +599,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) */ int kgdb_hex2mem(char *buf, char *mem, int count) { - char *tmp_raw; - char *tmp_hex; - unsigned short *mmr16; - unsigned long *mmr32; - int err; - int cpu = raw_smp_processor_id(); - - err = validate_memory_access_address((unsigned long)mem, count); - if (err) - return err; + char *tmp_raw, *tmp_hex; /* * We use the upper half of buf as an intermediate buffer for the @@ -669,39 +614,18 @@ int kgdb_hex2mem(char *buf, char *mem, int count) *tmp_raw |= hex(*tmp_hex--) << 4; } - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (count) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = (unsigned short *)tmp_raw; - *(unsigned short *)mem = *mmr16; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = (unsigned long *)tmp_raw; - *(unsigned long *)mem = *mmr32; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(mem, tmp_raw, count) == NULL) - err = -EFAULT; - } else - err = probe_kernel_write(mem, tmp_raw, count); - - return err; + return bfin_probe_kernel_write(mem, tmp_raw, count); } +#define IN_MEM(addr, size, l1_addr, l1_size) \ +({ \ + unsigned long __addr = (unsigned long)(addr); \ + (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ +}) +#define ASYNC_BANK_SIZE \ + (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) + int kgdb_validate_break_address(unsigned long addr) { int cpu = raw_smp_processor_id(); @@ -724,46 +648,17 @@ int kgdb_validate_break_address(unsigned long addr) int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) { - int err; - int cpu = raw_smp_processor_id(); - - if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE) - == NULL) - return -EFAULT; - - if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr, - BREAK_INSTR_SIZE) == NULL) - return -EFAULT; - - return 0; - } else { - err = probe_kernel_read(saved_instr, (char *)addr, - BREAK_INSTR_SIZE); - if (err) - return err; - - return probe_kernel_write((char *)addr, - arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE); - } + int err = bfin_probe_kernel_read(saved_instr, (char *)addr, + BREAK_INSTR_SIZE); + if (err) + return err; + return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr, + BREAK_INSTR_SIZE); } int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) { - if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) { - /* access L1 instruction SRAM */ - if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) - return -EFAULT; - - return 0; - } else - return probe_kernel_write((char *)addr, - (char *)bundle, BREAK_INSTR_SIZE); + return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE); } int kgdb_arch_init(void) diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 3e1d86e456f..79cad0ac589 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -344,6 +344,87 @@ void finish_atomic_sections (struct pt_regs *regs) } } +static inline +int in_mem(unsigned long addr, unsigned long size, + unsigned long start, unsigned long end) +{ + return addr >= start && addr + size <= end; +} +static inline +int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off, + unsigned long const_addr, unsigned long const_size) +{ + return const_size && + in_mem(addr, size, const_addr + off, const_addr + const_size); +} +static inline +int in_mem_const(unsigned long addr, unsigned long size, + unsigned long const_addr, unsigned long const_size) +{ + return in_mem_const_off(addr, 0, size, const_addr, const_size); +} +#define IN_ASYNC(bnum, bctlnum) \ +({ \ + (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ + bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ + BFIN_MEM_ACCESS_CORE; \ +}) + +int bfin_mem_access_type(unsigned long addr, unsigned long size) +{ + int cpu = raw_smp_processor_id(); + + /* Check that things do not wrap around */ + if (addr > ULONG_MAX - size) + return -EFAULT; + + if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end)) + return BFIN_MEM_ACCESS_CORE; + + if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; + if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; +#ifdef COREB_L1_CODE_START + if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; +#endif + if (in_mem_const(addr, size, L2_START, L2_LENGTH)) + return BFIN_MEM_ACCESS_CORE; + + if (addr >= SYSMMR_BASE) + return BFIN_MEM_ACCESS_CORE_ONLY; + + /* We can't read EBIU banks that aren't enabled or we end up hanging + * on the access to the async space. + */ + if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) + return IN_ASYNC(0, 0); + if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE)) + return IN_ASYNC(1, 0); + if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE)) + return IN_ASYNC(2, 1); + if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE)) + return IN_ASYNC(3, 1); + + if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) + return BFIN_MEM_ACCESS_CORE; + if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) + return BFIN_MEM_ACCESS_DMA; + + return -EFAULT; +} + #if defined(CONFIG_ACCESS_CHECK) #ifdef CONFIG_ACCESS_OK_L1 __attribute__((l1_text)) @@ -353,51 +434,61 @@ int _access_ok(unsigned long addr, unsigned long size) { if (size == 0) return 1; - if (addr > (addr + size)) + /* Check that things do not wrap around */ + if (addr > ULONG_MAX - size) return 0; if (segment_eq(get_fs(), KERNEL_DS)) return 1; #ifdef CONFIG_MTD_UCLINUX - if (addr >= memory_start && (addr + size) <= memory_end) - return 1; - if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end) + if (1) +#else + if (0) +#endif + { + if (in_mem(addr, size, memory_start, memory_end)) + return 1; + if (in_mem(addr, size, memory_mtd_end, physical_mem_end)) + return 1; +# ifndef CONFIG_ROMFS_ON_MTD + if (0) +# endif + /* For XIP, allow user space to use pointers within the ROMFS. */ + if (in_mem(addr, size, memory_mtd_start, memory_mtd_end)) + return 1; + } else { + if (in_mem(addr, size, memory_start, physical_mem_end)) + return 1; + } + + if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end)) return 1; -#ifdef CONFIG_ROMFS_ON_MTD - /* For XIP, allow user space to use pointers within the ROMFS. */ - if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end) + if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif -#else - if (addr >= memory_start && (addr + size) <= physical_mem_end) + if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif - if (addr >= (unsigned long)__init_begin && - addr + size <= (unsigned long)__init_end) + if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH)) return 1; - if (addr >= get_l1_scratch_start() - && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH) + if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) return 1; -#if L1_CODE_LENGTH != 0 - if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1) - && addr + size <= get_l1_code_start() + L1_CODE_LENGTH) +#ifdef COREB_L1_CODE_START + if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif -#if L1_DATA_A_LENGTH != 0 - if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1) - && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH) + if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) return 1; -#endif -#if L1_DATA_B_LENGTH != 0 - if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1) - && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH) + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) return 1; -#endif -#if L2_LENGTH != 0 - if (addr >= L2_START + (_ebss_l2 - _stext_l2) - && addr + size <= L2_START + L2_LENGTH) + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) return 1; #endif + if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) + return 1; + + if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) + return 1; + if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) + return 1; + return 0; } EXPORT_SYMBOL(_access_ok); diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index d279552fe9b..8eeb457ce5d 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -636,57 +637,30 @@ asmlinkage void trap_c(struct pt_regs *fp) */ static bool get_instruction(unsigned short *val, unsigned short *address) { - - unsigned long addr; - - addr = (unsigned long)address; + unsigned long addr = (unsigned long)address; /* Check for odd addresses */ if (addr & 0x1) return false; - /* Check that things do not wrap around */ - if (addr > (addr + 2)) + /* MMR region will never have instructions */ + if (addr >= SYSMMR_BASE) return false; - /* - * Since we are in exception context, we need to do a little address checking - * We need to make sure we are only accessing valid memory, and - * we don't read something in the async space that can hang forever - */ - if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) || -#if L2_LENGTH != 0 - (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) || -#endif - (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) || -#if L1_DATA_A_LENGTH != 0 - (addr >= L1_DATA_A_START && (addr + 2) <= (L1_DATA_A_START + L1_DATA_A_LENGTH)) || -#endif -#if L1_DATA_B_LENGTH != 0 - (addr >= L1_DATA_B_START && (addr + 2) <= (L1_DATA_B_START + L1_DATA_B_LENGTH)) || -#endif - (addr >= L1_SCRATCH_START && (addr + 2) <= (L1_SCRATCH_START + L1_SCRATCH_LENGTH)) || - (!(bfin_read_EBIU_AMBCTL0() & B0RDYEN) && - addr >= ASYNC_BANK0_BASE && (addr + 2) <= (ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)) || - (!(bfin_read_EBIU_AMBCTL0() & B1RDYEN) && - addr >= ASYNC_BANK1_BASE && (addr + 2) <= (ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)) || - (!(bfin_read_EBIU_AMBCTL1() & B2RDYEN) && - addr >= ASYNC_BANK2_BASE && (addr + 2) <= (ASYNC_BANK2_BASE + ASYNC_BANK1_SIZE)) || - (!(bfin_read_EBIU_AMBCTL1() & B3RDYEN) && - addr >= ASYNC_BANK3_BASE && (addr + 2) <= (ASYNC_BANK3_BASE + ASYNC_BANK1_SIZE))) { - *val = *address; - return true; + switch (bfin_mem_access_type(addr, 2)) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + *val = *address; + return true; + case BFIN_MEM_ACCESS_DMA: + dma_memcpy(val, address, 2); + return true; + case BFIN_MEM_ACCESS_ITEST: + isram_memcpy(val, address, 2); + return true; + default: /* invalid access */ + return false; } - -#if L1_CODE_LENGTH != 0 - if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) { - isram_memcpy(val, address, 2); - return true; - } -#endif - - - return false; } /* -- cgit v1.2.3 From 2780cd64346782a6116e316c559d70a7655ab6e5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 11 Jun 2009 09:22:02 -0400 Subject: Blackfin: bf518f-ezbrd: update DSA resources The common DSA code changed structure layout, so update the BF518F-EZBRD resources accordingly. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf518/boards/ezbrd.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 1382f038235..d9791106be9 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -119,13 +119,19 @@ static struct platform_device bfin_mac_device = { }; #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) -static struct dsa_platform_data ksz8893m_switch_data = { +static struct dsa_chip_data ksz8893m_switch_chip_data = { .mii_bus = &bfin_mii_bus.dev, + .port_names = { + NULL, + "eth%d", + "eth%d", + "cpu", + }, +}; +static struct dsa_platform_data ksz8893m_switch_data = { + .nr_chips = 1, .netdev = &bfin_mac_device.dev, - .port_names[0] = NULL, - .port_names[1] = "eth%d", - .port_names[2] = "eth%d", - .port_names[3] = "cpu", + .chip = &ksz8893m_switch_chip_data, }; static struct platform_device ksz8893m_switch_device = { -- cgit v1.2.3 From 4d5e6fd42c137dad3b1aced073c6fcb494a8e507 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 13 Jun 2009 06:34:49 -0400 Subject: Blackfin: bf533-ezkit: add resources for FISP devices The BF533-EZKIT has two Flash In-System Programming devices hooked up to the async memory bus, so add resources for the primary flashes and the SRAMs on the devices. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf533/boards/ezkit.c | 106 ++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) (limited to 'arch') diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 89a5ec4ca04..4e3e511bf14 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) @@ -86,6 +87,101 @@ static struct platform_device smc91x_device = { }; #endif +#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) +static const char *map_probes[] = { + "stm_flash", + NULL, +}; + +static struct platdata_mtd_ram stm_pri_data_a = { + .mapname = "Flash A Primary", + .map_probes = map_probes, + .bankwidth = 2, +}; + +static struct resource stm_pri_resource_a = { + .start = 0x20000000, + .end = 0x200fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device stm_pri_device_a = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &stm_pri_data_a, + }, + .num_resources = 1, + .resource = &stm_pri_resource_a, +}; + +static struct platdata_mtd_ram stm_pri_data_b = { + .mapname = "Flash B Primary", + .map_probes = map_probes, + .bankwidth = 2, +}; + +static struct resource stm_pri_resource_b = { + .start = 0x20100000, + .end = 0x201fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device stm_pri_device_b = { + .name = "mtd-ram", + .id = 4, + .dev = { + .platform_data = &stm_pri_data_b, + }, + .num_resources = 1, + .resource = &stm_pri_resource_b, +}; +#endif + +#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) +static struct platdata_mtd_ram sram_data_a = { + .mapname = "Flash A SRAM", + .bankwidth = 2, +}; + +static struct resource sram_resource_a = { + .start = 0x20240000, + .end = 0x2024ffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sram_device_a = { + .name = "mtd-ram", + .id = 8, + .dev = { + .platform_data = &sram_data_a, + }, + .num_resources = 1, + .resource = &sram_resource_a, +}; + +static struct platdata_mtd_ram sram_data_b = { + .mapname = "Flash B SRAM", + .bankwidth = 2, +}; + +static struct resource sram_resource_b = { + .start = 0x202c0000, + .end = 0x202cffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sram_device_b = { + .name = "mtd-ram", + .id = 9, + .dev = { + .platform_data = &sram_data_b, + }, + .num_resources = 1, + .resource = &sram_resource_b, +}; +#endif + #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition bfin_spi_flash_partitions[] = { { @@ -357,6 +453,16 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_dpmc, +#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) + &stm_pri_device_a, + &stm_pri_device_b, +#endif + +#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) + &sram_device_a, + &sram_device_b, +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif -- cgit v1.2.3 From a200ad22bb15fe01cf222fa631687876baad5e01 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 13 Jun 2009 06:37:14 -0400 Subject: Blackfin: update anomaly lists Update anomaly headers to match latest released anomaly sheets. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf518/include/mach/anomaly.h | 37 ++++++---- arch/blackfin/mach-bf527/include/mach/anomaly.h | 15 ++++- arch/blackfin/mach-bf533/include/mach/anomaly.h | 77 +++++++++++---------- arch/blackfin/mach-bf537/include/mach/anomaly.h | 41 +++++++----- arch/blackfin/mach-bf538/include/mach/anomaly.h | 24 ++++--- arch/blackfin/mach-bf548/include/mach/anomaly.h | 20 ++++-- arch/blackfin/mach-bf561/include/mach/anomaly.h | 89 +++++++++++++------------ 7 files changed, 178 insertions(+), 125 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index b69bd9af38d..426e064062a 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -7,7 +7,7 @@ */ /* This file should be up to date with: - * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ @@ -18,7 +18,7 @@ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) @@ -45,29 +45,31 @@ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (1) +#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (1) /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 (1) +#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ -#define ANOMALY_05000438 (1) +#define ANOMALY_05000438 (__SILICON_REVISION__ < 1) /* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (1) +#define ANOMALY_05000439 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (1) +#define ANOMALY_05000440 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* Incorrect L1 Instruction Bank B Memory Map Location */ -#define ANOMALY_05000444 (1) +#define ANOMALY_05000444 (__SILICON_REVISION__ < 1) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (1) +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* PWM_TRIPB Signal Not Available on PG10 */ -#define ANOMALY_05000453 (1) +#define ANOMALY_05000453 (__SILICON_REVISION__ < 1) /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ -#define ANOMALY_05000455 (1) -/* False Hardware Error when RETI points to invalid memory */ +#define ANOMALY_05000455 (__SILICON_REVISION__ < 1) +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -78,24 +80,30 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) @@ -103,10 +111,13 @@ #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (0) +#define ANOMALY_05000357 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) @@ -117,5 +128,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index c84ddea9574..0d63f740616 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -34,7 +34,7 @@ #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -184,8 +184,12 @@ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -195,24 +199,30 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) @@ -220,6 +230,7 @@ #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 31145b509e2..70a0ad69c61 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -34,7 +34,7 @@ # define ANOMALY_BF533 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) @@ -46,7 +46,7 @@ #define ANOMALY_05000122 (1) /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) @@ -56,13 +56,13 @@ #define ANOMALY_05000180 (1) /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) @@ -74,7 +74,7 @@ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) @@ -106,7 +106,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ +/* Data CPLBs Should Prevent False Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) @@ -148,21 +148,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -170,11 +170,11 @@ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) @@ -200,7 +200,7 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are @@ -215,17 +215,17 @@ #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) /* Writing FIO_DIR can corrupt a programmable flag's data */ #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled */ +/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) /* Internal Clocking Modes on SPORT0 not supported */ #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) /* Internal voltage regulator does not wake up from an RTC wakeup */ #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH instruction must be preceded by a CSYNC instruction */ +/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ +/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ +/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) @@ -235,45 +235,45 @@ #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ +/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect value written to the cycle counters */ +/* Incorrect Value Written to the Cycle Counters */ #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data memory incorrect when a specific sequence is followed */ +/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) /* Programmable Flag (PF3) functionality not supported in all PPI modes */ #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) /* Data store can be lost when targeting a cache line fill */ #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved bits in SYSCFG register not set at power on */ +/* Reserved Bits in SYSCFG Register Not Set at Power-On */ #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) /* Infinite Core Stall */ #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers */ +/* PPI_FSx may glitch when generated by the on chip Timers. */ #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SPI clock polarity and phase bits incorrect during booting */ #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ +/* DMEM_CONTROL<12> Is Not Set on Reset */ #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) /* SPI boot will not complete if there is a zero fill block in the loader file */ #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ +/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -287,7 +287,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) @@ -295,13 +295,13 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) /* DMA vs Core accesses to external memory */ #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) @@ -309,15 +309,15 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ +/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) @@ -326,6 +326,7 @@ #define ANOMALY_05000120 (0) #define ANOMALY_05000149 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) @@ -345,5 +346,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index fc966342546..57c128cc3b6 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -34,13 +34,13 @@ # define ANOMALY_BF537 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) @@ -50,11 +50,11 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +/* Buffered CLKIN Output Is Disabled by Default */ #define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ +/* EMAC TX DMA Error After an Early Frame Abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) @@ -62,7 +62,7 @@ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ +/* EMAC MDIO Input Latched on Wrong MDC Edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) @@ -80,7 +80,7 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) @@ -92,15 +92,15 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ +/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) @@ -112,25 +112,25 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ +/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ +/* UART Gets Disabled after UART Boot */ #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) @@ -154,7 +154,7 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ @@ -165,14 +165,17 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) @@ -195,5 +198,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 175ca9ef723..c97acdf85cd 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -30,13 +30,13 @@ # define ANOMALY_BF539 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (1) @@ -70,11 +70,11 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) @@ -92,11 +92,11 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) @@ -110,7 +110,7 @@ #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) -/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ +/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) @@ -126,26 +126,32 @@ #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) #define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) #define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) #define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000305 (0) @@ -166,5 +172,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index c510ae688e2..18a4cd24f67 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -18,7 +18,7 @@ # error will not work on BF548 silicon version 0.0, or 0.1 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) @@ -30,17 +30,17 @@ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ +/* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) @@ -178,8 +178,12 @@ #define ANOMALY_05000450 (1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -189,30 +193,36 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) #define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index dccd396cd93..94b8e277f09 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -18,19 +18,19 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) @@ -40,7 +40,7 @@ #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -52,7 +52,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) /* DMA engine may lose data due to incorrect handshaking */ #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) @@ -66,7 +66,7 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) @@ -76,17 +76,17 @@ #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) /* DMEM_CONTROL<12> is not set on Reset */ #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) /* DSPID register values incorrect */ #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) @@ -96,29 +96,29 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) @@ -126,7 +126,7 @@ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +134,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -158,7 +158,7 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) @@ -166,7 +166,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -192,9 +192,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,7 +202,7 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) @@ -212,17 +212,17 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +230,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -276,7 +276,7 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ @@ -284,6 +284,7 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) @@ -298,5 +299,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif -- cgit v1.2.3 From 26579216f3cdf1ae05f0af8412b444870a167510 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 15 Jun 2009 06:10:03 -0400 Subject: Blackfin: redo handling of bad irqs With the common IRQ code initializing much more of the irq_desc state, we can't blindly initialize it ourselves to the local bad_irq state. If we do, we end up wrongly clobbering many fields. So punt most of the bad irq code as the common layers will handle the default state, and simply call handle_bad_irq() directly when the IRQ we are processing is invalid. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/irqchip.c | 53 +++++++++--------------------------------- 1 file changed, 11 insertions(+), 42 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 6e31e935bb3..36bba302773 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -38,38 +38,15 @@ #include static atomic_t irq_err_count; -static spinlock_t irq_controller_lock; - -/* - * Dummy mask/unmask handler - */ -void dummy_mask_unmask_irq(unsigned int irq) -{ -} - void ack_bad_irq(unsigned int irq) { atomic_inc(&irq_err_count); printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); } -static struct irq_chip bad_chip = { - .ack = dummy_mask_unmask_irq, - .mask = dummy_mask_unmask_irq, - .unmask = dummy_mask_unmask_irq, -}; - -static int bad_stats; static struct irq_desc bad_irq_desc = { - .status = IRQ_DISABLED, - .chip = &bad_chip, .handle_irq = handle_bad_irq, - .depth = 1, .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), - .kstat_irqs = &bad_stats, -#ifdef CONFIG_SMP - .affinity = CPU_MASK_ALL -#endif }; #ifdef CONFIG_CPUMASK_OFFSTACK @@ -119,21 +96,13 @@ __attribute__((l1_text)) #endif asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) { - struct pt_regs *old_regs; - struct irq_desc *desc = irq_desc + irq; #ifndef CONFIG_IPIPE unsigned short pending, other_ints; #endif - old_regs = set_irq_regs(regs); - - /* - * Some hardware gives randomly wrong interrupts. Rather - * than crashing, do something sensible. - */ - if (irq >= NR_IRQS) - desc = &bad_irq_desc; + struct pt_regs *old_regs = set_irq_regs(regs); irq_enter(); + #ifdef CONFIG_DEBUG_STACKOVERFLOW /* Debugging check for stack overflow: is there less than STACK_WARN free? */ { @@ -149,7 +118,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) } } #endif - generic_handle_irq(irq); + + /* + * Some hardware gives randomly wrong interrupts. Rather + * than crashing, do something sensible. + */ + if (irq >= NR_IRQS) + handle_bad_irq(irq, &bad_irq_desc); + else + generic_handle_irq(irq); #ifndef CONFIG_IPIPE /* @@ -173,14 +150,6 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) void __init init_IRQ(void) { - struct irq_desc *desc; - int irq; - - spin_lock_init(&irq_controller_lock); - for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++) { - *desc = bad_irq_desc; - } - init_arch_irq(); #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND -- cgit v1.2.3 From 46f288a0f983401ebadb918751d342cbf819cde5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 15 Jun 2009 06:13:58 -0400 Subject: Blackfin: only build show_interrupts() when procfs is enabled Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/irqchip.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 36bba302773..8abb642283b 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -54,6 +54,7 @@ static struct irq_desc bad_irq_desc = { #error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." #endif +#ifdef CONFIG_PROC_FS int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; @@ -85,6 +86,7 @@ int show_interrupts(struct seq_file *p, void *v) } return 0; } +#endif /* * do_IRQ handles all hardware IRQs. Decoded IRQs should not -- cgit v1.2.3 From 6f10fdabdce356aac3c948e659f39b6f1e2f7382 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 15 Jun 2009 06:18:38 -0400 Subject: Blackfin: simplify irq stack overflow checking Take a page from x86 and abstract the stack checking out of the asm_do_IRQ() function so that the result is easier to digest. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/irqchip.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 8abb642283b..7378440792a 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -88,6 +88,22 @@ int show_interrupts(struct seq_file *p, void *v) } #endif +#ifdef CONFIG_DEBUG_STACKOVERFLOW +static void check_stack_overflow(int irq) +{ + /* Debugging check for stack overflow: is there less than STACK_WARN free? */ + long sp = __get_SP() & (THREAD_SIZE - 1); + + if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { + dump_stack(); + pr_emerg("irq%i: possible stack overflow only %ld bytes free\n", + irq, sp - sizeof(struct thread_info)); + } +} +#else +static inline void check_stack_overflow(int irq) { } +#endif + /* * do_IRQ handles all hardware IRQs. Decoded IRQs should not * come via this function. Instead, they should provide their @@ -105,21 +121,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) irq_enter(); -#ifdef CONFIG_DEBUG_STACKOVERFLOW - /* Debugging check for stack overflow: is there less than STACK_WARN free? */ - { - long sp; - - sp = __get_SP() & (THREAD_SIZE-1); - - if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { - dump_stack(); - printk(KERN_EMERG "%s: possible stack overflow while handling irq %i " - " only %ld bytes free\n", - __func__, irq, sp - sizeof(struct thread_info)); - } - } -#endif + check_stack_overflow(irq); /* * Some hardware gives randomly wrong interrupts. Rather -- cgit v1.2.3 From 81b79c213d0200fdd16951a9fb18748fd511d810 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 15 Jun 2009 06:22:08 -0400 Subject: Blackfin: abstract irq14 lowering in do_irq Split out the optional IRQ14 lowering code to further simplify the asm_do_IRQ() function and keep the ifdef nest under control. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/irqchip.c | 43 ++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 7378440792a..4b5fd36187d 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -104,6 +104,29 @@ static void check_stack_overflow(int irq) static inline void check_stack_overflow(int irq) { } #endif +#ifndef CONFIG_IPIPE +static void maybe_lower_to_irq14(void) +{ + unsigned short pending, other_ints; + + /* + * If we're the only interrupt running (ignoring IRQ15 which + * is for syscalls), lower our priority to IRQ14 so that + * softirqs run at that level. If there's another, + * lower-level interrupt, irq_exit will defer softirqs to + * that. If the interrupt pipeline is enabled, we are already + * running at IRQ14 priority, so we don't need this code. + */ + CSYNC(); + pending = bfin_read_IPEND() & ~0x8000; + other_ints = pending & (pending - 1); + if (other_ints == 0) + lower_to_irq14(); +} +#else +static inline void maybe_lower_to_irq14(void) { } +#endif + /* * do_IRQ handles all hardware IRQs. Decoded IRQs should not * come via this function. Instead, they should provide their @@ -114,9 +137,6 @@ __attribute__((l1_text)) #endif asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) { -#ifndef CONFIG_IPIPE - unsigned short pending, other_ints; -#endif struct pt_regs *old_regs = set_irq_regs(regs); irq_enter(); @@ -132,21 +152,8 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) else generic_handle_irq(irq); -#ifndef CONFIG_IPIPE - /* - * If we're the only interrupt running (ignoring IRQ15 which - * is for syscalls), lower our priority to IRQ14 so that - * softirqs run at that level. If there's another, - * lower-level interrupt, irq_exit will defer softirqs to - * that. If the interrupt pipeline is enabled, we are already - * running at IRQ14 priority, so we don't need this code. - */ - CSYNC(); - pending = bfin_read_IPEND() & ~0x8000; - other_ints = pending & (pending - 1); - if (other_ints == 0) - lower_to_irq14(); -#endif /* !CONFIG_IPIPE */ + maybe_lower_to_irq14(); + irq_exit(); set_irq_regs(old_regs); -- cgit v1.2.3 From 0de4adfb8c9674fa1572b0ff1371acc94b0be901 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 15 Jun 2009 07:39:19 +0000 Subject: Blackfin: fix accidental reset in some boot modes We read the SWRST (Software Reset) register to get at the last reset state, and then we may configure the DOUBLE_FAULT bit to control behavior when a double fault occurs. But if the lower bits of the register is already set (like UART boot mode on a BF54x), we inadvertently make the system reset by writing to the SYSTEM_RESET field at the same time. So make sure the lower 4 bits are always cleared. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 6454babdfaf..b2782eae31e 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -837,7 +837,8 @@ void __init setup_arch(char **cmdline_p) defined(CONFIG_BF538) || defined(CONFIG_BF539) _bfin_swrst = bfin_read_SWRST(); #else - _bfin_swrst = bfin_read_SYSCR(); + /* Clear boot mode field */ + _bfin_swrst = bfin_read_SYSCR() & ~0xf; #endif #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT -- cgit v1.2.3 From dc2c46bb702629d20a3786e10b540c7dcf2c017f Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Mon, 15 Jun 2009 08:23:41 +0000 Subject: Blackfin: bf526-ezbrd: set SPI flash resources to SST device The BF526-EZBRD has a SST SPI flash on it, not a ST Micro. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf527/boards/ezbrd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 9f9c0005dcf..b2f30f06b73 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -237,10 +237,10 @@ static struct flash_platform_data bfin_spi_flash_data = { .name = "m25p80", .parts = bfin_spi_flash_partitions, .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", + .type = "sst25wf040", }; -/* SPI flash chip (m25p64) */ +/* SPI flash chip (sst25wf040) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ .bits_per_word = 8, -- cgit v1.2.3 From 3d15f302d089d0583463745cbece077c1e8294b1 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 15 Jun 2009 16:21:44 +0000 Subject: Blackfin: allow people to select BF51x-0.1 silicon rev Now that 0.1 of the BF51x is coming out, allow people to build for it. Signed-off-by: Mike Frysinger --- arch/blackfin/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 8ea0d942cde..c2c4a62b676 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -274,7 +274,7 @@ config BF_REV_0_0 config BF_REV_0_1 bool "0.1" - depends on (BF52x || (BF54x && !BF54xM)) + depends on (BF51x || BF52x || (BF54x && !BF54xM)) config BF_REV_0_2 bool "0.2" -- cgit v1.2.3 From 06ecc190f3928850cb77c498f745fc8e9a7e2fd7 Mon Sep 17 00:00:00 2001 From: Philippe Gerum Date: Tue, 16 Jun 2009 05:25:37 +0200 Subject: Blackfin: convert interrupt pipeline to irqflags Signed-off-by: Philippe Gerum Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/ipipe_base.h | 30 +++--- arch/blackfin/include/asm/irq.h | 7 -- arch/blackfin/include/asm/irqflags.h | 164 +++++++++++++++++++++++++++++++-- arch/blackfin/include/asm/system.h | 4 +- arch/blackfin/kernel/ipipe.c | 2 +- 5 files changed, 177 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h index 3e8acbd1a3b..490098f532a 100644 --- a/arch/blackfin/include/asm/ipipe_base.h +++ b/arch/blackfin/include/asm/ipipe_base.h @@ -51,23 +51,23 @@ extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ -static inline void __ipipe_stall_root(void) -{ - volatile unsigned long *p = &__ipipe_root_status; - set_bit(0, p); -} +#define __ipipe_stall_root() \ + do { \ + volatile unsigned long *p = &__ipipe_root_status; \ + set_bit(0, p); \ + } while (0) -static inline unsigned long __ipipe_test_and_stall_root(void) -{ - volatile unsigned long *p = &__ipipe_root_status; - return test_and_set_bit(0, p); -} +#define __ipipe_test_and_stall_root() \ + ({ \ + volatile unsigned long *p = &__ipipe_root_status; \ + test_and_set_bit(0, p); \ + }) -static inline unsigned long __ipipe_test_root(void) -{ - const unsigned long *p = &__ipipe_root_status; - return test_bit(0, p); -} +#define __ipipe_test_root() \ + ({ \ + const unsigned long *p = &__ipipe_root_status; \ + test_bit(0, p); \ + }) #endif /* !__ASSEMBLY__ */ diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 9a7f63a83c4..42a15f5ce0d 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h @@ -22,13 +22,6 @@ /* SYS_IRQS and NR_IRQS are defined in */ #include -/* Xenomai IPIPE helpers */ -#define local_irq_restore_hw(x) local_irq_restore(x) -#define local_irq_save_hw(x) local_irq_save(x) -#define local_irq_enable_hw(x) local_irq_enable(x) -#define local_irq_disable_hw(x) local_irq_disable(x) -#define irqs_disabled_hw(x) irqs_disabled(x) - #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) # define NOP_PAD_ANOMALY_05000244 "nop; nop;" #else diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 139cba4651b..9b19a19d9ae 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void) return flags; } +#ifdef CONFIG_IPIPE + +#include +#include + +#ifdef CONFIG_DEBUG_HWERR +# define bfin_no_irqs 0x3f +#else +# define bfin_no_irqs 0x1f +#endif + +#define raw_local_irq_disable() \ + do { \ + ipipe_check_context(ipipe_root_domain); \ + __ipipe_stall_root(); \ + barrier(); \ + } while (0) + +static inline void raw_local_irq_enable(void) +{ + barrier(); + ipipe_check_context(ipipe_root_domain); + __ipipe_unstall_root(); +} + +#define raw_local_save_flags_ptr(x) \ + do { \ + *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ + } while (0) + +#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) + +#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) + +#define raw_local_irq_save_ptr(x) \ + do { \ + *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ + barrier(); \ + } while (0) + +#define raw_local_irq_save(x) \ + do { \ + ipipe_check_context(ipipe_root_domain); \ + raw_local_irq_save_ptr(&(x)); \ + } while (0) + +static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) +{ + /* + * Merge virtual and real interrupt mask bits into a single + * 32bit word. + */ + return (real & ~(1 << 31)) | ((virt != 0) << 31); +} + +static inline int raw_demangle_irq_bits(unsigned long *x) +{ + int virt = (*x & (1 << 31)) != 0; + *x &= ~(1L << 31); + return virt; +} + +static inline void local_irq_disable_hw_notrace(void) +{ + bfin_cli(); +} + +static inline void local_irq_enable_hw_notrace(void) +{ + bfin_sti(bfin_irq_flags); +} + +#define local_save_flags_hw(flags) \ + do { \ + (flags) = bfin_read_IMASK(); \ + } while (0) + +#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0) + +#define irqs_disabled_hw() \ + ({ \ + unsigned long flags; \ + local_save_flags_hw(flags); \ + irqs_disabled_flags_hw(flags); \ + }) + +static inline void local_irq_save_ptr_hw(unsigned long *flags) +{ + *flags = bfin_cli(); +#ifdef CONFIG_DEBUG_HWERR + bfin_sti(0x3f); +#endif +} + +#define local_irq_save_hw_notrace(flags) \ + do { \ + local_irq_save_ptr_hw(&(flags)); \ + } while (0) + +static inline void local_irq_restore_hw_notrace(unsigned long flags) +{ + if (!irqs_disabled_flags_hw(flags)) + local_irq_enable_hw_notrace(); +} + +#ifdef CONFIG_IPIPE_TRACE_IRQSOFF +# define local_irq_disable_hw() \ + do { \ + if (!irqs_disabled_hw()) { \ + local_irq_disable_hw_notrace(); \ + ipipe_trace_begin(0x80000000); \ + } \ + } while (0) +# define local_irq_enable_hw() \ + do { \ + if (irqs_disabled_hw()) { \ + ipipe_trace_end(0x80000000); \ + local_irq_enable_hw_notrace(); \ + } \ + } while (0) +# define local_irq_save_hw(flags) \ + do { \ + local_save_flags_hw(flags); \ + if (!irqs_disabled_flags_hw(flags)) { \ + local_irq_disable_hw_notrace(); \ + ipipe_trace_begin(0x80000001); \ + } \ + } while (0) +# define local_irq_restore_hw(flags) \ + do { \ + if (!irqs_disabled_flags_hw(flags)) { \ + ipipe_trace_end(0x80000001); \ + local_irq_enable_hw_notrace(); \ + } \ + } while (0) +#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ +# define local_irq_disable_hw() local_irq_disable_hw_notrace() +# define local_irq_enable_hw() local_irq_enable_hw_notrace() +# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags) +# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags) +#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ + +#else /* CONFIG_IPIPE */ + static inline void raw_local_irq_disable(void) { bfin_cli(); @@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void) #define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) -static inline void raw_local_irq_restore(unsigned long flags) -{ - if (!raw_irqs_disabled_flags(flags)) - raw_local_irq_enable(); -} - static inline unsigned long __raw_local_irq_save(void) { unsigned long flags = bfin_cli(); @@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void) } #define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) +#define local_irq_save_hw(flags) raw_local_irq_save(flags) +#define local_irq_restore_hw(flags) raw_local_irq_restore(flags) +#define local_irq_enable_hw() raw_local_irq_enable() +#define local_irq_disable_hw() raw_local_irq_disable() +#define irqs_disabled_hw() irqs_disabled() + +#endif /* !CONFIG_IPIPE */ + +static inline void raw_local_irq_restore(unsigned long flags) +{ + if (!raw_irqs_disabled_flags(flags)) + raw_local_irq_enable(); +} + #endif diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 294dbda2416..85e8f16cf8c 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -135,11 +135,13 @@ struct __xchg_dummy { }; #define __xg(x) ((volatile struct __xchg_dummy *)(x)) +#include + static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { unsigned long tmp = 0; - unsigned long flags = 0; + unsigned long flags; local_irq_save_hw(flags); diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index d8cde1fc5cb..2b979edee14 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c @@ -52,7 +52,7 @@ EXPORT_SYMBOL(__ipipe_freq_scale); atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; -unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags; +unsigned long __ipipe_irq_lvmask = bfin_no_irqs; EXPORT_SYMBOL(__ipipe_irq_lvmask); static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) -- cgit v1.2.3 From a40494a62a11dbaf326397aa94b2018ead09884d Mon Sep 17 00:00:00 2001 From: Philippe Gerum Date: Tue, 16 Jun 2009 05:25:42 +0200 Subject: Blackfin: allow CONFIG_TICKSOURCE_GPTMR0 with interrupt pipeline Signed-off-by: Philippe Gerum Signed-off-by: Mike Frysinger --- arch/blackfin/Kconfig | 1 - arch/blackfin/include/asm/ipipe.h | 7 ++++- arch/blackfin/mach-common/ints-priority.c | 47 +++++++++++++++---------------- 3 files changed, 28 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c2c4a62b676..8140a2fc8bb 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -623,7 +623,6 @@ choice config TICKSOURCE_GPTMR0 bool "Gptimer0 (SCLK domain)" select BFIN_GPTIMERS - depends on !IPIPE config TICKSOURCE_CORETMR bool "Core timer (CCLK domain)" diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index bbe1c3726b6..ffa5e60faa9 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h @@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void); int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); -#ifdef CONFIG_GENERIC_CLOCKEVENTS +#ifdef CONFIG_TICKSOURCE_CORETMR #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR #else @@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); #define ipipe_init_irq_threads() do { } while (0) #define ipipe_start_irq_thread(irq, desc) 0 +#ifndef CONFIG_TICKSOURCE_GPTMR0 #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR +#else +#define IRQ_SYSTMR IRQ_TIMER0 +#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 +#endif #define __ipipe_root_tick_p(regs) 1 diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index af70f09acd5..b42150190d0 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -1052,35 +1052,34 @@ int __init init_arch_irq(void) set_irq_chained_handler(irq, bfin_demux_error_irq); break; #endif -#if defined(CONFIG_TICKSOURCE_GPTMR0) - case IRQ_TIMER0: - set_irq_handler(irq, handle_percpu_irq); - break; -#endif #ifdef CONFIG_SMP case IRQ_SUPPLE_0: case IRQ_SUPPLE_1: set_irq_handler(irq, handle_percpu_irq); break; #endif - default: #ifdef CONFIG_IPIPE - /* - * We want internal interrupt sources to be - * masked, because ISRs may trigger interrupts - * recursively (e.g. DMA), but interrupts are - * _not_ masked at CPU level. So let's handle - * most of them as level interrupts, except - * the timer interrupt which is special. - */ - if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) - set_irq_handler(irq, handle_simple_irq); - else - set_irq_handler(irq, handle_level_irq); +#ifndef CONFIG_TICKSOURCE_CORETMR + case IRQ_TIMER0: + set_irq_handler(irq, handle_simple_irq); + break; +#endif /* !CONFIG_TICKSOURCE_CORETMR */ + case IRQ_CORETMR: + set_irq_handler(irq, handle_simple_irq); + break; + default: + set_irq_handler(irq, handle_level_irq); + break; #else /* !CONFIG_IPIPE */ +#ifdef CONFIG_TICKSOURCE_GPTMR0 + case IRQ_TIMER0: + set_irq_handler(irq, handle_percpu_irq); + break; +#endif /* CONFIG_TICKSOURCE_GPTMR0 */ + default: set_irq_handler(irq, handle_simple_irq); -#endif /* !CONFIG_IPIPE */ break; +#endif /* !CONFIG_IPIPE */ } } @@ -1224,15 +1223,14 @@ __attribute__((l1_text)) asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) { struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); - struct ipipe_domain *this_domain = ipipe_current_domain; + struct ipipe_domain *this_domain = __ipipe_current_domain; struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; int irq, s; - if (likely(vec == EVT_IVTMR_P)) { + if (likely(vec == EVT_IVTMR_P)) irq = IRQ_CORETMR; - - } else { + else { #if defined(SIC_ISR0) || defined(SICA_ISR0) unsigned long sic_status[3]; @@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) break; } #endif - irq = ivg->irqno; } if (irq == IRQ_SYSTMR) { -#ifndef CONFIG_GENERIC_CLOCKEVENTS +#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ #endif /* This is basically what we need from the register frame. */ -- cgit v1.2.3 From 5ba3b249c9e08100b0822f17276348b3447d6ee3 Mon Sep 17 00:00:00 2001 From: Philippe Gerum Date: Tue, 16 Jun 2009 05:25:50 +0200 Subject: Blackfin: remove obsolete mcount support from I-pipe code Signed-off-by: Philippe Gerum Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/Makefile | 1 - arch/blackfin/kernel/ipipe.c | 5 ---- arch/blackfin/kernel/mcount.S | 70 ------------------------------------------- 3 files changed, 76 deletions(-) delete mode 100644 arch/blackfin/kernel/mcount.S (limited to 'arch') diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 3731088e181..141d9281e4b 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o CFLAGS_REMOVE_ftrace.o = -pg obj-$(CONFIG_IPIPE) += ipipe.o -obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o obj-$(CONFIG_CPLB_INFO) += cplbinfo.o obj-$(CONFIG_MODULES) += module.o diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index 2b979edee14..b8d22034b9a 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c @@ -342,8 +342,3 @@ void ___ipipe_sync_pipeline(unsigned long syncmask) } EXPORT_SYMBOL(show_stack); - -#ifdef CONFIG_IPIPE_TRACE_MCOUNT -void notrace _mcount(void); -EXPORT_SYMBOL(_mcount); -#endif /* CONFIG_IPIPE_TRACE_MCOUNT */ diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S deleted file mode 100644 index edcfb3865f4..00000000000 --- a/arch/blackfin/kernel/mcount.S +++ /dev/null @@ -1,70 +0,0 @@ -/* - * linux/arch/blackfin/mcount.S - * - * Copyright (C) 2006 Analog Devices Inc. - * - * 2007/04/12 Save index, length, modify and base registers. --rpm - */ - -#include -#include - -.text - -.align 4 /* just in case */ - -ENTRY(__mcount) - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = ( r7:0, p5:0 ); - [--sp] = ASTAT; - - p1.L = _ipipe_trace_enable; - p1.H = _ipipe_trace_enable; - r7 = [p1]; - CC = r7 == 0; - if CC jump out; - link 0x10; - r0 = 0x0; - [sp + 0xc] = r0; /* v */ - r0 = 0x0; /* type: IPIPE_TRACE_FN */ - r1 = rets; - p0 = [fp]; /* p0: Prior FP */ - r2 = [p0 + 4]; /* r2: Prior RETS */ - call ___ipipe_trace; - unlink; -out: - ASTAT = [sp++]; - ( r7:0, p5:0 ) = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - rts; -ENDPROC(__mcount) -- cgit v1.2.3 From 7c039a90f02c3fdcab8d3ca170c05ad37014189e Mon Sep 17 00:00:00 2001 From: Philippe Gerum Date: Tue, 16 Jun 2009 05:25:54 +0200 Subject: Blackfin: update I-pipe patch level Signed-off-by: Philippe Gerum Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/ipipe.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index ffa5e60faa9..87ba9ad399c 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h @@ -35,9 +35,9 @@ #include #include -#define IPIPE_ARCH_STRING "1.10-00" +#define IPIPE_ARCH_STRING "1.11-00" #define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 10 +#define IPIPE_MINOR_NUMBER 11 #define IPIPE_PATCH_NUMBER 0 #ifdef CONFIG_SMP -- cgit v1.2.3 From 41ba653f24a39a0e6a4afe9b2763a95a57e042c2 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Tue, 16 Jun 2009 09:48:33 +0000 Subject: Blackfin: decouple unrelated cache settings to get exact behavior The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang Signed-off-by: Mike Frysinger --- arch/blackfin/Kconfig | 57 +++++++++++++------ arch/blackfin/include/asm/cache.h | 4 +- arch/blackfin/include/asm/cacheflush.h | 10 ++-- arch/blackfin/include/asm/cplb.h | 32 ++++++----- arch/blackfin/kernel/cplb-mpu/cplbinit.c | 10 ++-- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 36 ++++++++---- arch/blackfin/kernel/setup.c | 96 ++++++++++++++++++++++++++------ arch/blackfin/mach-common/arch_checks.c | 4 +- arch/blackfin/mach-common/cpufreq.c | 2 +- arch/blackfin/mach-common/pm.c | 4 +- arch/blackfin/mm/init.c | 2 +- 11 files changed, 176 insertions(+), 81 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 8140a2fc8bb..220635a1ebd 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -907,23 +907,41 @@ endchoice comment "Cache Support" + config BFIN_ICACHE bool "Enable ICACHE" + default y +config BFIN_ICACHE_LOCK + bool "Enable Instruction Cache Locking" + depends on BFIN_ICACHE + default n +config BFIN_EXTMEM_ICACHEABLE + bool "Enable ICACHE for external memory" + depends on BFIN_ICACHE + default y +config BFIN_L2_ICACHEABLE + bool "Enable ICACHE for L2 SRAM" + depends on BFIN_ICACHE + depends on BF54x || BF561 + default n + config BFIN_DCACHE bool "Enable DCACHE" + default y config BFIN_DCACHE_BANKA bool "Enable only 16k BankA DCACHE - BankB is SRAM" depends on BFIN_DCACHE && !BF531 default n -config BFIN_ICACHE_LOCK - bool "Enable Instruction Cache Locking" - -choice - prompt "External memory cache policy" +config BFIN_EXTMEM_DCACHEABLE + bool "Enable DCACHE for external memory" depends on BFIN_DCACHE - default BFIN_WB if !SMP - default BFIN_WT if SMP -config BFIN_WB + default y +choice + prompt "External memory DCACHE policy" + depends on BFIN_EXTMEM_DCACHEABLE + default BFIN_EXTMEM_WRITEBACK if !SMP + default BFIN_EXTMEM_WRITETHROUGH if SMP +config BFIN_EXTMEM_WRITEBACK bool "Write back" depends on !SMP help @@ -941,7 +959,7 @@ config BFIN_WB If you are unsure of the options and you want to be safe, then go with Write Through. -config BFIN_WT +config BFIN_EXTMEM_WRITETHROUGH bool "Write through" help Write Back Policy: @@ -960,23 +978,26 @@ config BFIN_WT endchoice +config BFIN_L2_DCACHEABLE + bool "Enable DCACHE for L2 SRAM" + depends on BFIN_DCACHE + depends on BF54x || BF561 + default n choice - prompt "L2 SRAM cache policy" - depends on (BF54x || BF561) - default BFIN_L2_WT -config BFIN_L2_WB + prompt "L2 SRAM DCACHE policy" + depends on BFIN_L2_DCACHEABLE + default BFIN_L2_WRITEBACK +config BFIN_L2_WRITEBACK bool "Write back" depends on !SMP -config BFIN_L2_WT +config BFIN_L2_WRITETHROUGH bool "Write through" depends on !SMP - -config BFIN_L2_NOT_CACHED - bool "Not cached" - endchoice + +comment "Memory Protection Unit" config MPU bool "Enable the memory protection unit (EXPERIMENTAL)" default n diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 2ef669ed922..477050ad5c5 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -35,10 +35,10 @@ #if defined(CONFIG_SMP) && \ !defined(CONFIG_BFIN_CACHE_COHERENT) -# if defined(CONFIG_BFIN_ICACHE) +# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) # define __ARCH_SYNC_CORE_ICACHE # endif -# if defined(CONFIG_BFIN_DCACHE) +# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) # define __ARCH_SYNC_CORE_DCACHE # endif #ifndef __ASSEMBLY__ diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 5c17dee53b5..7e55549e180 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void); static inline void flush_icache_range(unsigned start, unsigned end) { -#if defined(CONFIG_BFIN_WB) +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) blackfin_dcache_flush_range(start, end); #endif @@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \ #else # define invalidate_dcache_range(start,end) do { } while (0) #endif -#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) -# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) +# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) #else # define flush_dcache_range(start,end) do { } while (0) # define flush_dcache_page(page) do { } while (0) @@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on; static inline int bfin_addr_dcacheable(unsigned long addr) { -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE if (addr < (_ramend - DMA_UNCACHED_REGION)) return 1; #endif @@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr) addr >= _ramend && addr < physical_mem_end) return 1; -#ifndef CONFIG_BFIN_L2_NOT_CACHED +#ifdef CONFIG_BFIN_L2_DCACHEABLE if (addr >= L2_START && addr < L2_START + L2_LENGTH) return 1; #endif diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index a75a6a9f094..c5dacf8f8cf 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -37,8 +37,6 @@ #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) -/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ - #if ANOMALY_05000158 #define ANOMALY_05000158_WORKAROUND 0x200 #else @@ -47,10 +45,12 @@ #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#ifdef CONFIG_BFIN_WB /*Write Back Policy */ +#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) -#else /*Write Through */ +#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +#else +#define SDRAM_DGENERIC (CPLB_COMMON) #endif #define SDRAM_DNON_CHBL (CPLB_COMMON) @@ -61,21 +61,23 @@ #ifdef CONFIG_SMP #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (CPLB_COMMON) -#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) +#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) +#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) #else #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (SDRAM_IGENERIC) - -# if defined(CONFIG_BFIN_L2_WB) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) -# elif defined(CONFIG_BFIN_L2_WT) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) -# elif defined(CONFIG_BFIN_L2_NOT_CACHED) -# define L2_DMEMORY (CPLB_COMMON) +# if defined(CONFIG_BFIN_L2_ICACHEABLE) +# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# else +# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# endif + +# if defined(CONFIG_BFIN_L2_WRITEBACK) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) +# elif defined(CONFIG_BFIN_L2_WRITETHROUGH) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) # else -# define L2_DMEMORY (0) +# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) # endif #endif /* CONFIG_SMP */ diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index c006a44527b..36193eed9a1 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); -#ifdef CONFIG_BFIN_ICACHE +#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #endif -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE d_cache = CPLB_L1_CHBL; -#ifdef CONFIG_BFIN_WT +#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH d_cache |= CPLB_L1_AOW | CPLB_WT; #endif #endif @@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) /* Cover L2 memory */ #if L2_LENGTH > 0 dcplb_tbl[cpu][i_d].addr = L2_START; - dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; + dcplb_tbl[cpu][i_d++].data = L2_DMEMORY; icplb_tbl[cpu][i_i].addr = L2_START; - icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; + icplb_tbl[cpu][i_i++].data = L2_IMEMORY; #endif first_mask_dcplb = i_d; diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 784923e52a9..bcdfe9b0b71 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu) nr_dcplb_miss[cpu]++; d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE if (bfin_addr_dcacheable(addr)) { d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#ifdef CONFIG_BFIN_WT +# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH d_data |= CPLB_L1_AOW | CPLB_WT; -#endif +# endif } #endif - if (addr >= physical_mem_end) { + + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + d_data = L2_DMEMORY; + } else if (addr >= physical_mem_end) { if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && (status & FAULT_USERSUPV)) { addr &= ~0x3fffff; @@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu) i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_ICACHE +#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE /* * Normal RAM, and possibly the reserved memory area, are * cacheable. @@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu) i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #endif - if (addr >= physical_mem_end) { + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + i_data = L2_IMEMORY; + } else if (addr >= physical_mem_end) { if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & FAULT_USERSUPV)) { addr &= ~(1 * 1024 * 1024 - 1); @@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) local_irq_save_hw(flags); current_rwx_mask[cpu] = masks; - d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_DCACHE - d_data |= CPLB_L1_CHBL; -#ifdef CONFIG_BFIN_WT - d_data |= CPLB_L1_AOW | CPLB_WT; -#endif + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + d_data = L2_DMEMORY; + } else { + d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE + d_data |= CPLB_L1_CHBL; +# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH + d_data |= CPLB_L1_AOW | CPLB_WT; +# endif #endif + } disable_dcplb(); for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index b2782eae31e..8d789282013 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) */ #ifdef CONFIG_BFIN_ICACHE printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); + printk(KERN_INFO " External memory:" +# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE + " cacheable" +# else + " uncacheable" +# endif + " in instruction cache\n"); + if (L2_LENGTH) + printk(KERN_INFO " L2 SRAM :" +# ifdef CONFIG_BFIN_L2_ICACHEABLE + " cacheable" +# else + " uncacheable" +# endif + " in instruction cache\n"); + +#else + printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); #endif + #ifdef CONFIG_BFIN_DCACHE - printk(KERN_INFO "Data Cache Enabled for CPU%u" -# if defined CONFIG_BFIN_WB - " (write-back)" -# elif defined CONFIG_BFIN_WT - " (write-through)" + printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); + printk(KERN_INFO " External memory:" +# if defined CONFIG_BFIN_EXTMEM_WRITEBACK + " cacheable (write-back)" +# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH + " cacheable (write-through)" +# else + " uncacheable" +# endif + " in data cache\n"); + if (L2_LENGTH) + printk(KERN_INFO " L2 SRAM :" +# if defined CONFIG_BFIN_L2_WRITEBACK + " cacheable (write-back)" +# elif defined CONFIG_BFIN_L2_WRITETHROUGH + " cacheable (write-through)" +# else + " uncacheable" # endif - "\n", cpu); + " in data cache\n"); +#else + printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); #endif } @@ -516,7 +550,7 @@ static __init void memory_setup(void) && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) mtd_size = PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); -# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +# if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) /* Due to a Hardware Anomaly we need to limit the size of usable * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * 05000263 - Hardware loop corrupted when taking an ICPLB exception @@ -544,7 +578,7 @@ static __init void memory_setup(void) dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); #endif /* CONFIG_MTD_UCLINUX */ -#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) /* Due to a Hardware Anomaly we need to limit the size of usable * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * 05000263 - Hardware loop corrupted when taking an ICPLB exception @@ -1158,16 +1192,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) icache_size = 0; seq_printf(m, "cache size\t: %d KB(L1 icache) " - "%d KB(L1 dcache%s) %d KB(L2 cache)\n", - icache_size, dcache_size, -#if defined CONFIG_BFIN_WB - "-wb" -#elif defined CONFIG_BFIN_WT - "-wt" -#endif - "", 0); - + "%d KB(L1 dcache) %d KB(L2 cache)\n", + icache_size, dcache_size, 0); seq_printf(m, "%s\n", cache); + seq_printf(m, "external memory\t: " +#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) + "cacheable" +#else + "uncacheable" +#endif + " in instruction cache\n"); + seq_printf(m, "external memory\t: " +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) + "cacheable (write-back)" +#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) + "cacheable (write-through)" +#else + "uncacheable" +#endif + " in data cache\n"); if (icache_size) seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", @@ -1240,8 +1283,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_num != num_possible_cpus() - 1) return 0; - if (L2_LENGTH) + if (L2_LENGTH) { seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); + seq_printf(m, "L2 SRAM\t\t: " +#if defined(CONFIG_BFIN_L2_ICACHEABLE) + "cacheable" +#else + "uncacheable" +#endif + " in instruction cache\n"); + seq_printf(m, "L2 SRAM\t\t: " +#if defined(CONFIG_BFIN_L2_WRITEBACK) + "cacheable (write-back)" +#elif defined(CONFIG_BFIN_L2_WRITETHROUGH) + "cacheable (write-through)" +#else + "uncacheable" +#endif + " in data cache\n"); + } seq_printf(m, "board name\t: %s\n", bfin_board_name); seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index da93d920716..5998d8632a7 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -74,7 +74,7 @@ /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ #if ANOMALY_05000220 && \ - ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ - (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) + ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ + (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. #endif diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 70e3411f558..85c65808327 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) sclk = get_sclk() / 1000; #if ANOMALY_05000273 || ANOMALY_05000274 || \ - (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) + (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) min_cclk = sclk * 2; #else min_cclk = sclk; diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index bce5a84be49..9e7e27b7fc8 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr) return 0; } -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) static void flushinv_all_dcache(void) { u32 way, bank, subbank, set; @@ -175,7 +175,7 @@ static inline void dcache_disable(void) #ifdef CONFIG_BFIN_DCACHE unsigned long ctrl; -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) flushinv_all_dcache(); #endif SSYNC(); diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 014a55abd09..68bd0bd680c 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -160,7 +160,7 @@ void __init mem_init(void) /* do not count in kernel image between _rambase and _ramstart */ reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; -#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; #endif -- cgit v1.2.3 From 841a534367c2cfdc325a11958c51406da17686c7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 17 Jun 2009 07:11:42 +0000 Subject: Blackfin: update defconfigs Signed-off-by: Mike Frysinger --- arch/blackfin/configs/BF518F-EZBRD_defconfig | 24 +++++++++++++++--------- arch/blackfin/configs/BF526-EZBRD_defconfig | 22 ++++++++++++---------- arch/blackfin/configs/BF527-EZKIT_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/BF533-EZKIT_defconfig | 25 +++++++++++++++++-------- arch/blackfin/configs/BF533-STAMP_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/BF537-STAMP_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/BF538-EZKIT_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/BF548-EZKIT_defconfig | 27 ++++++++++++++++----------- arch/blackfin/configs/BF561-EZKIT_defconfig | 27 ++++++++++++++++----------- arch/blackfin/configs/BlackStamp_defconfig | 12 +++++++++--- arch/blackfin/configs/CM-BF527_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/CM-BF533_defconfig | 23 ++++++++++++++--------- arch/blackfin/configs/CM-BF537E_defconfig | 22 ++++++++++++++-------- arch/blackfin/configs/CM-BF537U_defconfig | 23 ++++++++++++++--------- arch/blackfin/configs/CM-BF548_defconfig | 25 ++++++++++++++++--------- arch/blackfin/configs/CM-BF561_defconfig | 25 ++++++++++++++++--------- arch/blackfin/configs/H8606_defconfig | 14 ++++++++++---- arch/blackfin/configs/PNAV-10_defconfig | 20 +++++++++++++------- arch/blackfin/configs/SRV1_defconfig | 14 ++++++++++---- arch/blackfin/configs/TCM-BF537_defconfig | 14 ++++++++++---- 20 files changed, 272 insertions(+), 155 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index baec1337f28..dcfb4889559 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -326,11 +326,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -413,11 +419,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -916,7 +922,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_SDHCI is not set CONFIG_SDH_BFIN=m CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y -CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ=y +# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set # CONFIG_MMC_SPI is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1147,7 +1153,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index c06262e41f7..48a3a7a9099 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -331,16 +331,18 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_MPU is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set # -# Asynchonous Memory Configuration +# Memory Protection Unit # +# CONFIG_MPU is not set # # EBIU_AMGCTL Global Control @@ -418,11 +420,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1424,7 +1426,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index e9175c608aa..dd8352791da 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -331,11 +331,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -418,11 +424,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1505,7 +1511,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 5aa63bafdd6..4c044805cb5 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -289,15 +289,24 @@ CONFIG_BFIN_GPTIMERS=m CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set +# +# Cache Support +# # # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -391,11 +400,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1052,7 +1061,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index fed25329e13..c99bbcd09a6 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -293,11 +293,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -391,11 +397,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1216,7 +1222,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index f9ac20d5579..092ffda80e6 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -300,11 +300,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -399,11 +405,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1269,7 +1275,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index ee98e227b88..fa698a89f6f 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -311,11 +311,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -398,11 +404,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1203,7 +1209,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index deeabef8ab8..b3d3cab81cf 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -366,14 +366,19 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_BFIN_L2_WB is not set -CONFIG_BFIN_L2_WT=y -# CONFIG_BFIN_L2_NOT_CACHED is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -459,11 +464,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1606,7 +1611,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index dcfbe2e2931..0313cd1d982 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -331,14 +331,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_BFIN_L2_WB is not set -CONFIG_BFIN_L2_WT=y -# CONFIG_BFIN_L2_NOT_CACHED is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -425,11 +430,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1044,7 +1049,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 174c578b8ec..5d944ffd4ab 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig @@ -285,11 +285,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index e17875e8abe..648a31d01bf 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig @@ -329,11 +329,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -417,11 +423,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1246,7 +1252,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index fafd95e84b2..ae665b93b87 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -262,12 +262,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -353,10 +358,10 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -873,7 +878,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index e73aa5af58b..d74b6f4db35 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -297,11 +297,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -383,11 +389,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -861,7 +867,7 @@ CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 80211303f6b..7fc8dfa1719 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -270,12 +270,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -361,10 +366,10 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -901,7 +906,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index dd815f0d151..acca4e51a45 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -333,12 +333,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -428,11 +435,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1334,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 16c198bd40c..bae4ee6e68b 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -308,12 +308,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -395,11 +402,11 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -837,7 +844,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 6b4c1a98238..a6a7c8ede70 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -258,12 +258,18 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -CONFIG_BFIN_ICACHE_LOCK=y -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# +# CONFIG_MPU is not set # # Asynchonous Memory Configuration diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 09701f907e9..ff377fae061 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig @@ -295,11 +295,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -382,11 +388,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index ec84a53daae..814f9cacf40 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig @@ -279,12 +279,18 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# +# CONFIG_MPU is not set # # Asynchonous Memory Configuration diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig index 6e2796240fd..375e75a27ab 100644 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ b/arch/blackfin/configs/TCM-BF537_defconfig @@ -287,11 +287,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -709,7 +715,7 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set -- cgit v1.2.3 From 985895bd8d1e41079b41da32cdc57876a4a74126 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Wed, 17 Jun 2009 08:12:54 -0400 Subject: Blackfin: stick the CPU name into boot image name Rather than use "Linux" in the boot image name (as this is redundant -- the image type is already set to "linux"), use the CPU name. This makes it fairly obvious when a wrong image is accidentally booted. Otherwise there is no kernel output and you waste time scratching your head wondering wtf just happened. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/boot/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile index 3ab6f23561d..fd9ccc5fea1 100644 --- a/arch/blackfin/boot/Makefile +++ b/arch/blackfin/boot/Makefile @@ -13,7 +13,7 @@ extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma quiet_cmd_uimage = UIMAGE $@ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ - -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ + -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ -d $< $@ -- cgit v1.2.3 From fa48f84a8cc722ca48b32fa0c338b6c3b358717d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 17 Jun 2009 11:25:06 -0400 Subject: Blackfin: unify memory map headers Many aspects of the Blackfin memory map is exactly the same across all variants. Rather than copy and paste all of these duplicated values in each header, unify all of these into the common Blackfin memory map header file. In the process, push down BF561 SMP specific stuff to the BF561 specific header to keep the noise down. Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/blackfin.h | 1 + arch/blackfin/include/asm/mem_map.h | 97 ++++++++++++------------ arch/blackfin/mach-bf518/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf518/include/mach/mem_map.h | 56 +++----------- arch/blackfin/mach-bf527/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf527/include/mach/mem_map.h | 56 +++----------- arch/blackfin/mach-bf533/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf533/include/mach/mem_map.h | 56 +++----------- arch/blackfin/mach-bf537/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf537/include/mach/mem_map.h | 56 +++----------- arch/blackfin/mach-bf538/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf538/include/mach/mem_map.h | 57 +++----------- arch/blackfin/mach-bf548/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf548/include/mach/mem_map.h | 51 +++---------- arch/blackfin/mach-bf561/include/mach/blackfin.h | 1 - arch/blackfin/mach-bf561/include/mach/mem_map.h | 58 ++++++++++---- 16 files changed, 145 insertions(+), 350 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h index 8bb2cb13975..4d443958339 100644 --- a/arch/blackfin/include/asm/blackfin.h +++ b/arch/blackfin/include/asm/blackfin.h @@ -86,6 +86,7 @@ static inline void CSYNC(void) #endif /* __ASSEMBLY__ */ +#include #include #include diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h index e92b31051bb..5e21627c9ba 100644 --- a/arch/blackfin/include/asm/mem_map.h +++ b/arch/blackfin/include/asm/mem_map.h @@ -1,87 +1,84 @@ /* - * mem_map.h - * Common header file for blackfin family of processors. + * Common Blackfin memory map * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_H_ -#define _MEM_MAP_H_ +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ #include -#ifndef __ASSEMBLY__ +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif -#ifdef CONFIG_SMP -static inline ulong get_l1_scratch_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; -} -static inline ulong get_l1_code_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; -} -static inline ulong get_l1_data_a_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; -} -static inline ulong get_l1_data_b_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; -} +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SCRATCH_START +# define L1_SCRATCH_START 0xFFB00000 +# define L1_SCRATCH_LENGTH 0x1000 +#endif -static inline ulong get_l1_scratch_start(void) -{ - return get_l1_scratch_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_code_start(void) -{ - return get_l1_code_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_data_a_start(void) -{ - return get_l1_data_a_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_data_b_start(void) -{ - return get_l1_data_b_start_cpu(blackfin_core_id()); -} +/* Most parts lack on-chip L2 SRAM */ +#ifndef L2_START +# define L2_START 0 +# define L2_LENGTH 0 +#endif + +/* Most parts lack on-chip L1 ROM */ +#ifndef L1_ROM_START +# define L1_ROM_START 0 +# define L1_ROM_LENGTH 0 +#endif + +/* Allow wonky SMP ports to override this */ +#ifndef GET_PDA_SAFE +# define GET_PDA_SAFE(preg) \ + preg.l = _cpu_pda; \ + preg.h = _cpu_pda; +# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) -#else /* !CONFIG_SMP */ +# ifndef __ASSEMBLY__ -static inline ulong get_l1_scratch_start_cpu(int cpu) +static inline unsigned long get_l1_scratch_start_cpu(int cpu) { return L1_SCRATCH_START; } -static inline ulong get_l1_code_start_cpu(int cpu) +static inline unsigned long get_l1_code_start_cpu(int cpu) { return L1_CODE_START; } -static inline ulong get_l1_data_a_start_cpu(int cpu) +static inline unsigned long get_l1_data_a_start_cpu(int cpu) { return L1_DATA_A_START; } -static inline ulong get_l1_data_b_start_cpu(int cpu) +static inline unsigned long get_l1_data_b_start_cpu(int cpu) { return L1_DATA_B_START; } -static inline ulong get_l1_scratch_start(void) +static inline unsigned long get_l1_scratch_start(void) { return get_l1_scratch_start_cpu(0); } -static inline ulong get_l1_code_start(void) +static inline unsigned long get_l1_code_start(void) { return get_l1_code_start_cpu(0); } -static inline ulong get_l1_data_a_start(void) +static inline unsigned long get_l1_data_a_start(void) { return get_l1_data_a_start_cpu(0); } -static inline ulong get_l1_data_b_start(void) +static inline unsigned long get_l1_data_b_start(void) { return get_l1_data_b_start_cpu(0); } -#endif /* CONFIG_SMP */ -#endif /* __ASSEMBLY__ */ +# endif /* __ASSEMBLY__ */ +#endif /* !GET_PDA_SAFE */ -#endif /* _MEM_MAP_H_ */ +#endif diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index 267bb7c8bfb..e8e14c2769e 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf518.h" -#include "mem_map.h" #include "defBF512.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h index 62bcc781bfa..3c6777cb353 100644 --- a/arch/blackfin/mach-bf518/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf518/mem_map.h - * based on: include/asm-blackfin/mach-bf527/mem_map.h - * author: Bryan Wu + * BF51x memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF518/6/4/2 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_518_H_ -#define _MEM_MAP_518_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -89,20 +67,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE */ -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_518_H_ */ +#endif diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h index 417abcd61f4..03665a8e16b 100644 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf527.h" -#include "mem_map.h" #include "defBF522.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h index 019e0017ad8..d96e894afd2 100644 --- a/arch/blackfin/mach-bf527/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf527/mem_map.h - * based on: include/asm-blackfin/mach-bf537/mem_map.h - * author: Michael Hennerich (michael.hennerich@analog.com) + * BF52x memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF527/5/2 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_527_H_ -#define _MEM_MAP_527_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -89,20 +67,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE */ -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_527_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index 045184f81a2..39aa175f19f 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h @@ -34,7 +34,6 @@ #define BF533_FAMILY #include "bf533.h" -#include "mem_map.h" #include "defBF532.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h index fc33b7cb993..197af1a398a 100644 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf533/mem_map.h - * Based on: - * Author: + * BF533 memory map * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_533_H_ -#define _MEM_MAP_533_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -158,20 +136,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index 7d6069c886f..f5e5015ad83 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -35,7 +35,6 @@ #define BF537_FAMILY #include "bf537.h" -#include "mem_map.h" #include "defBF534.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h index f9010c4b4bf..942f08de306 100644 --- a/arch/blackfin/mach-bf537/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf537/mem_map.h - * based on: - * author: + * BF537 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_537_H_ -#define _MEM_MAP_537_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -166,20 +144,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_537_H_ */ +#endif diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index 6f628353dde..9496196ac16 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h @@ -35,7 +35,6 @@ #define BF538_FAMILY #include "bf538.h" -#include "mem_map.h" #include "defBF539.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h index 76811966690..aff00f453e9 100644 --- a/arch/blackfin/mach-bf538/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf538/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf538/mem_map.h - * Based on: - * Author: + * BF538 memory map * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_538_H_ -#define _MEM_MAP_538_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -93,21 +71,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ - -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_538_H_ */ +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index cf6c1500222..6b97396d817 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf548.h" -#include "mem_map.h" #include "anomaly.h" #ifdef CONFIG_BF542 diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h index 70b9c119402..caac2dfb41e 100644 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf548/mem_map.h - * based on: - * author: + * BF548 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_548_H_ -#define _MEM_MAP_548_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -103,15 +81,4 @@ # define L2_LENGTH 0x20000 #endif -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif/* _MEM_MAP_548_H_ */ +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index f79f6626b7e..8be31358ef8 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -34,7 +34,6 @@ #define BF561_FAMILY #include "bf561.h" -#include "mem_map.h" #include "defBF561.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index 419dffdc96e..a63e15c86d9 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -1,13 +1,16 @@ /* - * Memory MAP - * Common header file for blackfin BF561 of processors. + * BF561 memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_561_H_ -#define _MEM_MAP_561_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -82,9 +85,6 @@ #define COREA_L1_SCRATCH_START 0xFFB00000 #define COREB_L1_SCRATCH_START 0xFF700000 -#define L1_SCRATCH_START COREA_L1_SCRATCH_START -#define L1_SCRATCH_LENGTH 0x1000 - #ifdef __ASSEMBLY__ /* @@ -155,14 +155,42 @@ dreg = ROT dreg BY -1; \ dreg = CC; -#else -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; +static inline unsigned long get_l1_scratch_start_cpu(int cpu) +{ + return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; +} +static inline unsigned long get_l1_code_start_cpu(int cpu) +{ + return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; +} +static inline unsigned long get_l1_data_a_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; +} +static inline unsigned long get_l1_data_b_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; +} + +static inline unsigned long get_l1_scratch_start(void) +{ + return get_l1_scratch_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_code_start(void) +{ + return get_l1_code_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_a_start(void) +{ + return get_l1_data_a_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_b_start(void) +{ + return get_l1_data_b_start_cpu(blackfin_core_id()); +} -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) #endif /* CONFIG_SMP */ #endif /* __ASSEMBLY__ */ -#endif /* _MEM_MAP_533_H_ */ +#endif -- cgit v1.2.3 From 8f580f7c82ed9edeb3629568aabcde2caff3f236 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Thu, 18 Jun 2009 04:21:39 +0000 Subject: Blackfin: fix typo in TRAS define in mem_init.h header We defined SDRAM_tRAS to TRAS_4, but then wrongly defined SDRAM_tRAS_num to 3. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/mem_init.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 61f7487fbf1..fc164b35a9c 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -59,7 +59,7 @@ #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 #define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 3 +#define SDRAM_tRAS_num 4 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 #endif -- cgit v1.2.3 From ee48efb5dc45aeb9786dea6469d3e1bea5105036 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Thu, 18 Jun 2009 04:32:04 +0000 Subject: Blackfin: bf526-ezbrd: handle different SDRAM chips The BF526-EZBRD changed SDRAM chips between board revisions, so create a timing table that can accommodate both. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/Kconfig | 7 ++- arch/blackfin/include/asm/mem_init.h | 86 ++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 220635a1ebd..384f7cd6b41 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC32M16A2TG_75 bool - depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) + depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) default y config MEM_MT48LC32M8A2_75 @@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75 depends on (BFIN518F_EZBRD) default y +config MEM_MT48H32M16LFCJ_75 + bool + depends on (BFIN526_EZBRD) + default y + source "arch/blackfin/mach-bf518/Kconfig" source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf533/Kconfig" diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index fc164b35a9c..4179e329b9c 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -89,6 +89,85 @@ #endif #endif +/* + * The BF526-EZ-Board changed SDRAM chips between revisions, + * so we use below timings to accommodate both. + */ +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) +#if (CONFIG_SCLK_HZ > 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_8 +#define SDRAM_tRAS_num 8 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_7 +#define SDRAM_tRAS_num 7 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_6 +#define SDRAM_tRAS_num 6 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_5 +#define SDRAM_tRAS_num 5 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ <= 29850746) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_2 +#define SDRAM_tRAS_num 2 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#endif + #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) /*SDRAM INFORMATION: */ @@ -109,6 +188,13 @@ #define SDRAM_CL CL_3 #endif +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_2 +#endif + #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC /* Equation from section 17 (p17-46) of BF533 HRM */ -- cgit v1.2.3 From 3a7f5b1605570f5259e71d1846be27588a00bbaf Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 18 Jun 2009 19:13:03 +0000 Subject: Blackfin: drop unused ISP1760 port1_disable from board resources The port1 disable stuff was dropped from the USB ISP1760, so update the Blackfin boards accordingly. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf527/boards/cm_bf527.c | 1 - arch/blackfin/mach-bf527/boards/ezkit.c | 1 - arch/blackfin/mach-bf537/boards/stamp.c | 1 - arch/blackfin/mach-bf548/boards/ezkit.c | 1 - arch/blackfin/mach-bf561/boards/ezkit.c | 1 - 5 files changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 1eaf27ff722..f4867ce0c61 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -78,7 +78,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 3e5b7db6b06..799a1d1fa89 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -77,7 +77,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index ff7228caa7d..c1f76dd2c4e 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -79,7 +79,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 805a57b5e65..81f5b95cc36 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -76,7 +76,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index b5ef7ff7b7b..4df904f9e90 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, -- cgit v1.2.3 From 3aca47c02097a78a566f67e7ec5fa3e0f2583a73 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 18 Jun 2009 19:40:47 +0000 Subject: Blackfin: fix GPTMR0_CLOCKSOURCE dependency on BFIN_GPTIMERS The GPTMR0_CLOCKSOURCE Kconfig option requires the gptimers framework, so make sure it is selected when this option is enabled. Reported-by: Peter Meerwald Signed-off-by: Mike Frysinger --- arch/blackfin/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 384f7cd6b41..7faa2f554ab 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -648,6 +648,7 @@ config CYCLES_CLOCKSOURCE config GPTMR0_CLOCKSOURCE bool "Use GPTimer0 as a clocksource (higher rating)" + select BFIN_GPTIMERS depends on GENERIC_CLOCKEVENTS depends on !TICKSOURCE_GPTMR0 -- cgit v1.2.3 From bd854c077e660b5f44b5049219645042bcba61ac Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Thu, 18 Jun 2009 22:53:43 +0000 Subject: Blackfin: fix early crash when booting on wrong cpu Make sure we process the kernel command line before poking the hardware, so that we can process early printk. This helps ensure that if you boot a kernel configured for a different processor, something will be left in the log buffer. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 8d789282013..298f023bcc0 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -477,9 +477,11 @@ static __init void parse_cmdline_early(char *cmdline_p) } else if (!memcmp(to, "clkin_hz=", 9)) { to += 9; early_init_clkin_hz(to); +#ifdef CONFIG_EARLY_PRINTK } else if (!memcmp(to, "earlyprintk=", 12)) { to += 12; setup_early_printk(to); +#endif } else if (!memcmp(to, "memmap=", 7)) { to += 7; parse_memmap(to); @@ -798,6 +800,11 @@ void __init setup_arch(char **cmdline_p) { unsigned long sclk, cclk; + /* Check to make sure we are running on the right processor */ + if (unlikely(CPUID != bfin_cpuid())) + printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", + CPU, bfin_cpuid(), bfin_revid()); + #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif @@ -812,14 +819,17 @@ void __init setup_arch(char **cmdline_p) memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - /* setup memory defaults from the user config */ - physical_mem_end = 0; - _ramend = get_mem_size() * 1024 * 1024; - memset(&bfin_memmap, 0, sizeof(bfin_memmap)); + /* If the user does not specify things on the command line, use + * what the bootloader set things up as + */ + physical_mem_end = 0; parse_cmdline_early(&command_line[0]); + if (_ramend == 0) + _ramend = get_mem_size() * 1024 * 1024; + if (physical_mem_end == 0) physical_mem_end = _ramend; @@ -910,10 +920,7 @@ void __init setup_arch(char **cmdline_p) else printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); - if (unlikely(CPUID != bfin_cpuid())) - printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", - CPU, bfin_cpuid(), bfin_revid()); - else { + if (likely(CPUID == bfin_cpuid())) { if (bfin_revid() != bfin_compiled_revid()) { if (bfin_compiled_revid() == -1) printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", -- cgit v1.2.3 From 986d6c1e05642edac81cb8cc99f36a26d16ef220 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Fri, 19 Jun 2009 08:51:11 +0000 Subject: Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction) We don't support the BF535 at all, and the exception 0x2A text specific to it is pretty verbose and confusing (since the behavior is simply odd), so punt it to keep the noise down. Signed-off-by: Yi Li Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/traps.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb07..3cdc454cde2 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n" -- cgit v1.2.3 From 5ecf3e03cd513e8dba080d389b56bac11a2b0d8a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 19 Jun 2009 18:56:57 -0400 Subject: Blackfin: hook up new perf_counter_open syscall Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/unistd.h | 3 ++- arch/blackfin/mach-common/entry.S | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index da35133c171..c8e7ee4768c 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -381,8 +381,9 @@ #define __NR_preadv 366 #define __NR_pwritev 367 #define __NR_rt_tgsigqueueinfo 368 +#define __NR_perf_counter_open 369 -#define __NR_syscall 369 +#define __NR_syscall 370 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 31fa313e81c..5a4e7c7fd92 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table) .long _sys_preadv .long _sys_pwritev .long _sys_rt_tgsigqueueinfo + .long _sys_perf_counter_open .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall -- cgit v1.2.3 From 42b86e06c7db365f1947dda9b75317cbb3c9fb5b Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Mon, 22 Jun 2009 21:48:37 -0400 Subject: Blackfin: fix dma-mapping build errors The recent deprecation of dma_sync_{sg,single} ironically broke Blackfin systems. This is because we don't define dma_sync_sg_for_cpu at all, so until the DMA asm-generic conversion/cleanup is done after the next release, simply stub out the dma_sync_sg_for_{cpu,device} functions. Signed-off-by: FUJITA Tomonori Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/dma-mapping.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h index d7d9148e433..ed6b1f3cccc 100644 --- a/arch/blackfin/include/asm/dma-mapping.h +++ b/arch/blackfin/include/asm/dma-mapping.h @@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev, enum dma_data_direction dir) { } + +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ +} + +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ +} + #endif /* _BLACKFIN_DMA_MAPPING_H */ -- cgit v1.2.3 From 7b994836f09fc3ce7d073ad6f8259a1a84003e02 Mon Sep 17 00:00:00 2001 From: Roel Kluin <[mailto:roel.kluin@gmail.com]> Date: Tue, 23 Jun 2009 10:04:14 +0200 Subject: CRISv10: remove redundant tests on unsigned Since dmanr is unsigned, negatives are wrapped and caught by the other test. Signed-off-by: Roel Kluin Acked-by: Jesper Nilsson --- arch/cris/arch-v10/kernel/dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c index 929e6866629..d31504b4a19 100644 --- a/arch/cris/arch-v10/kernel/dma.c +++ b/arch/cris/arch-v10/kernel/dma.c @@ -24,7 +24,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, unsigned long int gens; int fail = -EINVAL; - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { + if (dmanr >= MAX_DMA_CHANNELS) { printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); return -EINVAL; } @@ -213,7 +213,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, void cris_free_dma(unsigned int dmanr, const char * device_id) { unsigned long flags; - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { + if (dmanr >= MAX_DMA_CHANNELS) { printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); return; } -- cgit v1.2.3 From 2e046b9487dcc60707cac77fb8f744ec830209cd Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 19 Jun 2009 14:40:51 +0900 Subject: sh: Provide cpu_idle_wait() to fix up cpuidle/SMP build. Crib the x86 cpu_idle_wait() implementation and shove it in with the idle code, subsequently enabling ARCH_HAS_CPU_IDLE_WAIT. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 3 +++ arch/sh/include/asm/system.h | 1 + arch/sh/kernel/idle.c | 23 ++++++++++++++++++++++- 3 files changed, 26 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ac1c620d1c7..09c0aef31d0 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -151,6 +151,9 @@ config ARCH_NO_VIRT_TO_BUS config ARCH_HAS_DEFAULT_IDLE def_bool y +config ARCH_HAS_CPU_IDLE_WAIT + def_bool y + config IO_TRAPPED bool diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index a88895e6dcb..ab79e1f4fbe 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -154,6 +154,7 @@ extern struct dentry *sh_debugfs_root; void per_cpu_trap_init(void); void default_idle(void); +void cpu_idle_wait(void); asmlinkage void break_point_trap(void); diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index f35ed034885..27ff2dc093c 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -1,7 +1,7 @@ /* * The idle loop for all SuperH platforms. * - * Copyright (C) 2002 - 2008 Paul Mundt + * Copyright (C) 2002 - 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -79,3 +80,23 @@ void cpu_idle(void) check_pgt_cache(); } } + +static void do_nothing(void *unused) +{ +} + +/* + * cpu_idle_wait - Used to ensure that all the CPUs discard old value of + * pm_idle and update to new pm_idle value. Required while changing pm_idle + * handler on SMP systems. + * + * Caller must have changed pm_idle to the new value before the call. Old + * pm_idle value will not be used by any CPU after the return of this function. + */ +void cpu_idle_wait(void) +{ + smp_mb(); + /* kick all the CPUs so that they exit out of pm_idle */ + smp_call_function(do_nothing, NULL, 1); +} +EXPORT_SYMBOL_GPL(cpu_idle_wait); -- cgit v1.2.3 From 997d0030934f7722d81e5b1cdd7af85ac7ed960b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 19 Jun 2009 15:37:11 +0900 Subject: sh: Use local TLB flush in set_pte_phys(). set_pte_phys() presently uses the global flush_tlb_one(), which locks on SMP trying to do the IPI. As we have not even initialized the other CPUs at this point, switch to the local_ variant so the flush happens on the boot CPU. Signed-off-by: Paul Mundt --- arch/sh/mm/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index ee8e6bbe882..d1be0420421 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -70,7 +70,7 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) } set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot)); - flush_tlb_one(get_asid(), addr); + local_flush_tlb_one(get_asid(), addr); } /* -- cgit v1.2.3 From b29fa1fbc210a51103c7a16af44df42cadce0361 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 19 Jun 2009 15:39:47 +0900 Subject: sh: Wire up the uncached fixmap on sh64 as well. Now that sh64 also can use the uncached section, wire up the fixmap for it as well. Signed-off-by: Paul Mundt --- arch/sh/mm/init.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index d1be0420421..fe532aeaa16 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -177,10 +177,8 @@ void __init paging_init(void) free_area_init_nodes(max_zone_pfns); -#ifdef CONFIG_SUPERH32 /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); -#endif } static struct kcore_list kcore_mem, kcore_vmalloc; -- cgit v1.2.3 From 2eb2a4368273e123d2716a704c86f3130aa14c22 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 19 Jun 2009 16:00:00 +0900 Subject: sh: SH7786 SMP support. SH7786 is roughly identical to SH-X3 proto SMP, though there are only 2 CPUs. This just wraps in to the existing SH-X3 SMP code with some minor changes for SH7786, including wiring up the IPIs properly, enabling IRQ_PER_CPU, and so forth. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 7 ++++++- arch/sh/kernel/cpu/sh4a/Makefile | 6 +++--- arch/sh/kernel/cpu/sh4a/setup-sh7786.c | 29 +++++++++-------------------- 3 files changed, 18 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 09c0aef31d0..eff0f2352c9 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -71,6 +71,9 @@ config GENERIC_HARDIRQS_NO__DO_IRQ config GENERIC_IRQ_PROBE def_bool y +config IRQ_PER_CPU + def_bool y + config GENERIC_GPIO def_bool n @@ -414,6 +417,8 @@ config CPU_SUBTYPE_SH7786 select CPU_HAS_PTEAEX select ARCH_SPARSEMEM_ENABLE select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_SMP + select GENERIC_CLOCKEVENTS_BROADCAST if SMP config CPU_SUBTYPE_SHX3 bool "Support SH-X3 processor" @@ -651,7 +656,7 @@ config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 depends on SMP - default "4" if CPU_SHX3 + default "4" if CPU_SUBTYPE_SHX3 default "2" help This allows you to specify the maximum number of CPUs which this diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 96ea09ca8cc..ebdd391d5f4 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o # SMP setup -smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o +smp-$(CONFIG_CPU_SHX3) := smp-shx3.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o @@ -38,6 +38,6 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o -obj-y += $(clock-y) -obj-$(CONFIG_SMP) += $(smp-y) +obj-y += $(clock-y) +obj-$(CONFIG_SMP) += $(smp-y) obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 93e0d2c017e..b70049470a0 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -595,9 +595,8 @@ enum { HSPI, GPIO0, GPIO1, Thermal, - INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7, - - /* interrupt groups */ + INTICI0, INTICI1, INTICI2, INTICI3, + INTICI4, INTICI5, INTICI6, INTICI7, }; static struct intc_vect vectors[] __initdata = { @@ -638,10 +637,12 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(HSPI, 0xe80), INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), INTC_VECT(Thermal, 0xee0), + INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), + INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), + INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), + INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), }; -/* FIXME: Main CPU support only now */ -#if 1 /* Main CPU */ #define CnINTMSK0 0xfe410030 #define CnINTMSK1 0xfe410040 #define CnINTMSKCLR0 0xfe410050 @@ -654,21 +655,6 @@ static struct intc_vect vectors[] __initdata = { #define CnINT2MSKCR1 0xfe410a34 #define CnINT2MSKCR2 0xfe410a38 #define CnINT2MSKCR3 0xfe410a3c -#else /* Sub CPU */ -#define CnINTMSK0 0xfe410034 -#define CnINTMSK1 0xfe410044 -#define CnINTMSKCLR0 0xfe410054 -#define CnINTMSKCLR1 0xfe410064 -#define CnINT2MSKR0 0xfe410b20 -#define CnINT2MSKR1 0xfe410b24 -#define CnINT2MSKR2 0xfe410b28 -#define CnINT2MSKR3 0xfe410b2c -#define CnINT2MSKCR0 0xfe410b30 -#define CnINT2MSKCR1 0xfe410b34 -#define CnINT2MSKCR2 0xfe410b38 -#define CnINT2MSKCR3 0xfe410b3c -#endif - #define INTMSK2 0xfe410068 #define INTMSKCLR2 0xfe41006c @@ -753,6 +739,9 @@ static struct intc_prio_reg prio_registers[] __initdata = { GPIO1, Thermal } }, { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } }, { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } }, + { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ + { INTICI7, INTICI6, INTICI5, INTICI4, + INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, }; static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, -- cgit v1.2.3 From 854c879f5abf309ebd378bea1ee41acf4ddf7194 Mon Sep 17 00:00:00 2001 From: Pekka J Enberg Date: Mon, 22 Jun 2009 17:39:41 +0300 Subject: x86: Move init_gbpages() to setup_arch() The init_gbpages() function is conditionally called from init_memory_mapping() function. There are two call-sites where this 'after_bootmem' condition can be true: setup_arch() and mem_init() via pci_iommu_alloc(). Therefore, it's safe to move the call to init_gbpages() to setup_arch() as it's always called before mem_init(). This removes an after_bootmem use - paving the way to remove all uses of that state variable. Signed-off-by: Pekka Enberg Acked-by: Yinghai Lu LKML-Reference: Signed-off-by: Ingo Molnar --- arch/x86/kernel/setup.c | 16 ++++++++++++++++ arch/x86/mm/init.c | 17 ----------------- 2 files changed, 16 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index be5ae80f897..de2cab13284 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -289,6 +289,20 @@ void * __init extend_brk(size_t size, size_t align) return ret; } +#ifdef CONFIG_X86_64 +static void __init init_gbpages(void) +{ + if (direct_gbpages && cpu_has_gbpages) + printk(KERN_INFO "Using GB pages for direct mapping\n"); + else + direct_gbpages = 0; +} +#else +static inline void init_gbpages(void) +{ +} +#endif + static void __init reserve_brk(void) { if (_brk_end > _brk_start) @@ -871,6 +885,8 @@ void __init setup_arch(char **cmdline_p) reserve_brk(); + init_gbpages(); + /* max_pfn_mapped is updated here */ max_low_pfn_mapped = init_memory_mapping(0, max_low_pfn< Date: Tue, 23 Jun 2009 17:36:23 +0900 Subject: sh: Fix up more dma-mapping fallout. commit dbe6f1869188b6e04e38aa861dd198befb08bcd7 ("dma-mapping: mark dma_sync_single and dma_sync_sg as deprecated" conveniently broke every single SH build. In the future it would be great if people could at least bother figuring out how to use grep. Signed-off-by: Paul Mundt --- arch/sh/include/asm/dma-mapping.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h index ea9d4f41c9d..69d56dd4c96 100644 --- a/arch/sh/include/asm/dma-mapping.h +++ b/arch/sh/include/asm/dma-mapping.h @@ -97,7 +97,7 @@ static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, dma_unmap_single(dev, dma_address, size, dir); } -static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, +static inline void __dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) @@ -119,7 +119,7 @@ static inline void dma_sync_single_range(struct device *dev, dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); } -static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, +static inline void __dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { int i; @@ -137,7 +137,7 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { - dma_sync_single(dev, dma_handle, size, dir); + __dma_sync_single(dev, dma_handle, size, dir); debug_dma_sync_single_for_cpu(dev, dma_handle, size, dir); } @@ -146,7 +146,7 @@ static inline void dma_sync_single_for_device(struct device *dev, size_t size, enum dma_data_direction dir) { - dma_sync_single(dev, dma_handle, size, dir); + __dma_sync_single(dev, dma_handle, size, dir); debug_dma_sync_single_for_device(dev, dma_handle, size, dir); } @@ -177,7 +177,7 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - dma_sync_sg(dev, sg, nelems, dir); + __dma_sync_sg(dev, sg, nelems, dir); debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); } @@ -185,7 +185,7 @@ static inline void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - dma_sync_sg(dev, sg, nelems, dir); + __dma_sync_sg(dev, sg, nelems, dir); debug_dma_sync_sg_for_device(dev, sg, nelems, dir); } -- cgit v1.2.3 From 0c405b3346ea08098a82a1ee82912b018dfa9f96 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Tue, 23 Jun 2009 13:30:21 +0300 Subject: OMAP1: Fix compilation of arch/arm/mach-omap1/mailbox.c This fixes the positioning of " in MODULE_AUTHOR, which is currently causing a build failure on latest git with CONFIG_OMAP_MBOX_FWK=m; the original breakage appears to date from the end of last year in a5abbbe52b7e89a7633319c5417bd4331f7ac8ed Signed-Off-By: Jonathan McDowell Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 0af4d6c85b4..6810b4aeb02 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); -MODULE_AUTHOR("Hiroshi DOYU" ); +MODULE_AUTHOR("Hiroshi DOYU "); MODULE_ALIAS("platform:omap1-mailbox"); -- cgit v1.2.3 From e4d24ec39c98cdc9cd97c26fdd426bbab0034fbe Mon Sep 17 00:00:00 2001 From: Andrew de Quincey Date: Tue, 23 Jun 2009 13:30:21 +0300 Subject: OMAP1: Fix N770 MMC support Some of the N770's MMC configuration options seem to have been dropped. This patch adds them back in again. Note that only the .ocr_mask change was /critical/, but I've added the .max_freq setting back as well, as the original sources had it. Can anyone confirm if this is unnecessary? Secondly, there is support in the original code for a 4wire/higher speed mode. As I don't have the requisite N770 hardware (I think it was a rev2 N770?) to test this, I can't really add it back. Signed-off-by: Andrew de Quincey Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-nokia770.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index e70fc7c66bb..d9ebba01ffc 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -205,9 +205,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot) static struct omap_mmc_platform_data nokia770_mmc2_data = { .nr_slots = 1, .dma_mask = 0xffffffff, + .max_freq = 12000000, .slots[0] = { .set_power = nokia770_mmc_set_power, .get_cover_state = nokia770_mmc_get_cover_state, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .name = "mmcblk", }, }; -- cgit v1.2.3 From d376f89701b0aa5b45d25fbfbeb1a0040399ad30 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Tue, 23 Jun 2009 13:30:22 +0300 Subject: OMAP1: remove duplicated #include Remove duplicated #include in arch/arm/mach-omap1/board-nokia770.c. Signed-off-by: Huang Weiyi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-nokia770.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index d9ebba01ffc..ed2a48a9ce7 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #define ADS7846_PENDOWN_GPIO 15 -- cgit v1.2.3 From 762ad3a476baa1831f732488e80960f4aa024393 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Tue, 23 Jun 2009 13:30:22 +0300 Subject: OMAP2/3: mmc-twl4030: use correct controller in twl_mmc23_set_power twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which breaks MMC3. Find the right controller to use instead. Signed-off-by: Grazvydas Ignotas Cc: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mmc-twl4030.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c index 9756a878fd9..1541fd4c8d0 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ b/arch/arm/mach-omap2/mmc-twl4030.c @@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) { int ret = 0; - struct twl_mmc_controller *c = &hsmmc[1]; + struct twl_mmc_controller *c = NULL; struct omap_mmc_platform_data *mmc = dev->platform_data; + int i; + + for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { + if (mmc == hsmmc[i].mmc) { + c = &hsmmc[i]; + break; + } + } + + if (c == NULL) + return -ENODEV; /* If we don't see a Vcc regulator, assume it's a fixed * voltage always-on regulator. -- cgit v1.2.3 From 091a58af0ba1765d80b1e74382c7572baceb1bdc Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Tue, 23 Jun 2009 13:30:22 +0300 Subject: OMAP2/3: omap mailbox: platform_get_irq() error ignored platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq is unsigned, so the error was not noticed. Signed-off-by: Roel Kluin Signed-off-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mailbox.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index fd5b8a5925c..6f71f3730c9 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) return -ENOMEM; /* DSP or IVA2 IRQ */ - mbox_dsp_info.irq = platform_get_irq(pdev, 0); - if (mbox_dsp_info.irq < 0) { + ret = platform_get_irq(pdev, 0); + if (ret < 0) { dev_err(&pdev->dev, "invalid irq resource\n"); - ret = -ENODEV; goto err_dsp; } + mbox_dsp_info.irq = ret; ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); if (ret) -- cgit v1.2.3 From 8e25ad964aac0bf6b30dd013303750089f819679 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 23 Jun 2009 13:30:23 +0300 Subject: OMAP2/3: Add omap_type() for determining GP/EMU/HS The omap_type() function is added and returns the DEVICETYPE field of the CONTROL_STATUS register. The result can be used for conditional code based on whether device is GP (general purpose), EMU or HS (high security). Also move the type defines so omap1 code compile does not require ifdefs for sections using these defines. This code is needed for the following fix to set the SRAM size correctly for HS omaps. Also at least PM and watchdog code will need this function. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 22 ++++++++++++++++++++++ arch/arm/plat-omap/include/mach/cpu.h | 22 +++++++++++----------- 2 files changed, 33 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 458990e20c6..a98201cc265 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci) } EXPORT_SYMBOL(omap_chip_is); +int omap_type(void) +{ + u32 val = 0; + + if (cpu_is_omap24xx()) + val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); + else if (cpu_is_omap34xx()) + val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); + else { + pr_err("Cannot detect omap type!\n"); + goto out; + } + + val &= OMAP2_DEVICETYPE_MASK; + val >>= 8; + +out: + return val; +} +EXPORT_SYMBOL(omap_type); + + /*----------------------------------------------------------------------------*/ #define OMAP_TAP_IDCODE 0x0204 diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index fc60c4ebcc2..285eaa3a827 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h @@ -30,6 +30,17 @@ #ifndef __ASM_ARCH_OMAP_CPU_H #define __ASM_ARCH_OMAP_CPU_H +/* + * Omap device type i.e. EMU/HS/TST/GP/BAD + */ +#define OMAP2_DEVICE_TYPE_TEST 0 +#define OMAP2_DEVICE_TYPE_EMU 1 +#define OMAP2_DEVICE_TYPE_SEC 2 +#define OMAP2_DEVICE_TYPE_GP 3 +#define OMAP2_DEVICE_TYPE_BAD 4 + +int omap_type(void); + struct omap_chip_id { u8 oc; u8 type; @@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430) int omap_chip_is(struct omap_chip_id oci); -int omap_type(void); - -/* - * Macro to detect device type i.e. EMU/HS/TST/GP/BAD - */ -#define OMAP2_DEVICE_TYPE_TEST 0 -#define OMAP2_DEVICE_TYPE_EMU 1 -#define OMAP2_DEVICE_TYPE_SEC 2 -#define OMAP2_DEVICE_TYPE_GP 3 -#define OMAP2_DEVICE_TYPE_BAD 4 - void omap2_check_revision(void); #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ -- cgit v1.2.3 From 5b0acc59d1bc5c310dfd6976555664f9dcf4dacd Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 23 Jun 2009 13:30:23 +0300 Subject: OMAP3: SRAM size fix for HS/EMU devices SRAM size fix for HS/EMU devices Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/sram.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 65006df3f1b..4ea73804d21 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -133,7 +133,12 @@ void __init omap_detect_sram(void) if (cpu_is_omap34xx()) { omap_sram_base = OMAP3_SRAM_PUB_VA; omap_sram_start = OMAP3_SRAM_PUB_PA; - omap_sram_size = 0x8000; /* 32K */ + if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || + (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { + omap_sram_size = 0x7000; /* 28K */ + } else { + omap_sram_size = 0x8000; /* 32K */ + } } else { omap_sram_base = OMAP2_SRAM_PUB_VA; omap_sram_start = OMAP2_SRAM_PUB_PA; -- cgit v1.2.3 From aecedb94b366d6fb5e2a17ca18a5dc78e593198e Mon Sep 17 00:00:00 2001 From: Kalle Jokiniemi Date: Tue, 23 Jun 2009 13:30:24 +0300 Subject: OMAP3: DMA: Enable idlemodes for DMA OCP This patch enables MStandby smart-idle mode, autoidle smartidle mode, and the autoidle bit for DMA4_OCP_SYSCONFIG. Signed-off-by: Kalle Jokiniemi Signed-off-by: Tony Lindgren Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/dma.c | 13 +++++++++++++ arch/arm/plat-omap/include/mach/dma.h | 15 +++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index def14ec265b..7677a4a1cef 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void) setup_irq(irq, &omap24xx_dma_irq); } + /* Enable smartidle idlemodes and autoidle */ + if (cpu_is_omap34xx()) { + u32 v = dma_read(OCP_SYSCONFIG); + v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | + DMA_SYSCONFIG_SIDLEMODE_MASK | + DMA_SYSCONFIG_AUTOIDLE); + v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | + DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | + DMA_SYSCONFIG_AUTOIDLE); + dma_write(v , OCP_SYSCONFIG); + } + + /* FIXME: Update LCD DMA to work on 24xx */ if (cpu_class_is_omap1()) { r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h index 8c1eae88737..7b939cc0196 100644 --- a/arch/arm/plat-omap/include/mach/dma.h +++ b/arch/arm/plat-omap/include/mach/dma.h @@ -389,6 +389,21 @@ #define DMA_THREAD_FIFO_25 (0x02 << 14) #define DMA_THREAD_FIFO_50 (0x03 << 14) +/* DMA4_OCP_SYSCONFIG bits */ +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) +#define DMA_SYSCONFIG_EMUFREE (1 << 5) +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) +#define DMA_SYSCONFIG_SOFTRESET (1 << 2) +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) + +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) + +#define DMA_IDLEMODE_SMARTIDLE 0x2 +#define DMA_IDLEMODE_NO_IDLE 0x1 +#define DMA_IDLEMODE_FORCE_IDLE 0x0 + /* Chaining modes*/ #ifndef CONFIG_ARCH_OMAP1 #define OMAP_DMA_STATIC_CHAIN 0x1 -- cgit v1.2.3 From 6d453e84b587f38e4197bb2c6a37296c4a80cbac Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 23 Jun 2009 13:30:24 +0300 Subject: OMAP2/3: gpmc-onenand: correct use of async timings Use async timings when sync timings are not requested. Also ensure that OneNAND is in async mode when async timings are used. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 2fd22f9c5f0..54fec53a48e 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = { static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) { struct gpmc_timings t; + u32 reg; + int err; const int t_cer = 15; const int t_avdp = 12; @@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) const int t_wpl = 40; const int t_wph = 30; + /* Ensure sync read and sync write are disabled */ + reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); + reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; + writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); + memset(&t, 0, sizeof(t)); t.sync_clk = 0; t.cs_on = 0; @@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) GPMC_CONFIG1_DEVICESIZE_16 | GPMC_CONFIG1_MUXADDDATA); - return gpmc_cs_set_timings(cs, &t); + err = gpmc_cs_set_timings(cs, &t); + if (err) + return err; + + /* Ensure sync read and sync write are disabled */ + reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); + reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; + writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); + + return 0; } static void set_onenand_cfg(void __iomem *onenand_base, int latency, @@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, } else if (cfg->flags & ONENAND_SYNC_READWRITE) { sync_read = 1; sync_write = 1; - } + } else + return omap2_onenand_set_async_mode(cs, onenand_base); if (!freq) { /* Very first call freq is not known */ -- cgit v1.2.3 From c8e6488f7b56d82453fc7d526118e9f1c2df133a Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 23 Jun 2009 13:30:25 +0300 Subject: OMAP3: RX51: Use OneNAND sync read / write Use OneNAND sync read / write Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-rx51-peripherals.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index da93b86234e..9a0bf6744a0 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = { .gpio_irq = 65, .parts = onenand_partitions, .nr_parts = ARRAY_SIZE(onenand_partitions), + .flags = ONENAND_SYNC_READWRITE, }; static void __init board_onenand_init(void) -- cgit v1.2.3 From f48ef99ca14577f3ea0a48c0e05ed7f5f6d211e9 Mon Sep 17 00:00:00 2001 From: Fernando Guzman Lugo Date: Tue, 23 Jun 2009 13:30:25 +0300 Subject: OMAP: IOMMU: function flush_iotlb_page is not flushing correct entry The function flush_iotlb_page is not loading the CAM register with the correct entry to be flushed, so it is flushing other entry Signed-off-by: Fernando Guzman Lugo Signed-off-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 4cf449fa2cb..4a030139901 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da) if ((start <= da) && (da < start + bytes)) { dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", __func__, start, da, bytes); - + iotlb_load_cr(obj, &cr); iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } -- cgit v1.2.3 From cb5793db5ecf108594d8006ae838e47996a76a19 Mon Sep 17 00:00:00 2001 From: janboe Date: Tue, 23 Jun 2009 13:30:25 +0300 Subject: OMAP2/3: Initialize gpio debounce register Some bootloader may initialize debounce register and this will make dbclk not consist with the debounce register after linux kernel boot up. Signed-off-by: janboe Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7fd89ba8d3b..26b387c1242 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void) __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); + __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); /* Initialize interface clock ungated, module enabled */ __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); -- cgit v1.2.3 From 291e99a112f9bf34c027031de7ef8b94a2692937 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 4 May 2009 09:30:51 +0100 Subject: [ARM] S3C24XX: Fix use of CONFIG_S3C24XX_PWM CONFIG_S3C24XX_PWM was defined in arch/arm/plat-s3c24xx/Kconfig but not used anywhere else as the corresponding makefile used CONFIG_HAVE_PWM (selected by CONFIG_S3C24XX_PWM) to compile the PWM driver. Change the makefile to use CONFIG_S3C24XX_PWM to compile this driver to ensure it is only build when needed. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 636cb12711d..579a165c282 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += sleep.o -obj-$(CONFIG_HAVE_PWM) += pwm.o +obj-$(CONFIG_S3C24XX_PWM) += pwm.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o obj-$(CONFIG_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C24XX_ADC) += adc.o -- cgit v1.2.3 From a18327f35a879a6467c3e901da7f68944b191732 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 4 May 2009 09:53:12 +0100 Subject: [ARM] S3C: Remove unused CONFIG_DEBUG_S3C_PORT Remove the unused CONFIG_DEBUG_S3C_PORT as we currently only have support for using the S3C UARTs via the low-level debug code. Signed-off-by: Ben Dooks --- arch/arm/Kconfig.debug | 8 -------- arch/arm/configs/s3c2410_defconfig | 1 - arch/arm/configs/s3c6400_defconfig | 1 - arch/arm/configs/tct_hammer_defconfig | 1 - 4 files changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index a71fd941ade..a89e4734b8f 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -99,14 +99,6 @@ config DEBUG_CLPS711X_UART2 output to the second serial port on these devices. Saying N will cause the debug messages to appear on the first serial port. -config DEBUG_S3C_PORT - depends on DEBUG_LL && PLAT_S3C - bool "Kernel low-level debugging messages via S3C UART" - help - Say Y here if you want debug print routines to go to one of the - S3C internal UARTs. The chosen UART must have been configured - before it is used. - config DEBUG_S3C_UART depends on PLAT_S3C int "S3C UART to use for low-level debug" diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 2d58b8fe59b..f4f1899f3c8 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -2298,7 +2298,6 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set -CONFIG_DEBUG_S3C_PORT=y CONFIG_DEBUG_S3C_UART=0 # diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 2e8fa50e9a0..32860609e05 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -816,7 +816,6 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set -CONFIG_DEBUG_S3C_PORT=y CONFIG_DEBUG_S3C_UART=0 # diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index 07dfb98df4f..9d32faef05f 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -857,7 +857,6 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set -# CONFIG_DEBUG_S3C_PORT is not set CONFIG_DEBUG_S3C_UART=0 # -- cgit v1.2.3 From f49156ea1bf3bccf45a01351cf3db2b5f6a8597e Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 26 May 2009 10:21:42 -0500 Subject: powerpc/qe: add polling timeout to qe_issue_cmd() The qe_issue_cmd() function (Freescale PowerPC QUICC Engine library) polls on a register until a status bit changes, but does not include a timeout to handle the situation if the bit never changes. Change the code to use the new spin_event_timeout() macro, which simplifies polling on a register without a timeout. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/qe.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index b28b0e512d6..237e3654f48 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -112,6 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) { unsigned long flags; u8 mcn_shift = 0, dev_shift = 0; + u32 ret; spin_lock_irqsave(&qe_lock, flags); if (cmd == QE_RESET) { @@ -139,11 +140,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) } /* wait for the QE_CR_FLG to clear */ - while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) - cpu_relax(); + ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0, + 100, 0); + /* On timeout (e.g. failure), the expression will be false (ret == 0), + otherwise it will be true (ret == 1). */ spin_unlock_irqrestore(&qe_lock, flags); - return 0; + return ret == 1; } EXPORT_SYMBOL(qe_issue_cmd); -- cgit v1.2.3 From 5e10cf587a7b1aa34099cbfc244e6f04e96dc835 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 19 May 2009 00:52:20 -0500 Subject: powerpc/cpm1: Remove IMAP_ADDR We no longer user IMAP_ADDR for anything so kill it off. Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/cpm1.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h index 2ff798744c1..7685ffde882 100644 --- a/arch/powerpc/include/asm/cpm1.h +++ b/arch/powerpc/include/asm/cpm1.h @@ -598,8 +598,6 @@ typedef struct risc_timer_pram { #define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#define IMAP_ADDR (get_immrbase()) - #define CPM_PIN_INPUT 0 #define CPM_PIN_OUTPUT 1 #define CPM_PIN_PRIMARY 0 -- cgit v1.2.3 From a44a23ed4d144e4fb83d256b32021b732bda4787 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Jun 2009 23:28:34 -0500 Subject: powerpc/85xx: Stop using ppc_md.init on socrates Match what other 85xx platforms do for of_platform_bus_probe and use machine_device_initcall. This is one small step in killing of ppc_md.init. Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/socrates.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c index d0e8443b12c..747d8fb3ab8 100644 --- a/arch/powerpc/platforms/85xx/socrates.c +++ b/arch/powerpc/platforms/85xx/socrates.c @@ -102,10 +102,11 @@ static struct of_device_id __initdata socrates_of_bus_ids[] = { {}, }; -static void __init socrates_init(void) +static int __init socrates_publish_devices(void) { - of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); + return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); } +machine_device_initcall(socrates, socrates_publish_devices); /* * Called very early, device-tree isn't unflattened @@ -124,7 +125,6 @@ define_machine(socrates) { .name = "Socrates", .probe = socrates_probe, .setup_arch = socrates_setup_arch, - .init = socrates_init, .init_IRQ = socrates_pic_init, .get_irq = mpic_get_irq, .restart = fsl_rstcr_restart, -- cgit v1.2.3 From fa874618c3155e4f255387987d630a203578b5ae Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Fri, 19 Jun 2009 03:22:08 +0400 Subject: powerpc/85xx: Fix FSL RapidIO probing on MDS boards FSL RapidIO won't probe without a proper compatible entry. This patch fixes the issue by adding fsl,rapidio-delta compatible to mpc85xx_ids. Signed-off-by: Randy Vinson Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 77f90b35635..60ed9c067b1 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -285,6 +285,7 @@ static struct of_device_id mpc85xx_ids[] = { { .type = "qe", }, { .compatible = "fsl,qe", }, { .compatible = "gianfar", }, + { .compatible = "fsl,rapidio-delta", }, {}, }; -- cgit v1.2.3 From cb1ffb6204712b04396ae0a9f3d1bf93cd8df8fb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 19 Jun 2009 03:30:42 -0500 Subject: powerpc/85xx: Fix issue found by lockdep trace in smp_85xx_kick_cpu lockdep trace found the following: ------------[ cut here ]------------ Badness at c007baf0 [verbose debug info unavailable] NIP: c007baf0 LR: c007bad8 CTR: 00000000 REGS: ef855e00 TRAP: 0700 Tainted: G W (2.6.30-06736-g12a31df-dirty) MSR: 00021000 CR: 24044022 XER: 20000000 TASK = ef858000[1] 'swapper' THREAD: ef854000 CPU: 0 GPR00: 00000000 ef855eb0 ef858000 00000001 000000d0 f1000000 ffbc8000 ffffffff GPR08: 000000d0 c0760000 c0710000 00000007 2fffffff 1004a388 7ffd9400 00000000 GPR16: 00000000 7ffcd100 7ffcd100 7ffcd100 c059cd78 c075c498 c057da7c ffffffff GPR24: ffbc8000 f1000000 00000001 c00bf8b0 c07595d4 000000d0 00021000 000000d0 NIP [c007baf0] lockdep_trace_alloc+0xc0/0xf0 LR [c007bad8] lockdep_trace_alloc+0xa8/0xf0 Call Trace: [ef855eb0] [c007ba60] lockdep_trace_alloc+0x30/0xf0 (unreliable) [ef855ec0] [c00cb3ac] kmem_cache_alloc+0x2c/0xf0 [ef855ee0] [c00bf8b0] __get_vm_area_node+0x80/0x1c0 [ef855f10] [c0017580] __ioremap_caller+0x1d0/0x1e0 [ef855f40] [c057da7c] smp_85xx_kick_cpu+0x64/0x124 [ef855f60] [c0599180] __cpu_up+0xd0/0x1a4 [ef855f80] [c05997c4] cpu_up+0x14c/0x1e0 [ef855fc0] [c05732a0] kernel_init+0x100/0x1c4 [ef855ff0] [c0011524] kernel_thread+0x4c/0x68 Instruction dump: 8009c174 2f800000 409e0048 73c08000 40820040 4818980d 2f830000 419effa0 3d20c076 8009c388 2f800000 409eff90 <0fe00000> 4bffff88 60000000 60000000 We were calling ioremap after we local_irq_restore(flags). A simple reorder fixes the problem. Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/smp.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index cc0b0db8a6f..62c592ede64 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -52,20 +52,19 @@ smp_85xx_kick_cpu(int nr) pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); - local_irq_save(flags); - np = of_get_cpu_node(nr, NULL); cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); if (cpu_rel_addr == NULL) { printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); - local_irq_restore(flags); return; } /* Map the spin table */ bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); + local_irq_save(flags); + out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); @@ -73,10 +72,10 @@ smp_85xx_kick_cpu(int nr) while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) mdelay(1); - iounmap(bptr_vaddr); - local_irq_restore(flags); + iounmap(bptr_vaddr); + pr_debug("waited %d msecs for CPU #%d.\n", n, nr); } -- cgit v1.2.3 From 6cc7959f385abc77abdeda5462f96407a556265a Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Sat, 20 Jun 2009 19:16:59 +0800 Subject: powerpc/85xx: remove duplicated #include Remove duplicated #include in arch/powerpc/platforms/85xx/xes_mpc85xx.c. Signed-off-by: Huang Weiyi Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/xes_mpc85xx.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c index ee01532786e..1b426050a2f 100644 --- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c @@ -32,7 +32,6 @@ #include #include -#include /* A few bit definitions needed for fixups on some boards */ #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ -- cgit v1.2.3 From 66c6b856d8738278a4a6e558d25c90e9950aa112 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 19 Jun 2009 03:37:52 +0400 Subject: powerpc/85xx: Make eSDHC 1-bit only transfer mode default for MPC8569E-MDS For yet unknown reason 4-bit mode doesn't work on MPC8569E-MDS boards, so make 1-bit mode default. When we resolve the issue, u-boot will remove sdhci,1-bit-only property from the device tree, while SDHCI will still work with older u-boots. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8569mds.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts index a8dcb018c4a..a680165292f 100644 --- a/arch/powerpc/boot/dts/mpc8569mds.dts +++ b/arch/powerpc/boot/dts/mpc8569mds.dts @@ -253,6 +253,7 @@ /* Filled in by U-Boot */ clock-frequency = <0>; status = "disabled"; + sdhci,1-bit-only; }; crypto@30000 { -- cgit v1.2.3 From 503dcbeba50fd3545283594bc391b4a400fa6c48 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 23 Jun 2009 16:55:30 +0300 Subject: OMAP: Fix IOMEM macro for assembly Otherwise IOMEM calculations can fail. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/mach/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index 3b281472056..73f483d56ca 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h @@ -201,7 +201,7 @@ #define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa)) #ifdef __ASSEMBLER__ -#define IOMEM(x) x +#define IOMEM(x) (x) #else #define IOMEM(x) ((void __force __iomem *)(x)) -- cgit v1.2.3 From 927dbcd668ede8d2210cc59bea548ca9ff45b240 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Jun 2009 16:15:38 +0100 Subject: [ARM] S3C24XX: Fix spi-bus configuration build errors The commit ec976d6eb021dc8f2994248c310a41540f4756bd removed a number of gpio definitions from but misssed updating these two files: Fix the following build errors by including : arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c: In function 's3c24xx_spi_gpiocfg_bus1_gpg5_6_7': arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c:25: error: implicit declaration of function 's3c2410_gpio_cfgpin' arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c:28: error: implicit declaration of function 's3c2410_gpio_pullup' arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c: In function 's3c24xx_spi_gpiocfg_bus0_gpe11_12_13': arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c:25: error: implicit declaration of function 's3c2410_gpio_cfgpin' arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c:28: error: implicit declaration of function 's3c2410_gpio_pullup' Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | 3 +-- arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c index 9edf7894eed..da7a61728c1 100644 --- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c @@ -12,8 +12,7 @@ */ #include - -#include +#include #include #include diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c index f34d0fc69ad..86b9edc6741 100644 --- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c @@ -12,8 +12,7 @@ */ #include - -#include +#include #include #include -- cgit v1.2.3 From ffd14417bdf2a1650bcb16d37c7e658535d1681a Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Tue, 23 Jun 2009 20:58:57 +0800 Subject: [ARM] MINI2440: remove duplicated #include Remove duplicated #include('s) in arch/arm/mach-s3c2440/mach-mini2440.c Signed-off-by: Huang Weiyi Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-mini2440.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 6a5bc3021bd..e714bfabbc0 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -48,8 +48,6 @@ #include #include -#include - #include #include #include -- cgit v1.2.3 From a3c79901170aba0d3717c2602326bab639eb1344 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Jun 2009 16:30:02 +0100 Subject: [ARM] S3C24XX: Fix missing s3c_iis_device. Commit 52da219e9664e537a745877b0efa7cf2b1ff2996 removed the s3c_device_iis, but didn't replace it with anything so a number of s3c24xx machines are currently failing to build. As a temporary fix, re-instate s3c_device_iis until a proper replacement can be done for it. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/devs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index b5b9c4d46e9..2e170827e0b 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -37,6 +37,7 @@ extern struct platform_device s3c_device_i2c1; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; +extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_hwmon; extern struct platform_device s3c_device_hsmmc0; extern struct platform_device s3c_device_hsmmc1; -- cgit v1.2.3 From b647712f669f4fadf428a14ab45ab4c03558cdf5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Jun 2009 16:34:35 +0100 Subject: [ARM] S3C: Fix S3C24XX build to not include s3c64xx IIS devices Commit 52da219e9664e537a745877b0efa7cf2b1ff2996 added IIS platform devices, but these do not build on s3c24xx systems and the file depends on SND_S3C24XX_SOC, which is selected for all S3C64XX/S3C24XX systems. As a quick fix, make the dev-audio.o file depends on SND_S3C64XX_SOC_I2S instead. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 74bb7cb5da4..0761766b183 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o -obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o +obj-$(CONFIG_SND_S3C64XX_SOC_I2S) += dev-audio.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o -- cgit v1.2.3 From bb38c222e07cbe252cfbd99cd6a9c834b0a2639a Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 24 Jun 2009 01:41:05 +0900 Subject: sh: Fix up HAVE_PERF_COUNTERS typo. That's HAVE_PERF_COUNTERS not HAVE_PERF_COUNTER. This was right initially but I seem to have screwed it up while re-typing it out by hand on another machine when I checked it in. Hmph. Reported-by: Robert P. J. Day Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index eff0f2352c9..e2bdd7b94fd 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -15,7 +15,7 @@ config SUPERH select HAVE_IOREMAP_PROT if MMU select HAVE_ARCH_TRACEHOOK select HAVE_DMA_API_DEBUG - select HAVE_PERF_COUNTER + select HAVE_PERF_COUNTERS select RTC_LIB select GENERIC_ATOMIC64 help -- cgit v1.2.3 From 622a8f5f7bf160507861cf05309020049f42976d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Jun 2009 18:20:10 +0100 Subject: [ARM] s3c2410_defconfig: add MINI2440 machine to build Add the MINI2440 to the list of machines built by the central defconfig. Signed-off-by: Ben Dooks --- arch/arm/configs/s3c2410_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index f4f1899f3c8..b49810461e4 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -260,6 +260,7 @@ CONFIG_MACH_NEXCODER_2440=y CONFIG_SMDK2440_CPU2440=y CONFIG_MACH_AT2440EVB=y CONFIG_CPU_S3C2442=y +CONFIG_MACH_MINI2440=y # # S3C2442 Machines -- cgit v1.2.3 From 51af243c631d9d03376d1454a24cf0a96e6f17cb Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 23 Jun 2009 18:23:27 +0100 Subject: [ARM] MINI2440: Add missing flash_bbt flat to NAND The commit 9db41f9edcb87ae050fcb171c44be7f212728d54 added the .flash_bbt flag to the nand set, so add this back into the mach-mini2440.c file (taken out on initial commit to allow build). Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-mini2440.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index e714bfabbc0..ec71a696578 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -273,6 +273,7 @@ static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = { .nr_chips = 1, .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part), .partitions = mini2440_default_nand_part, + .flash_bbt = 1, /* we use u-boot to create a BBT */ }, }; -- cgit v1.2.3 From 840c516f9c395c64240ad35f858f37ea16270afa Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Tue, 23 Jun 2009 12:37:06 -0700 Subject: h8/300: fix incorrect "select" directives in arch/h8300/Kconfig.cpu. Fix the incorrect "select" directives by dropping the "CONFIG_" prefixes, and correcting the typo "H8S2768" to "H8S2678". Signed-off-by: Robert P. J. Day Acked-by: Yoshinori Sato Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/h8300/Kconfig.cpu | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu index b65dcfe51d9..6e2ecff199c 100644 --- a/arch/h8300/Kconfig.cpu +++ b/arch/h8300/Kconfig.cpu @@ -13,7 +13,7 @@ config H8300H_GENERIC config H8300H_AKI3068NET bool "AE-3068/69" - select CONFIG_H83068 + select H83068 help AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support More Information. (Japanese Only) @@ -24,7 +24,7 @@ config H8300H_AKI3068NET config H8300H_H8MAX bool "H8MAX" - select CONFIG_H83068 + select H83068 help H8MAX Evaluation Board Support More Information. (Japanese Only) @@ -32,7 +32,7 @@ config H8300H_H8MAX config H8300H_SIM bool "H8/300H Simulator" - select CONFIG_H83007 + select H83007 help GDB Simulator Support More Information. @@ -45,7 +45,7 @@ config H8S_GENERIC config H8S_EDOSK2674 bool "EDOSK-2674" - select CONFIG_H8S2768 + select H8S2678 help Renesas EDOSK-2674 Evaluation Board Support More Information. -- cgit v1.2.3 From 7262b6e4a4cc18d0f67df145d032c843e4bc382b Mon Sep 17 00:00:00 2001 From: Hidetoshi Seto Date: Tue, 23 Jun 2009 12:40:54 +0900 Subject: x86, mce: Fix mce resume on 32bit Calling mcheck_init() on resume is required only with CONFIG_X86_OLD_MCE=y. Signed-off-by: Hidetoshi Seto Acked-by: Andi Kleen Signed-off-by: H. Peter Anvin --- arch/x86/power/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index d277ef1eea5..b3d20b9cac6 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -244,7 +244,7 @@ static void __restore_processor_state(struct saved_context *ctxt) do_fpu_end(); mtrr_ap_init(); -#ifdef CONFIG_X86_32 +#ifdef CONFIG_X86_OLD_MCE mcheck_init(&boot_cpu_data); #endif } -- cgit v1.2.3 From f007e99c8e2e322b8331aba72414715119a2920d Mon Sep 17 00:00:00 2001 From: Weidong Han Date: Sat, 23 May 2009 00:41:15 +0800 Subject: Intel-IOMMU, intr-remap: source-id checking To support domain-isolation usages, the platform hardware must be capable of uniquely identifying the requestor (source-id) for each interrupt message. Without source-id checking for interrupt remapping , a rouge guest/VM with assigned devices can launch interrupt attacks to bring down anothe guest/VM or the VMM itself. This patch adds source-id checking for interrupt remapping, and then really isolates interrupts for guests/VMs with assigned devices. Because PCI subsystem is not initialized yet when set up IOAPIC entries, use read_pci_config_byte to access PCI config space directly. Signed-off-by: Weidong Han Signed-off-by: David Woodhouse --- arch/x86/kernel/apic/io_apic.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index b7a79207295..4d0216fcb36 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1414,6 +1414,9 @@ int setup_ioapic_entry(int apic_id, int irq, irte.vector = vector; irte.dest_id = IRTE_DEST(destination); + /* Set source-id of interrupt request */ + set_ioapic_sid(&irte, apic_id); + modify_irte(irq, &irte); ir_entry->index2 = (index >> 15) & 0x1; @@ -3290,6 +3293,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms irte.vector = cfg->vector; irte.dest_id = IRTE_DEST(dest); + /* Set source-id of interrupt request */ + set_msi_sid(&irte, pdev); + modify_irte(irq, &irte); msg->address_hi = MSI_ADDR_BASE_HI; -- cgit v1.2.3 From 76609a6928bff29ca05a94420ae3e088fbb9c2f9 Mon Sep 17 00:00:00 2001 From: Nelson Castillo Date: Tue, 23 Jun 2009 13:54:32 -0500 Subject: [ARM] GTA02: build fixes (s3c2410_nand_set usage) This patch fixes two errors we get when building GTA02 kernel. ~ use_bbt is incorrect, we need flash_bbt. ~ We do not need .force_soft_ecc because we can unset CONFIG_MTD_NAND_S3C2410_HWECC. Signed-off-by: Nelson Castillo [ben-linux@fluff.org: updated patch description] Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2442/mach-gta02.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index e23b581aa0e..0fb385bd9cd 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -433,8 +433,7 @@ static struct s3c2410_nand_set gta02_nand_sets[] = { */ .name = "neo1973-nand", .nr_chips = 1, - .use_bbt = 1, - .force_soft_ecc = 1, + .flash_bbt = 1, }, }; -- cgit v1.2.3 From c14dab5c0782ef632742963a66276a195418a63c Mon Sep 17 00:00:00 2001 From: Yong Wang Date: Wed, 24 Jun 2009 10:13:24 +0800 Subject: perf_counter, x86: Set global control MSR correctly Previous code made an assumption that the power on value of global control MSR has enabled all fixed and general purpose counters properly. However, this is not the case for certain Intel processors, such as Atom - and it might also be firmware dependent. Each enable bit in IA32_PERF_GLOBAL_CTRL is AND'ed with the enable bits for all privilege levels in the respective IA32_PERFEVTSELx or IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective counters. Counting is enabled if the AND'ed results is true; counting is disabled when the result is false. The end result is that all fixed counters are always disabled on Atom processors because the assumption is just invalid. Fix this by not initializing the ctrl-mask out of the global MSR, but setting it to perf_counter_mask. Reported-by: Stephane Eranian Signed-off-by: Yong Wang Cc: Arjan van de Ven Cc: Peter Zijlstra Cc: Mike Galbraith Cc: Paul Mackerras LKML-Reference: <20090624021324.GA2788@ywang-moblin2.bj.intel.com> Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_counter.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 22eb3a1d4f9..a310d19faca 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -969,13 +969,6 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) if (!x86_pmu.num_counters_fixed) return -1; - /* - * Quirk, IA32_FIXED_CTRs do not work on current Atom processors: - */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86_model == 28) - return -1; - event = hwc->config & ARCH_PERFMON_EVENT_MASK; if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) @@ -1428,8 +1421,6 @@ static int intel_pmu_init(void) */ x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); - rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); - /* * Install the hw-cache-events table: */ @@ -1514,6 +1505,7 @@ void __init init_hw_perf_counters(void) perf_counter_mask |= ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; + x86_pmu.intel_ctrl = perf_counter_mask; perf_counters_lapic_init(); register_die_notifier(&perf_counter_nmi_notifier); -- cgit v1.2.3 From d94d4adb7dd05b4e25f3c317a1b932ec74272a12 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 24 Jun 2009 22:35:30 +0900 Subject: sh: make set_perf_counter_pending() static inline. Fixes up a recently introduced build error. Reported-by: Kyle McMartin Signed-off-by: Paul Mundt --- arch/sh/include/asm/perf_counter.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/include/asm/perf_counter.h b/arch/sh/include/asm/perf_counter.h index a8153c2aa6f..61c2b40c802 100644 --- a/arch/sh/include/asm/perf_counter.h +++ b/arch/sh/include/asm/perf_counter.h @@ -2,6 +2,6 @@ #define __ASM_SH_PERF_COUNTER_H /* SH only supports software counters through this interface. */ -#define set_perf_counter_pending() do { } while (0) +static inline void set_perf_counter_pending(void) {} #endif /* __ASM_SH_PERF_COUNTER_H */ -- cgit v1.2.3 From 9c26f52b900f7207135bafc8789e1a4f5d43e096 Mon Sep 17 00:00:00 2001 From: Cliff Wickman Date: Wed, 24 Jun 2009 09:41:59 -0500 Subject: x86: Fix uv bau sending buffer initialization The initialization of the UV Broadcast Assist Unit's sending buffers was making an invalid assumption about the initialization of an MMR that defines its address. The BIOS will not be providing that MMR. So uv_activation_descriptor_init() should unconditionally set it. Tested on UV simulator. Signed-off-by: Cliff Wickman Cc: # for v2.6.30.x LKML-Reference: Signed-off-by: Ingo Molnar --- arch/x86/kernel/tlb_uv.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 124d40c575d..8ccabb8a2f6 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c @@ -711,7 +711,6 @@ uv_activation_descriptor_init(int node, int pnode) unsigned long pa; unsigned long m; unsigned long n; - unsigned long mmr_image; struct bau_desc *adp; struct bau_desc *ad2; @@ -727,12 +726,8 @@ uv_activation_descriptor_init(int node, int pnode) n = pa >> uv_nshift; m = pa & uv_mmask; - mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE); - if (mmr_image) { - uv_write_global_mmr64(pnode, (unsigned long) - UVH_LB_BAU_SB_DESCRIPTOR_BASE, - (n << UV_DESC_BASE_PNODE_SHIFT | m)); - } + uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, + (n << UV_DESC_BASE_PNODE_SHIFT | m)); /* * initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each -- cgit v1.2.3 From 7433ab770327b471399f7b5baacad78e160b5393 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 25 Jun 2009 02:30:10 +0900 Subject: sh: Hook up page fault events for software perf counters. This adds page fault instrumentation for the software performance counters. Follows the x86 and powerpc changes. Signed-off-by: Paul Mundt --- arch/sh/mm/fault_32.c | 61 +++++++++++++++++++++++++++------------------------ 1 file changed, 32 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index cc8ddbdf3d7..71925946f1e 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -15,12 +15,28 @@ #include #include #include -#include +#include #include #include #include #include +static inline int notify_page_fault(struct pt_regs *regs, int trap) +{ + int ret = 0; + +#ifdef CONFIG_KPROBES + if (!user_mode(regs)) { + preempt_disable(); + if (kprobe_running() && kprobe_fault_handler(regs, trap)) + ret = 1; + preempt_enable(); + } +#endif + + return ret; +} + /* * This routine handles page faults. It determines the address, * and the problem, and then passes it off to one of the appropriate @@ -87,13 +103,16 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, return; } + mm = tsk->mm; + + if (unlikely(notify_page_fault(regs, lookup_exception_vector()))) + return; + /* Only enable interrupts if they were on before the fault */ - if ((regs->sr & SR_IMASK) != SR_IMASK) { - trace_hardirqs_on(); + if ((regs->sr & SR_IMASK) != SR_IMASK) local_irq_enable(); - } - mm = tsk->mm; + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); /* * If we're in an interrupt or have no user @@ -141,10 +160,15 @@ survive: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) + if (fault & VM_FAULT_MAJOR) { tsk->maj_flt++; - else + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, + regs, address); + } else { tsk->min_flt++; + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, + regs, address); + } up_read(&mm->mmap_sem); return; @@ -245,22 +269,6 @@ do_sigbus: goto no_context; } -static inline int notify_page_fault(struct pt_regs *regs, int trap) -{ - int ret = 0; - -#ifdef CONFIG_KPROBES - if (!user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, trap)) - ret = 1; - preempt_enable(); - } -#endif - - return ret; -} - /* * Called with interrupts disabled. */ @@ -273,12 +281,7 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs, pmd_t *pmd; pte_t *pte; pte_t entry; - int ret = 0; - - if (notify_page_fault(regs, lookup_exception_vector())) - goto out; - - ret = 1; + int ret = 1; /* * We don't take page faults for P1, P2, and parts of P4, these -- cgit v1.2.3 From 0ca5921e791fb2011d4d6de787f6485b3900703d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 19 Jun 2009 13:51:28 +0100 Subject: MIPS: bug.h Build fix - include . In the past this file somehow used to be dragged in. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bug.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 08ea46863fe..6cf29c26e87 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -1,6 +1,7 @@ #ifndef __ASM_BUG_H #define __ASM_BUG_H +#include #include #ifdef CONFIG_BUG -- cgit v1.2.3 From 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 19 Jun 2009 14:05:26 +0100 Subject: MIPS: Build fix - include into all smp_processor_id() users. Some of the were relying into smp.h being dragged in by another header which of course is fragile. uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/octeon-irq.c | 2 +- arch/mips/cavium-octeon/setup.c | 1 + arch/mips/include/asm/bugs.h | 1 + arch/mips/include/asm/irq.h | 1 + arch/mips/include/asm/mmu_context.h | 1 + arch/mips/include/asm/smp.h | 1 + arch/mips/include/asm/sn/addrs.h | 1 + arch/mips/jazz/irq.c | 1 + arch/mips/kernel/cevt-bcm1480.c | 1 + arch/mips/kernel/cevt-r4k.c | 1 + arch/mips/kernel/cevt-sb1250.c | 1 + arch/mips/kernel/cevt-smtc.c | 1 + arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kernel/i8253.c | 1 + arch/mips/kernel/irq-gic.c | 1 + arch/mips/kernel/kgdb.c | 1 + arch/mips/kernel/smp-cmp.c | 1 + arch/mips/kernel/smp.c | 1 + arch/mips/kernel/smtc.c | 1 + arch/mips/mm/c-octeon.c | 1 + arch/mips/mm/c-r3k.c | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/c-tx39.c | 1 + arch/mips/mm/highmem.c | 1 + arch/mips/mm/init.c | 1 + arch/mips/mm/page.c | 1 + arch/mips/mm/tlb-r3k.c | 1 + arch/mips/mm/tlb-r4k.c | 1 + arch/mips/mm/tlb-r8k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/mti-malta/malta-int.c | 1 + arch/mips/pci/pci-ip27.c | 1 + arch/mips/pmc-sierra/yosemite/smp.c | 1 + arch/mips/sgi-ip27/ip27-init.c | 1 + arch/mips/sgi-ip27/ip27-irq.c | 1 + arch/mips/sgi-ip27/ip27-timer.c | 1 + arch/mips/sgi-ip27/ip27-xtalk.c | 1 + arch/mips/sibyte/bcm1480/irq.c | 1 + arch/mips/sni/time.c | 1 + 39 files changed, 39 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 8dfa009e007..3090ee37e10 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -7,7 +7,7 @@ */ #include #include -#include +#include #include #include diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 5f4e49ba471..da559249cc2 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include /* for memset */ #include diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index 9dc10df3207..b160a706795 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -11,6 +11,7 @@ #include #include +#include #include #include diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 4f1eed107b0..09b08d05ff7 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -10,6 +10,7 @@ #define _ASM_IRQ_H #include +#include #include diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d7f3eb03ad1..d3bea88d874 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 40e5ef1d4d2..2f83fa8631d 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -13,6 +13,7 @@ #include #include +#include #include #include diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h index 3a56d90abfa..2367b56dcde 100644 --- a/arch/mips/include/asm/sn/addrs.h +++ b/arch/mips/include/asm/sn/addrs.h @@ -11,6 +11,7 @@ #ifndef __ASSEMBLY__ +#include #include #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index d9b6a5b5399..7fd170d007e 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index a5182a20769..e02f79b1eb5 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 0015e442572..2652362ce04 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index 340f53e5c6b..ac5903d1b20 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c index df6f5bc6057..98bd7de7577 100644 --- a/arch/mips/kernel/cevt-smtc.c +++ b/arch/mips/kernel/cevt-smtc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b13b8eb3059..1abe9905c9c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index ed20e7fe65e..f7d8d5d0ddb 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 3f43c2e3aa5..39000f103f2 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -2,6 +2,7 @@ #include #include +#include #include #include diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 6e152c80cd4..50c9bb88066 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index f27beca4b26..653be061b9e 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index c937506a03a..58f4679bbd4 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 37d51cd124e..8a0626cbb10 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 44d01a0a849..b165cdcb281 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 5500c20c79a..54e5f7b9f44 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71fe4cb778c..6721ee2b1e8 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index f7c8f9ce39c..6515b441871 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 2b1309b2580..e274fda329f 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -1,5 +1,6 @@ #include #include +#include #include #include diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c5511294a9e..0e820508ff2 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 48060c635ac..f5c73754d66 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 1c0048a6f5c..0f5ab236ab6 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index f60fe513eb6..cee502caf39 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 4ec95cc2df2..2b82f23df1a 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 8f606ead826..9a17bf8395d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index ea176113fea..b4eaf137e4a 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index dda6f205866..a0e726eb039 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index f78c29b68d7..8ace2771623 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -1,5 +1,6 @@ #include #include +#include #include #include diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 4a500e8cd3c..51d3a4f2d7e 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 1bb692a3b31..c1c8e40d65d 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index f10a7cd64f7..6d0e59ffba2 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c index 6ae64e8dfc4..5e871e75a8d 100644 --- a/arch/mips/sgi-ip27/ip27-xtalk.c +++ b/arch/mips/sgi-ip27/ip27-xtalk.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 690de06bde9..ba59839a021 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 69f5f88711c..0d9ec1a5c24 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -1,5 +1,6 @@ #include #include +#include #include #include -- cgit v1.2.3 From 44eeab67416711db9b84610ef18c99a60415dff8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 19 Jun 2009 15:01:44 +0100 Subject: MIPS: Hibernation: Remove SMP TLB and cacheflushing code. We can't perform any flushes on SMP from swsusp_arch_resume because interrupts are disabled. A cross-CPU flush is unnecessary anyway because all but the local CPU have already been disabled. A local flush is not needed either because we didn't change any mappings. So just delete the code. Signed-off-by: Ralf Baechle --- arch/mips/power/hibernate.S | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch') diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S index 486bd3fd01a..4b8174b382d 100644 --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S @@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume) bne t1, t3, 1b PTR_L t0, PBE_NEXT(t0) bnez t0, 0b - /* flush caches to make sure context is in memory */ - PTR_L t0, __flush_cache_all - jalr t0 - /* flush tlb entries */ -#ifdef CONFIG_SMP - jal flush_tlb_all -#else - jal local_flush_tlb_all -#endif PTR_LA t0, saved_regs PTR_L ra, PT_R31(t0) PTR_L sp, PT_R29(t0) -- cgit v1.2.3 From ab7f6f3010a6c5ae147541168705a446cee511e7 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 22 Jun 2009 15:48:27 +0100 Subject: MIPS: MIPSsim: Fix build error if MSC01E_INT_BASE is undefined. This fixes kernel.org bugzilla 13595, see http://bugzilla.kernel.org/show_bug.cgi?id=13595 Reported-by: dvice_null@yahoo.com Signed-off-by: Ralf Baechle --- arch/mips/mipssim/sim_time.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 881ecbc1fa2..0cea932f124 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void) mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } else { #endif + { if (cpu_has_vint) set_vi_handler(cp0_compare_irq, mips_timer_dispatch); mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; -- cgit v1.2.3 From 2e25406fb878e2313a9d8e302ed7ff3c2831198f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 22 Jun 2009 16:17:52 +0100 Subject: MIPS: Sibyte: Fix build error if CONFIG_SERIAL_SB1250_DUART is undefined. This fixes kernel.org bugzilla 13596, see http://bugzilla.kernel.org/show_bug.cgi?id=13596 Reported-by: dvice_null@yahoo.com Signed-off-by: Ralf Baechle --- arch/mips/sibyte/common/cfe_console.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/sibyte/common/cfe_console.c b/arch/mips/sibyte/common/cfe_console.c index 81e3d54376e..1ad2da103fe 100644 --- a/arch/mips/sibyte/common/cfe_console.c +++ b/arch/mips/sibyte/common/cfe_console.c @@ -51,12 +51,13 @@ static int cfe_console_setup(struct console *cons, char *str) setleds("u0cn"); } else if (!strcmp(consdev, "uart1")) { setleds("u1cn"); + } else #endif #ifdef CONFIG_VGA_CONSOLE - } else if (!strcmp(consdev, "pcconsole0")) { - setleds("pccn"); -#endif + if (!strcmp(consdev, "pcconsole0")) { + setleds("pccn"); } else +#endif return -ENODEV; } return 0; -- cgit v1.2.3 From 1b2bc75c1bde6581d2694cb3ed7fb06b69685008 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 23 Jun 2009 10:00:31 +0100 Subject: MIPS: Add arch generic CPU hotplug Each platform has to add support for CPU hotplugging itself by providing suitable definitions for the cpu_disable and cpu_die of the smp_ops methods and setting SYS_SUPPORTS_HOTPLUG_CPU. A platform should only set SYS_SUPPORTS_HOTPLUG_CPU once all it's smp_ops definitions have the necessary changes. This patch contains the changes to the dummy smp_ops definition for uni-processor systems. Parts of the code contributed by Cavium Inc. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 11 ++++++++++- arch/mips/include/asm/smp-ops.h | 4 ++++ arch/mips/include/asm/smp.h | 19 +++++++++++++++++++ arch/mips/kernel/process.c | 13 ++++++++++++- arch/mips/kernel/smp-up.c | 16 ++++++++++++++++ arch/mips/kernel/smp.c | 17 +++++++++++++---- arch/mips/kernel/topology.c | 5 ++++- 7 files changed, 78 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b29f0280d71..eb7e8d795c6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -784,8 +784,17 @@ config SYS_HAS_EARLY_PRINTK bool config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs" + depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU + help + Say Y here to allow turning CPUs off and on. CPUs can be + controlled through /sys/devices/system/cpu. + (Note: power management support will enable this option + automatically on SMP systems. ) + Say N if you want to disable CPU hotplug. + +config SYS_SUPPORTS_HOTPLUG_CPU bool - default n config I8259 bool diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 64ffc0290b8..fd545547b8a 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -26,6 +26,10 @@ struct plat_smp_ops { void (*boot_secondary)(int cpu, struct task_struct *idle); void (*smp_setup)(void); void (*prepare_cpus)(unsigned int max_cpus); +#ifdef CONFIG_HOTPLUG_CPU + int (*cpu_disable)(void); + void (*cpu_die)(unsigned int cpu); +#endif }; extern void register_smp_ops(struct plat_smp_ops *ops); diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 2f83fa8631d..01f813dc388 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -41,6 +41,7 @@ extern int __cpu_logical_map[NR_CPUS]; /* Octeon - Tell another core to flush its icache */ #define SMP_ICACHE_FLUSH 0x4 +extern cpumask_t cpu_callin_map; extern void asmlinkage smp_bootstrap(void); @@ -56,6 +57,24 @@ static inline void smp_send_reschedule(int cpu) mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF); } +#ifdef CONFIG_HOTPLUG_CPU +static inline int __cpu_disable(void) +{ + extern struct plat_smp_ops *mp_ops; /* private */ + + return mp_ops->cpu_disable(); +} + +static inline void __cpu_die(unsigned int cpu) +{ + extern struct plat_smp_ops *mp_ops; /* private */ + + mp_ops->cpu_die(cpu); +} + +extern void play_dead(void); +#endif + extern asmlinkage void smp_call_function_interrupt(void); extern void arch_send_call_function_single_ipi(int cpu); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 1eaaa450e20..c09d681b718 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -50,10 +50,15 @@ */ void __noreturn cpu_idle(void) { + int cpu; + + /* CPU is going idle. */ + cpu = smp_processor_id(); + /* endless idle loop with no priority at all */ while (1) { tick_nohz_stop_sched_tick(1); - while (!need_resched()) { + while (!need_resched() && cpu_online(cpu)) { #ifdef CONFIG_MIPS_MT_SMTC extern void smtc_idle_loop_hook(void); @@ -62,6 +67,12 @@ void __noreturn cpu_idle(void) if (cpu_wait) (*cpu_wait)(); } +#ifdef CONFIG_HOTPLUG_CPU + if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) && + (system_state == SYSTEM_RUNNING || + system_state == SYSTEM_BOOTING)) + play_dead(); +#endif tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); schedule(); diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c index 878e3733bbb..2508d55d68f 100644 --- a/arch/mips/kernel/smp-up.c +++ b/arch/mips/kernel/smp-up.c @@ -55,6 +55,18 @@ static void __init up_prepare_cpus(unsigned int max_cpus) { } +#ifdef CONFIG_HOTPLUG_CPU +static int up_cpu_disable(void) +{ + return -ENOSYS; +} + +static void up_cpu_die(unsigned int cpu) +{ + BUG(); +} +#endif + struct plat_smp_ops up_smp_ops = { .send_ipi_single = up_send_ipi_single, .send_ipi_mask = up_send_ipi_mask, @@ -64,4 +76,8 @@ struct plat_smp_ops up_smp_ops = { .boot_secondary = up_boot_secondary, .smp_setup = up_smp_setup, .prepare_cpus = up_prepare_cpus, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = up_cpu_disable, + .cpu_die = up_cpu_die, +#endif }; diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 58f4679bbd4..bc7d9b05e2f 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -45,7 +45,7 @@ #include #endif /* CONFIG_MIPS_MT_SMTC */ -static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ +volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ @@ -201,6 +201,8 @@ void __devinit smp_prepare_boot_cpu(void) * and keep control until "cpu_online(cpu)" is set. Note: cpu is * physical, not logical. */ +static struct task_struct *cpu_idle_thread[NR_CPUS]; + int __cpuinit __cpu_up(unsigned int cpu) { struct task_struct *idle; @@ -210,9 +212,16 @@ int __cpuinit __cpu_up(unsigned int cpu) * The following code is purely to make sure * Linux can schedule processes on this slave. */ - idle = fork_idle(cpu); - if (IS_ERR(idle)) - panic(KERN_ERR "Fork failed for CPU %d", cpu); + if (!cpu_idle_thread[cpu]) { + idle = fork_idle(cpu); + cpu_idle_thread[cpu] = idle; + + if (IS_ERR(idle)) + panic(KERN_ERR "Fork failed for CPU %d", cpu); + } else { + idle = cpu_idle_thread[cpu]; + init_idle(idle, cpu); + } mp_ops->boot_secondary(cpu, idle); diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c index 660e44ed44d..cf3eb61fad1 100644 --- a/arch/mips/kernel/topology.c +++ b/arch/mips/kernel/topology.c @@ -17,7 +17,10 @@ static int __init topology_init(void) #endif /* CONFIG_NUMA */ for_each_present_cpu(i) { - ret = register_cpu(&per_cpu(cpu_devices, i), i); + struct cpu *c = &per_cpu(cpu_devices, i); + + c->hotpluggable = 1; + ret = register_cpu(c, i); if (ret) printk(KERN_WARNING "topology_init: register_cpu %d " "failed (%d)\n", i, ret); -- cgit v1.2.3 From 9801b321ecdb6708365b6825bf728c8e433fca00 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 23 Jun 2009 10:20:56 +0100 Subject: MIPS: SMP: Allow suspend and hibernation if CPU hotplug is available The SMP implementation of suspend and hibernate depends on CPU hotplugging. In the past we didn't have CPU hotplug so suspend and hibernation were not possible on SMP systems. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index eb7e8d795c6..3cce4ed5473 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2145,11 +2145,11 @@ menu "Power management options" config ARCH_HIBERNATION_POSSIBLE def_bool y - depends on !SMP + depends on SYS_SUPPORTS_HOTPLUG_CPU config ARCH_SUSPEND_POSSIBLE def_bool y - depends on !SMP + depends on SYS_SUPPORTS_HOTPLUG_CPU source "kernel/power/Kconfig" -- cgit v1.2.3 From 773cb77d0e32f0a3c36edf5aaeb9642c18038cd2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 23 Jun 2009 10:36:38 +0100 Subject: MIPS: Cavium: Add CPU hotplugging code. Thanks to Cavium Inc. for the code contribution and help. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/octeon-irq.c | 59 +++++++++ arch/mips/cavium-octeon/octeon_boot.h | 70 ++++++++++ arch/mips/cavium-octeon/smp.c | 234 +++++++++++++++++++++++++++++++++- arch/mips/include/asm/smp.h | 2 +- 5 files changed, 365 insertions(+), 2 deletions(-) create mode 100644 arch/mips/cavium-octeon/octeon_boot.h (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3cce4ed5473..8c4be1f301c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -601,6 +601,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_CPU_CAVIUM_OCTEON help The Octeon simulator is software performance model of the Cavium @@ -615,6 +616,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 3090ee37e10..384f1842bfb 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -501,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void) } } } + +#ifdef CONFIG_HOTPLUG_CPU +static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) +{ + unsigned int isset; +#ifdef CONFIG_SMP + int coreid = cpu_logical_map(cpu); +#else + int coreid = cvmx_get_core_num(); +#endif + int bit = (irq < OCTEON_IRQ_WDOG0) ? + irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; + if (irq < 64) { + isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & + (1ull << bit)) >> bit; + } else { + isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) & + (1ull << bit)) >> bit; + } + return isset; +} + +void fixup_irqs(void) +{ + int irq; + + for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) + octeon_irq_core_disable_local(irq); + + for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu0.disable(irq); + octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); + } + } + +#if 0 + for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++) + octeon_irq_mailbox_mask(irq); +#endif + for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu0.disable(irq); + octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); + } + } + + for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu1.disable(irq); + octeon_irq_ciu1_set_affinity(irq, &cpu_online_map); + } + } +} + +#endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h new file mode 100644 index 00000000000..0f7f84accf9 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_boot.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004, 2005 Cavium Networks + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __OCTEON_BOOT_H__ +#define __OCTEON_BOOT_H__ + +#include + +struct boot_init_vector { + uint32_t stack_addr; + uint32_t code_addr; + uint32_t app_start_func_addr; + uint32_t k0_val; + uint32_t flags; + uint32_t boot_info_addr; + uint32_t pad; + uint32_t pad2; +}; + +/* similar to bootloader's linux_app_boot_info but without global data */ +struct linux_app_boot_info { + uint32_t labi_signature; + uint32_t start_core0_addr; + uint32_t avail_coremask; + uint32_t pci_console_active; + uint32_t icache_prefetch_disable; + uint32_t InitTLBStart_addr; + uint32_t start_app_addr; + uint32_t cur_exception_base; + uint32_t no_mark_private_data; + uint32_t compact_flash_common_base_addr; + uint32_t compact_flash_attribute_base_addr; + uint32_t led_display_base_addr; +}; + +/* If not to copy a lot of bootloader's structures + here is only offset of requested member */ +#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c + +/* hardcoded in bootloader */ +#define LABI_ADDR_IN_BOOTLOADER 0x700 + +#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" + +#define LABI_SIGNATURE 0xAABBCCDD + +/* from uboot-headers/octeon_mem_map.h */ +#define EXCEPTION_BASE_INCR (4 * 1024) + /* Increment size for exception base addresses (4k minimum) */ +#define EXCEPTION_BASE_BASE 0 +#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800) +#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE) + +#endif /* __OCTEON_BOOT_H__ */ diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 24e0ad63980..0b891a9c625 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -5,6 +5,7 @@ * * Copyright (C) 2004-2008 Cavium Networks */ +#include #include #include #include @@ -19,10 +20,16 @@ #include +#include "octeon_boot.h" + volatile unsigned long octeon_processor_boot = 0xff; volatile unsigned long octeon_processor_sp; volatile unsigned long octeon_processor_gp; +#ifdef CONFIG_HOTPLUG_CPU +static unsigned int InitTLBStart_addr; +#endif + static irqreturn_t mailbox_interrupt(int irq, void *dev_id) { const int coreid = cvmx_get_core_num(); @@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) } /** - * Detect available CPUs, populate phys_cpu_present_map + * Detect available CPUs, populate cpu_possible_map */ +static void octeon_smp_hotplug_setup(void) +{ +#ifdef CONFIG_HOTPLUG_CPU + uint32_t labi_signature; + + labi_signature = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + labi_signature))); + if (labi_signature != LABI_SIGNATURE) + pr_err("The bootloader version on this board is incorrect\n"); + InitTLBStart_addr = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + InitTLBStart_addr))); +#endif +} + static void octeon_smp_setup(void) { const int coreid = cvmx_get_core_num(); @@ -91,6 +118,9 @@ static void octeon_smp_setup(void) cpus++; } } + cpu_present_map = cpu_possible_map; + + octeon_smp_hotplug_setup(); } /** @@ -128,6 +158,17 @@ static void octeon_init_secondary(void) const int coreid = cvmx_get_core_num(); union cvmx_ciu_intx_sum0 interrupt_enable; +#ifdef CONFIG_HOTPLUG_CPU + unsigned int cur_exception_base; + + cur_exception_base = cvmx_read64_uint32( + CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + cur_exception_base))); + /* cur_exception_base is incremented in bootloader after setting */ + write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR)); +#endif octeon_check_cpu_bist(); octeon_init_cvmcount(); /* @@ -199,6 +240,193 @@ static void octeon_cpus_done(void) #endif } +#ifdef CONFIG_HOTPLUG_CPU + +/* State of each CPU. */ +DEFINE_PER_CPU(int, cpu_state); + +extern void fixup_irqs(void); + +static DEFINE_SPINLOCK(smp_reserve_lock); + +static int octeon_cpu_disable(void) +{ + unsigned int cpu = smp_processor_id(); + + if (cpu == 0) + return -EBUSY; + + spin_lock(&smp_reserve_lock); + + cpu_clear(cpu, cpu_online_map); + cpu_clear(cpu, cpu_callin_map); + local_irq_disable(); + fixup_irqs(); + local_irq_enable(); + + flush_cache_all(); + local_flush_tlb_all(); + + spin_unlock(&smp_reserve_lock); + + return 0; +} + +static void octeon_cpu_die(unsigned int cpu) +{ + int coreid = cpu_logical_map(cpu); + uint32_t avail_coremask; + struct cvmx_bootmem_named_block_desc *block_desc; + +#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG + /* Disable the watchdog */ + cvmx_ciu_wdogx_t ciu_wdog; + ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu)); + ciu_wdog.s.mode = 0; + cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64); +#endif + + while (per_cpu(cpu_state, cpu) != CPU_DEAD) + cpu_relax(); + + /* + * This is a bit complicated strategics of getting/settig available + * cores mask, copied from bootloader + */ + /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ + block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); + + if (!block_desc) { + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof + (struct linux_app_boot_info, + avail_coremask))); + } else { /* alternative, already initialized */ + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); + } + + avail_coremask |= 1 << coreid; + + /* Setting avail_coremask for bootoct binary */ + if (!block_desc) { + cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + avail_coremask)), + avail_coremask); + } else { + cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK), + avail_coremask); + } + + pr_info("Reset core %d. Available Coremask = %x \n", coreid, + avail_coremask); + cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); + cvmx_write_csr(CVMX_CIU_PP_RST, 0); +} + +void play_dead(void) +{ + int coreid = cvmx_get_core_num(); + + idle_task_exit(); + octeon_processor_boot = 0xff; + per_cpu(cpu_state, coreid) = CPU_DEAD; + + while (1) /* core will be reset here */ + ; +} + +extern void kernel_entry(unsigned long arg1, ...); + +static void start_after_reset(void) +{ + kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ +} + +int octeon_update_boot_vector(unsigned int cpu) +{ + + int coreid = cpu_logical_map(cpu); + unsigned int avail_coremask; + struct cvmx_bootmem_named_block_desc *block_desc; + struct boot_init_vector *boot_vect = + (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 + + BOOTLOADER_BOOT_VECTOR); + + block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); + + if (!block_desc) { + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + avail_coremask))); + } else { /* alternative, already initialized */ + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); + } + + if (!(avail_coremask & (1 << coreid))) { + /* core not available, assume, that catched by simple-executive */ + cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); + cvmx_write_csr(CVMX_CIU_PP_RST, 0); + } + + boot_vect[coreid].app_start_func_addr = + (uint32_t) (unsigned long) start_after_reset; + boot_vect[coreid].code_addr = InitTLBStart_addr; + + CVMX_SYNC; + + cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); + + return 0; +} + +static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + + switch (action) { + case CPU_UP_PREPARE: + octeon_update_boot_vector(cpu); + break; + case CPU_ONLINE: + pr_info("Cpu %d online\n", cpu); + break; + case CPU_DEAD: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata octeon_cpu_notifier = { + .notifier_call = octeon_cpu_callback, +}; + +static int __cpuinit register_cavium_notifier(void) +{ + register_hotcpu_notifier(&octeon_cpu_notifier); + + return 0; +} + +late_initcall(register_cavium_notifier); + +#endif /* CONFIG_HOTPLUG_CPU */ + struct plat_smp_ops octeon_smp_ops = { .send_ipi_single = octeon_send_ipi_single, .send_ipi_mask = octeon_send_ipi_mask, @@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = { .boot_secondary = octeon_boot_secondary, .smp_setup = octeon_smp_setup, .prepare_cpus = octeon_prepare_cpus, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = octeon_cpu_disable, + .cpu_die = octeon_cpu_die, +#endif }; diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 01f813dc388..aaa2d4ab26d 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -41,7 +41,7 @@ extern int __cpu_logical_map[NR_CPUS]; /* Octeon - Tell another core to flush its icache */ #define SMP_ICACHE_FLUSH 0x4 -extern cpumask_t cpu_callin_map; +extern volatile cpumask_t cpu_callin_map; extern void asmlinkage smp_bootstrap(void); -- cgit v1.2.3 From 163b2f0ba93e9298b3d5fff2337d860c3872ec60 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 25 Jun 2009 02:49:03 +0900 Subject: sh64: Hook up page fault events for software perf counters. sh64 can use these as well, so tie them up there as well. Signed-off-by: Paul Mundt --- arch/sh/mm/tlbflush_64.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index fcbb6e135ce..3ce40ea3482 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -3,7 +3,7 @@ * * Copyright (C) 2000, 2001 Paolo Alberelli * Copyright (C) 2003 Richard Curnow (/proc/tlb, bug fixes) - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -115,6 +116,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess, /* Not an IO address, so reenable interrupts */ local_irq_enable(); + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); + /* * If we're in an interrupt or have no user * context, we must not take the fault.. @@ -195,10 +198,16 @@ survive: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) + + if (fault & VM_FAULT_MAJOR) { tsk->maj_flt++; - else + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, + regs, address); + } else { tsk->min_flt++; + perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, + regs, address); + } /* If we get here, the page fault has been handled. Do the TLB refill now from the newly-setup PTE, to avoid having to fault again right -- cgit v1.2.3 From 236e946b53ffd5e2f5d7e6abebbe72a9f0826d15 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 24 Jun 2009 16:23:03 -0700 Subject: Revert "PCI: use ACPI _CRS data by default" This reverts commit 9e9f46c44e487af0a82eb61b624553e2f7118f5b. Quoting from the commit message: "At this point, it seems to solve more problems than it causes, so let's try using it by default. It's an easy revert if it ends up causing trouble." And guess what? The _CRS code causes trouble. Signed-off-by: Linus Torvalds --- arch/x86/include/asm/pci_x86.h | 2 +- arch/x86/pci/acpi.c | 2 +- arch/x86/pci/amd_bus.c | 2 +- arch/x86/pci/common.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index d419f5c0266..b399988eee3 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -25,7 +25,7 @@ #define PCI_BIOS_IRQ_SCAN 0x2000 #define PCI_ASSIGN_ALL_BUSSES 0x4000 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 -#define PCI_NO_ROOT_CRS 0x10000 +#define PCI_USE__CRS 0x10000 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 #define PCI_HAS_IO_ECS 0x40000 #define PCI_NOASSIGN_ROMS 0x80000 diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index 16c3fda85bb..b26626dc517 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -238,7 +238,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do #endif } - if (bus && !(pci_probe & PCI_NO_ROOT_CRS)) + if (bus && (pci_probe & PCI_USE__CRS)) get_current_resources(device, busnum, domain, bus); return bus; } diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index 2255f880678..f893d6a6e80 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -101,7 +101,7 @@ void x86_pci_root_bus_res_quirks(struct pci_bus *b) struct pci_root_info *info; /* don't go for it if _CRS is used */ - if (!(pci_probe & PCI_NO_ROOT_CRS)) + if (pci_probe & PCI_USE__CRS) return; /* if only one root bus, don't need to anything */ diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 4740119e4bb..2202b6257b8 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -515,8 +515,8 @@ char * __devinit pcibios_setup(char *str) } else if (!strcmp(str, "assign-busses")) { pci_probe |= PCI_ASSIGN_ALL_BUSSES; return NULL; - } else if (!strcmp(str, "nocrs")) { - pci_probe |= PCI_NO_ROOT_CRS; + } else if (!strcmp(str, "use_crs")) { + pci_probe |= PCI_USE__CRS; return NULL; } else if (!strcmp(str, "earlydump")) { pci_early_dump_regs = 1; -- cgit v1.2.3 From 1fbcf37128cc19bd67d9a736fb634dc444e907d7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 25 Jun 2009 21:17:19 +0900 Subject: sh: Kill off unused DEBUG_BOOTMEM symbol. This was killed off in generic code some time ago, kill off the left over symbol. Signed-off-by: Paul Mundt --- arch/sh/Kconfig.debug | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 8ece0b5bd02..39224b57c6e 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -61,10 +61,6 @@ config EARLY_PRINTK select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using the kernel command line option to toggle back and forth. -config DEBUG_BOOTMEM - depends on DEBUG_KERNEL - bool "Debug BOOTMEM initialization" - config DEBUG_STACKOVERFLOW bool "Check for stack overflows" depends on DEBUG_KERNEL && SUPERH32 -- cgit v1.2.3 From 7aa5514e7170c6179272bc638a980adc1738fd29 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Mon, 22 Jun 2009 09:23:36 +0100 Subject: [ARM] 5560/1: Avoid buffer overrun in case of an invalid IRQ handle_bad_irq() expects the IRQ number to be valid (used for statistics), so it cannot be called with an illegal vector. The problem was reported by a static analysis tool. The change makes bad_irq_desc redundant, so delete it. Signed-off-by: Aaro Koskinen Signed-off-by: Russell King --- arch/arm/kernel/irq.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 096f600dc8d..b7c3490eaa2 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -98,17 +98,6 @@ unlock: return 0; } -/* Handle bad interrupts */ -static struct irq_desc bad_irq_desc = { - .handle_irq = handle_bad_irq, - .lock = __SPIN_LOCK_UNLOCKED(bad_irq_desc.lock), -}; - -#ifdef CONFIG_CPUMASK_OFFSTACK -/* We are not allocating bad_irq_desc.affinity or .pending_mask */ -#error "ARM architecture does not support CONFIG_CPUMASK_OFFSTACK." -#endif - /* * do_IRQ handles all hardware IRQ's. Decoded IRQs should not * come via this function. Instead, they should provide their @@ -124,10 +113,13 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) * Some hardware gives randomly wrong interrupts. Rather * than crashing, do something sensible. */ - if (irq >= NR_IRQS) - handle_bad_irq(irq, &bad_irq_desc); - else + if (unlikely(irq >= NR_IRQS)) { + if (printk_ratelimit()) + printk(KERN_WARNING "Bad IRQ%u\n", irq); + ack_bad_irq(irq); + } else { generic_handle_irq(irq); + } /* AT91 specific workaround */ irq_finish(irq); @@ -165,10 +157,6 @@ void __init init_IRQ(void) for (irq = 0; irq < NR_IRQS; irq++) irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; -#ifdef CONFIG_SMP - cpumask_setall(bad_irq_desc.affinity); - bad_irq_desc.node = smp_processor_id(); -#endif init_arch_irq(); } -- cgit v1.2.3 From f6430a938dc6d77e33722aaf6a58382b3423935d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 24 Jun 2009 23:38:56 +0100 Subject: [ARM] 5565/2: Use PAGE_SIZE and RO_DATA() in link script Update the link script for ARM to use PAGE_SIZE instead of hard- coded 4096. Also the old RODATA macro is deprecated for the RO_DATA(PAGE_SIZE) macro. As a consequence the PAGE_SIZE was changed from (1UL << PAGE_SHIFT) to (_AC(1,UL) << PAGE_SHIFT) because the linker does not understand the "UL" suffix to numeric constants. Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/include/asm/page.h | 2 +- arch/arm/kernel/vmlinux.lds.S | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index be962c1349c..9c746af1bf6 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -12,7 +12,7 @@ /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #ifndef __ASSEMBLY__ diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 4340bf3d2c8..69371028a20 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -6,6 +6,7 @@ #include #include #include +#include OUTPUT_ARCH(arm) ENTRY(stext) @@ -63,7 +64,7 @@ SECTIONS usr/built-in.o(.init.ramfs) __initramfs_end = .; #endif - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __per_cpu_load = .; __per_cpu_start = .; *(.data.percpu.page_aligned) @@ -73,7 +74,7 @@ SECTIONS #ifndef CONFIG_XIP_KERNEL __init_begin = _stext; INIT_DATA - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_end = .; #endif } @@ -118,7 +119,7 @@ SECTIONS *(.got) /* Global offset table */ } - RODATA + RO_DATA(PAGE_SIZE) _etext = .; /* End of text and rodata section */ @@ -158,17 +159,17 @@ SECTIONS *(.data.init_task) #ifdef CONFIG_XIP_KERNEL - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_begin = .; INIT_DATA - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_end = .; #endif - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_begin = .; *(.data.nosave) - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_end = .; /* -- cgit v1.2.3 From ab420e6d9c2511b862d753b70efb4e979faa0714 Mon Sep 17 00:00:00 2001 From: Paul Menage Date: Thu, 25 Jun 2009 00:17:15 -0700 Subject: UML: Fix some apparent bitrot UML: Fix some apparent bitrot - migration of net_device methods into net_device_ops - dma_sync_single() changes Signed-off-by: Paul Menage Acked-by: Amerigo Wang -- This version is split from my earlier patch, including just the portions that ar required for Linus' tree. Fixes the following compile errors: include/linux/dma-mapping.h:113: error: redefinition of 'dma_sync_single' arch/um/include/asm/dma-mapping.h:84: error: previous definition of 'dma_sync_single' was here include/linux/dma-mapping.h: In function 'dma_sync_single': include/linux/dma-mapping.h:117: error: implicit declaration of function 'dma_sync_single_for_cpu' include/linux/dma-mapping.h: At top level: include/linux/dma-mapping.h:120: error: redefinition of 'dma_sync_sg' arch/um/include/asm/dma-mapping.h:91: error: previous definition of 'dma_sync_sg' was here include/linux/dma-mapping.h: In function 'dma_sync_sg': include/linux/dma-mapping.h:124: error: implicit declaration of function 'dma_sync_sg_for_cpu' arch/um/drivers/slirp_kern.c: In function 'slirp_init': arch/um/drivers/slirp_kern.c:35: error: 'struct net_device' has no member named 'init' Signed-off-by: Linus Torvalds --- arch/um/drivers/slip_kern.c | 1 - arch/um/drivers/slirp_kern.c | 1 - arch/um/include/asm/dma-mapping.h | 4 ++-- 3 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/um/drivers/slip_kern.c b/arch/um/drivers/slip_kern.c index 5ec17563142..dd2aadc14af 100644 --- a/arch/um/drivers/slip_kern.c +++ b/arch/um/drivers/slip_kern.c @@ -30,7 +30,6 @@ static void slip_init(struct net_device *dev, void *data) slip_proto_init(&spri->slip); - dev->init = NULL; dev->hard_header_len = 0; dev->header_ops = NULL; dev->addr_len = 0; diff --git a/arch/um/drivers/slirp_kern.c b/arch/um/drivers/slirp_kern.c index f15a6e7654f..e376284f0fb 100644 --- a/arch/um/drivers/slirp_kern.c +++ b/arch/um/drivers/slirp_kern.c @@ -32,7 +32,6 @@ void slirp_init(struct net_device *dev, void *data) slip_proto_init(&spri->slip); - dev->init = NULL; dev->hard_header_len = 0; dev->header_ops = NULL; dev->addr_len = 0; diff --git a/arch/um/include/asm/dma-mapping.h b/arch/um/include/asm/dma-mapping.h index 90fc708b320..378de4bbf49 100644 --- a/arch/um/include/asm/dma-mapping.h +++ b/arch/um/include/asm/dma-mapping.h @@ -79,14 +79,14 @@ dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, } static inline void -dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { BUG(); } static inline void -dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { BUG(); -- cgit v1.2.3 From 194002b274e9169a04beb1b23dcc132159bb566c Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 22 Jun 2009 16:35:24 +0200 Subject: perf_counter, x86: Add mmap counter read support Update the mmap control page with the needed information to use the userspace RDPMC instruction for self monitoring. Signed-off-by: Peter Zijlstra LKML-Reference: Signed-off-by: Ingo Molnar --- arch/powerpc/include/asm/perf_counter.h | 2 ++ arch/x86/include/asm/perf_counter.h | 3 +++ arch/x86/kernel/cpu/perf_counter.c | 6 ++++++ 3 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h index 8ccd4e15576..0ea0639fcf7 100644 --- a/arch/powerpc/include/asm/perf_counter.h +++ b/arch/powerpc/include/asm/perf_counter.h @@ -61,6 +61,8 @@ struct pt_regs; extern unsigned long perf_misc_flags(struct pt_regs *regs); extern unsigned long perf_instruction_pointer(struct pt_regs *regs); +#define PERF_COUNTER_INDEX_OFFSET 1 + /* * Only override the default definitions in include/linux/perf_counter.h * if we have hardware PMU support. diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_counter.h index 5fb33e160ea..fa64e401589 100644 --- a/arch/x86/include/asm/perf_counter.h +++ b/arch/x86/include/asm/perf_counter.h @@ -87,6 +87,9 @@ union cpuid10_edx { #ifdef CONFIG_PERF_COUNTERS extern void init_hw_perf_counters(void); extern void perf_counters_lapic_init(void); + +#define PERF_COUNTER_INDEX_OFFSET 0 + #else static inline void init_hw_perf_counters(void) { } static inline void perf_counters_lapic_init(void) { } diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index a310d19faca..b83474b6021 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -912,6 +912,8 @@ x86_perf_counter_set_period(struct perf_counter *counter, err = checking_wrmsrl(hwc->counter_base + idx, (u64)(-left) & x86_pmu.counter_mask); + perf_counter_update_userpage(counter); + return ret; } @@ -1034,6 +1036,8 @@ try_generic: x86_perf_counter_set_period(counter, hwc, idx); x86_pmu.enable(hwc, idx); + perf_counter_update_userpage(counter); + return 0; } @@ -1126,6 +1130,8 @@ static void x86_pmu_disable(struct perf_counter *counter) x86_perf_counter_update(counter, hwc, idx); cpuc->counters[idx] = NULL; clear_bit(idx, cpuc->used_mask); + + perf_counter_update_userpage(counter); } /* -- cgit v1.2.3 From 5211a242d0cbdded372aee59da18f80552b0a80a Mon Sep 17 00:00:00 2001 From: Kurt Garloff Date: Wed, 24 Jun 2009 14:32:11 -0700 Subject: x86: Add sysctl to allow panic on IOCK NMI error This patch introduces a new sysctl: /proc/sys/kernel/panic_on_io_nmi which defaults to 0 (off). When enabled, the kernel panics when the kernel receives an NMI caused by an IO error. The IO error triggered NMI indicates a serious system condition, which could result in IO data corruption. Rather than contiuing, panicing and dumping might be a better choice, so one can figure out what's causing the IO error. This could be especially important to companies running IO intensive applications where corruption must be avoided, e.g. a bank's databases. [ SuSE has been shipping it for a while, it was done at the request of a large database vendor, for their users. ] Signed-off-by: Kurt Garloff Signed-off-by: Roberto Angelino Signed-off-by: Greg Kroah-Hartman Cc: "Eric W. Biederman" LKML-Reference: <20090624213211.GA11291@kroah.com> Signed-off-by: Ingo Molnar --- arch/x86/kernel/dumpstack.c | 1 + arch/x86/kernel/traps.c | 3 +++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 95ea5fa7d44..c8405718a4c 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -22,6 +22,7 @@ #include "dumpstack.h" int panic_on_unrecovered_nmi; +int panic_on_io_nmi; unsigned int code_bytes = 64; int kstack_depth_to_print = 3 * STACKSLOTS_PER_LINE; static int die_counter; diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index a0f48f5671c..5204332f475 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -346,6 +346,9 @@ io_check_error(unsigned char reason, struct pt_regs *regs) printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); show_registers(regs); + if (panic_on_io_nmi) + panic("NMI IOCK error: Not continuing"); + /* Re-enable the IOCK line, wait for a few seconds */ reason = (reason & 0xf) | 8; outb(reason, 0x61); -- cgit v1.2.3 From 5be6066a7f8d917db347d94f1b359b9b70dcb572 Mon Sep 17 00:00:00 2001 From: Hidetoshi Seto Date: Wed, 24 Jun 2009 09:21:10 +0900 Subject: x86, mce: percpu mcheck_timer should be pinned If CONFIG_NO_HZ + CONFIG_SMP, timer added via add_timer() might be migrated on other cpu. Use add_timer_on() instead. Avoids the following failure: Maciej Rutecki wrote: > > After normal boot I try: > > > > echo 1 > /sys/devices/system/machinecheck/machinecheck0/check_interval > > > > I found this in dmesg: > > > > [ 141.704025] ------------[ cut here ]------------ > > [ 141.704039] WARNING: at arch/x86/kernel/cpu/mcheck/mce.c:1102 > > mcheck_timer+0xf5/0x100() Reported-by: Maciej Rutecki Signed-off-by: Hidetoshi Seto Tested-by: Maciej Rutecki Acked-by: Andi Kleen Signed-off-by: H. Peter Anvin --- arch/x86/kernel/cpu/mcheck/mce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 284d1de968b..af425b83202 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1117,7 +1117,7 @@ static void mcheck_timer(unsigned long data) *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); t->expires = jiffies + *n; - add_timer(t); + add_timer_on(t, smp_processor_id()); } static void mce_do_trigger(struct work_struct *work) @@ -1321,7 +1321,7 @@ static void mce_init_timer(void) return; setup_timer(t, mcheck_timer, smp_processor_id()); t->expires = round_jiffies(jiffies + *n); - add_timer(t); + add_timer_on(t, smp_processor_id()); } /* -- cgit v1.2.3 From 22f4319d6bc0155e6c0ae560729baa6c09dc09e7 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Thu, 25 Jun 2009 16:20:48 -0400 Subject: x86, setup: Fix typo "CONFIG_x86_64" in CONFIG_X86_64 was misspelled (wrong case), which caused the x86-64 kernel to advertise itself as more relocatable than it really is. This could in theory cause boot failures once bootloaders start support the new relocation fields. Signed-off-by: Robert P. J. Day Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h index 418e632d4a8..6f02b9a5384 100644 --- a/arch/x86/include/asm/boot.h +++ b/arch/x86/include/asm/boot.h @@ -16,7 +16,7 @@ & ~(CONFIG_PHYSICAL_ALIGN - 1)) /* Minimum kernel alignment, as a power of two */ -#ifdef CONFIG_x86_64 +#ifdef CONFIG_X86_64 #define MIN_KERNEL_ALIGN_LG2 PMD_SHIFT #else #define MIN_KERNEL_ALIGN_LG2 (PAGE_SHIFT+1) -- cgit v1.2.3 From 658dbfeb5e7ab35d440c665d643a6285e43fddcd Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Thu, 25 Jun 2009 15:16:06 -0700 Subject: x86, setup: correct include file in needs , not in order to resolve PMD_SHIFT. Also, correct a +1 which really should be + THREAD_ORDER. This is a build error which was masked by a typoed #ifdef. Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/boot.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h index 6f02b9a5384..7a1065958ba 100644 --- a/arch/x86/include/asm/boot.h +++ b/arch/x86/include/asm/boot.h @@ -8,7 +8,7 @@ #ifdef __KERNEL__ -#include +#include /* Physical address where kernel should be loaded. */ #define LOAD_PHYSICAL_ADDR ((CONFIG_PHYSICAL_START \ @@ -19,7 +19,7 @@ #ifdef CONFIG_X86_64 #define MIN_KERNEL_ALIGN_LG2 PMD_SHIFT #else -#define MIN_KERNEL_ALIGN_LG2 (PAGE_SHIFT+1) +#define MIN_KERNEL_ALIGN_LG2 (PAGE_SHIFT + THREAD_ORDER) #endif #define MIN_KERNEL_ALIGN (_AC(1, UL) << MIN_KERNEL_ALIGN_LG2) -- cgit v1.2.3 From e888d7facd1f1460a638151036d15b6cfb3ccc74 Mon Sep 17 00:00:00 2001 From: "Pallipadi, Venkatesh" Date: Thu, 25 Jun 2009 16:44:31 -0700 Subject: x86, delay: tsc based udelay should have rdtsc_barrier delay_tsc needs rdtsc_barrier to provide proper delay. Output from a test driver using hpet to cross check delay provided by udelay(). Before: [ 86.794363] Expected delay 5us actual 4679ns [ 87.154362] Expected delay 5us actual 698ns [ 87.514162] Expected delay 5us actual 4539ns [ 88.653716] Expected delay 5us actual 4539ns [ 94.664106] Expected delay 10us actual 9638ns [ 95.049351] Expected delay 10us actual 10126ns [ 95.416110] Expected delay 10us actual 9568ns [ 95.799216] Expected delay 10us actual 9638ns [ 103.624104] Expected delay 10us actual 9707ns [ 104.020619] Expected delay 10us actual 768ns [ 104.419951] Expected delay 10us actual 9707ns After: [ 50.983320] Expected delay 5us actual 5587ns [ 51.261807] Expected delay 5us actual 5587ns [ 51.565715] Expected delay 5us actual 5657ns [ 51.861171] Expected delay 5us actual 5587ns [ 52.164704] Expected delay 5us actual 5726ns [ 52.487457] Expected delay 5us actual 5657ns [ 52.789338] Expected delay 5us actual 5726ns [ 57.119680] Expected delay 10us actual 10755ns [ 57.893997] Expected delay 10us actual 10615ns [ 58.261287] Expected delay 10us actual 10755ns [ 58.620505] Expected delay 10us actual 10825ns [ 58.941035] Expected delay 10us actual 10755ns [ 59.320903] Expected delay 10us actual 10615ns [ 61.306311] Expected delay 10us actual 10755ns [ 61.520542] Expected delay 10us actual 10615ns Signed-off-by: Venkatesh Pallipadi Signed-off-by: H. Peter Anvin --- arch/x86/lib/delay.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index f4568605d7d..ff485d36118 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -55,8 +55,10 @@ static void delay_tsc(unsigned long loops) preempt_disable(); cpu = smp_processor_id(); + rdtsc_barrier(); rdtscl(bclock); for (;;) { + rdtsc_barrier(); rdtscl(now); if ((now - bclock) >= loops) break; @@ -78,6 +80,7 @@ static void delay_tsc(unsigned long loops) if (unlikely(cpu != smp_processor_id())) { loops -= (now - bclock); cpu = smp_processor_id(); + rdtsc_barrier(); rdtscl(bclock); } } -- cgit v1.2.3 From 14a2ff6ed28931f796d2c2c8a440227a5d90f441 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 25 Jun 2009 19:00:47 -0700 Subject: sparc64: Don't use alloc_bootmem() in init_IRQ() code paths. The page allocator and SLAB are available at this point now, and if we still try to use bootmem allocations here the kernel spits out warnings. Signed-off-by: David S. Miller --- arch/sparc/kernel/irq_64.c | 45 +++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index bd075054942..f0ee7905540 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -914,25 +913,19 @@ void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu) tb->nonresum_qmask); } -static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) -{ - unsigned long size = PAGE_ALIGN(qmask + 1); - void *p = __alloc_bootmem(size, size, 0); - if (!p) { - prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); - prom_halt(); - } - - *pa_ptr = __pa(p); -} - -static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) +/* Each queue region must be a power of 2 multiple of 64 bytes in + * size. The base real address must be aligned to the size of the + * region. Thus, an 8KB queue must be 8KB aligned, for example. + */ +static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask) { unsigned long size = PAGE_ALIGN(qmask + 1); - void *p = __alloc_bootmem(size, size, 0); + unsigned long order = get_order(size); + unsigned long p; + p = __get_free_pages(GFP_KERNEL, order); if (!p) { - prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); + prom_printf("SUN4V: Error, cannot allocate queue.\n"); prom_halt(); } @@ -942,11 +935,11 @@ static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) { #ifdef CONFIG_SMP - void *page; + unsigned long page; BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); - page = alloc_bootmem_pages(PAGE_SIZE); + page = get_zeroed_page(GFP_KERNEL); if (!page) { prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); prom_halt(); @@ -965,13 +958,13 @@ static void __init sun4v_init_mondo_queues(void) for_each_possible_cpu(cpu) { struct trap_per_cpu *tb = &trap_block[cpu]; - alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); - alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); - alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); - alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); - alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); - alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, - tb->nonresum_qmask); + alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); + alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask); + alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask); + alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask); + alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask); + alloc_one_queue(&tb->nonresum_kernel_buf_pa, + tb->nonresum_qmask); } } @@ -999,7 +992,7 @@ void __init init_IRQ(void) kill_prom_timer(); size = sizeof(struct ino_bucket) * NUM_IVECS; - ivector_table = alloc_bootmem(size); + ivector_table = kzalloc(size, GFP_KERNEL); if (!ivector_table) { prom_printf("Fatal error, cannot allocate ivector_table\n"); prom_halt(); -- cgit v1.2.3 From 413ee282a510afb2f18975a189501f39d279a906 Mon Sep 17 00:00:00 2001 From: Julian Calaby Date: Sun, 21 Jun 2009 16:44:13 +0000 Subject: sparc64: Fix build warnings in piggyback_64.c This patch fixes the following build warnings: arch/sparc/boot/piggyback_64.c: In function 'main': arch/sparc/boot/piggyback_64.c:44: warning: 'end' may be used uninitialized in this function arch/sparc/boot/piggyback_64.c:44: warning: 'start' may be used uninitialized in this function Signed-off-by: Julian Calaby Signed-off-by: David S. Miller --- arch/sparc/boot/piggyback_64.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sparc/boot/piggyback_64.c b/arch/sparc/boot/piggyback_64.c index de364bfed0b..c63fd1b6bdd 100644 --- a/arch/sparc/boot/piggyback_64.c +++ b/arch/sparc/boot/piggyback_64.c @@ -46,6 +46,7 @@ int main(int argc,char **argv) struct stat s; int image, tail; + start = end = 0; if (stat (argv[3], &s) < 0) die (argv[3]); map = fopen (argv[2], "r"); if (!map) die(argv[2]); -- cgit v1.2.3 From 22b096a8907e5184f25fafd1b73f0b3633d52495 Mon Sep 17 00:00:00 2001 From: Robert Reif Date: Sun, 21 Jun 2009 16:45:44 +0000 Subject: sparc32: Fix obvious build issues for tftpboot.img build. Signed-off-by: Robert Reif Signed-off-by: David S. Miller --- arch/sparc/boot/Makefile | 2 +- arch/sparc/boot/piggyback_32.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index 96041a8d39e..5e2caeb3110 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -58,7 +58,7 @@ $(obj)/image: $(obj)/btfix.o FORCE $(obj)/zImage: $(obj)/image $(call if_changed,strip) -$(obj)/tftpboot.img: $(obj)/piggyback $(obj)/System.map $(obj)/image FORCE +$(obj)/tftpboot.img: $(obj)/piggyback_32 $(obj)/System.map $(obj)/image FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) diff --git a/arch/sparc/boot/piggyback_32.c b/arch/sparc/boot/piggyback_32.c index c9f500c1a8b..3f0f9335454 100644 --- a/arch/sparc/boot/piggyback_32.c +++ b/arch/sparc/boot/piggyback_32.c @@ -70,7 +70,7 @@ void die(char *str) int main(int argc,char **argv) { static char aout_magic[] = { 0x01, 0x03, 0x01, 0x07 }; - unsigned char buffer[1024], *q, *r; + char buffer[1024], *q, *r; unsigned int i, j, k, start, end, offset; FILE *map; struct stat s; -- cgit v1.2.3 From 52da82cfb569b44e26e15395a6727277758580fe Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 21 Jun 2009 16:46:10 +0000 Subject: sparc: fix tftpboot.img build Kjetil Oftedal mentioned that piggyback_32 was failing when building a sparc image. I tracked this down to the fact that the kernel no longer provided an absolute symbol named "end". Commit 86ed40bd6fe511d26bb8f3fa65a84cb65c235366 ("sparc: unify sections.h") renamed end to _end but failed to update piggyback_32. Signed-off-by: Sam Ravnborg Cc: Kjetil Oftedal Cc: Robert Reif Signed-off-by: Julian Calaby Signed-off-by: David S. Miller --- arch/sparc/boot/piggyback_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sparc/boot/piggyback_32.c b/arch/sparc/boot/piggyback_32.c index 3f0f9335454..e8dc9adfcd6 100644 --- a/arch/sparc/boot/piggyback_32.c +++ b/arch/sparc/boot/piggyback_32.c @@ -84,7 +84,7 @@ int main(int argc,char **argv) while (fgets (buffer, 1024, map)) { if (!strcmp (buffer + 8, " T start\n") || !strcmp (buffer + 16, " T start\n")) start = strtoul (buffer, NULL, 16); - else if (!strcmp (buffer + 8, " A end\n") || !strcmp (buffer + 16, " A end\n")) + else if (!strcmp (buffer + 8, " A _end\n") || !strcmp (buffer + 16, " A _end\n")) end = strtoul (buffer, NULL, 16); } fclose (map); -- cgit v1.2.3 From 3e05c5e2ce40066582dc34aa8335baa328815a09 Mon Sep 17 00:00:00 2001 From: Julian Calaby Date: Sun, 21 Jun 2009 16:45:01 +0000 Subject: sparc32: Fix tftpboot.img Makefile Signed-off-by: Julian Calaby Signed-off-by: David S. Miller --- arch/sparc/boot/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index 5e2caeb3110..500a2f87f28 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -15,7 +15,7 @@ quiet_cmd_elftoaout = ELFTOAOUT $@ ifeq ($(CONFIG_SPARC32),y) quiet_cmd_piggy = PIGGY $@ - cmd_piggy = $(obj)/piggyback_32 $@ $(obj)/System.map $(ROOT_IMG) + cmd_piggy = $(obj)/piggyback_32 $@ System.map $(ROOT_IMG) quiet_cmd_btfix = BTFIX $@ cmd_btfix = $(OBJDUMP) -x vmlinux | $(obj)/btfixupprep > $@ quiet_cmd_sysmap = SYSMAP $(obj)/System.map @@ -58,7 +58,7 @@ $(obj)/image: $(obj)/btfix.o FORCE $(obj)/zImage: $(obj)/image $(call if_changed,strip) -$(obj)/tftpboot.img: $(obj)/piggyback_32 $(obj)/System.map $(obj)/image FORCE +$(obj)/tftpboot.img: $(obj)/piggyback_32 System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) -- cgit v1.2.3 From 8944146daa2c38dd85bc489d1b84fb9abc108837 Mon Sep 17 00:00:00 2001 From: Julian Calaby Date: Tue, 23 Jun 2009 01:45:46 +0000 Subject: sparc32: Fix makefile not generating required files The tftpboot build was failing with missing file errors. It turns out that $(obj)/image wasn't being generated which was causing the a.out conversion to be skipped and hence piggyback to be called with nonexistent files. Signed-off-by: Julian Calaby Signed-off-by: David S. Miller --- arch/sparc/boot/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index 500a2f87f28..1ff0fd92475 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -58,7 +58,7 @@ $(obj)/image: $(obj)/btfix.o FORCE $(obj)/zImage: $(obj)/image $(call if_changed,strip) -$(obj)/tftpboot.img: $(obj)/piggyback_32 System.map $(ROOT_IMG) FORCE +$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_32 System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) @@ -79,7 +79,7 @@ $(obj)/image: vmlinux FORCE $(call if_changed,strip) @echo ' kernel: $@ is ready' -$(obj)/tftpboot.img: vmlinux $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE +$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) @echo ' kernel: $@ is ready' -- cgit v1.2.3 From 6f0b1c6094b3e8eeeb13f8f16c1b2ef452a6f519 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Mon, 22 Jun 2009 23:13:48 +0000 Subject: powerpc: Swiotlb breaks pseries Turning on SWIOTLB selects or enables PPC_NEED_DMA_SYNC_OPS, which means we get the non empty versions of dma_sync_* in asm/dma-mapping.h On my pseries machine the dma_ops have no such routines and we die with a null pointer - this patch gets it booting, is there a more elegant way to do it? Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/dma-mapping.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 3d9e887c3c0..b44aaabdd1a 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -309,7 +309,9 @@ static inline void dma_sync_single_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, + + if (dma_ops->sync_single_range_for_cpu) + dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, size, direction); } @@ -320,7 +322,9 @@ static inline void dma_sync_single_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_device(dev, dma_handle, + + if (dma_ops->sync_single_range_for_device) + dma_ops->sync_single_range_for_device(dev, dma_handle, 0, size, direction); } @@ -331,7 +335,9 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); + + if (dma_ops->sync_sg_for_cpu) + dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); } static inline void dma_sync_sg_for_device(struct device *dev, @@ -341,7 +347,9 @@ static inline void dma_sync_sg_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_sg_for_device(dev, sgl, nents, direction); + + if (dma_ops->sync_sg_for_device) + dma_ops->sync_sg_for_device(dev, sgl, nents, direction); } static inline void dma_sync_single_range_for_cpu(struct device *dev, @@ -351,7 +359,9 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_cpu(dev, dma_handle, + + if (dma_ops->sync_single_range_for_cpu) + dma_ops->sync_single_range_for_cpu(dev, dma_handle, offset, size, direction); } @@ -362,7 +372,9 @@ static inline void dma_sync_single_range_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_device(dev, dma_handle, offset, + + if (dma_ops->sync_single_range_for_device) + dma_ops->sync_single_range_for_device(dev, dma_handle, offset, size, direction); } #else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */ -- cgit v1.2.3 From 5a2642f620eb6e40792822fa0eafe23046fbb55e Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 22 Jun 2009 16:47:59 +0000 Subject: powerpc/mpic: Fix mapping of "DCR" based MPIC variants Commit 31207dab7d2e63795eb15823947bd2f7025b08e2 "Fix incorrect allocation of interrupt rev-map" introduced a regression crashing on boot on machines using a "DCR" based MPIC, such as the Cell blades. The reason is that the irq host data structure is initialized much later as a result of that patch, causing our calls to mpic_map() do be done before we have a host setup. Unfortunately, this breaks _mpic_map_dcr() which uses the mpic->irqhost to get to the device node. This fixes it by, instead, passing the device node explicitely to mpic_map(). Signed-off-by: Benjamin Herrenschmidt Acked-by: Akira Tsukamoto --- arch/powerpc/sysdev/mpic.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9c3af504549..32a2e950f56 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, } #ifdef CONFIG_PPC_DCR -static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, +static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, + struct mpic_reg_bank *rb, unsigned int offset, unsigned int size) { const u32 *dbasep; - dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); + dbasep = of_get_property(node, "dcr-reg", NULL); - rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); + rb->dhost = dcr_map(node, *dbasep + offset, size); BUG_ON(!DCR_MAP_OK(rb->dhost)); } -static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, - struct mpic_reg_bank *rb, unsigned int offset, - unsigned int size) +static inline void mpic_map(struct mpic *mpic, struct device_node *node, + phys_addr_t phys_addr, struct mpic_reg_bank *rb, + unsigned int offset, unsigned int size) { if (mpic->flags & MPIC_USES_DCR) - _mpic_map_dcr(mpic, rb, offset, size); + _mpic_map_dcr(mpic, node, rb, offset, size); else _mpic_map_mmio(mpic, phys_addr, rb, offset, size); } #else /* CONFIG_PPC_DCR */ -#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) +#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) #endif /* !CONFIG_PPC_DCR */ @@ -1152,8 +1153,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, } /* Map the global registers */ - mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); - mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); + mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); + mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); /* Reset */ if (flags & MPIC_WANTS_RESET) { @@ -1194,7 +1195,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, /* Map the per-CPU registers */ for (i = 0; i < mpic->num_cpus; i++) { - mpic_map(mpic, paddr, &mpic->cpuregs[i], + mpic_map(mpic, node, paddr, &mpic->cpuregs[i], MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 0x1000); } @@ -1202,7 +1203,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, /* Initialize main ISU if none provided */ if (mpic->isu_size == 0) { mpic->isu_size = mpic->num_sources; - mpic_map(mpic, paddr, &mpic->isus[0], + mpic_map(mpic, node, paddr, &mpic->isus[0], MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); } mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); @@ -1256,8 +1257,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, BUG_ON(isu_num >= MPIC_MAX_ISU); - mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, + mpic_map(mpic, mpic->irqhost->of_node, + paddr, &mpic->isus[isu_num], 0, MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); + if ((isu_first + mpic->isu_size) > mpic->num_sources) mpic->num_sources = isu_first + mpic->isu_size; } -- cgit v1.2.3 From b810c6ec5c659c80b3641580b112db877a0f1f45 Mon Sep 17 00:00:00 2001 From: Jon Smirl Date: Sun, 21 Jun 2009 15:28:00 +0000 Subject: powerpc: Have git ignore generated files from dtc compile Have git ignore generated files from dtc compile Signed-off-by: Jon Smirl Acked-by: David Gibson Acked-by: Sean MacLennan Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/boot/.gitignore | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore index 2f50acd11a6..3d80c3e9cf6 100644 --- a/arch/powerpc/boot/.gitignore +++ b/arch/powerpc/boot/.gitignore @@ -36,3 +36,13 @@ zImage.pseries zconf.h zlib.h zutil.h +fdt.c +fdt.h +fdt_ro.c +fdt_rw.c +fdt_strerror.c +fdt_sw.c +fdt_wip.c +libfdt.h +libfdt_internal.h + -- cgit v1.2.3 From 3984114f056203d833251af85501721f7b00fd18 Mon Sep 17 00:00:00 2001 From: Sean MacLennan Date: Fri, 19 Jun 2009 19:43:59 +0000 Subject: powerpc/warp: Platform fix for i2c change A change to the i2c subsystem breaks the warp platform code. The patch is cleaner anyway, the old way was a bit crufty. For those with keen eyes, the gratuitous change in the string from PIKA to Warp is just so the logs look a bit nicer. The following two lines tend to be printed one after another. Warp POST OK Warp DTM thread running. Yeah, this will be the third patch to warp.c submitted in this release.... Cheers, Sean The i2c_client struct changed, breaking the code that looked for the ad7414 chip. Use the new of_find_i2c_device_by_node function added in 2.6.29. Signed-off-by: Sean MacLennan Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/44x/warp.c | 44 +++++++++++++-------------------------- 1 file changed, 14 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c index 42e09a9f77e..0362c88f47d 100644 --- a/arch/powerpc/platforms/44x/warp.c +++ b/arch/powerpc/platforms/44x/warp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -65,7 +66,6 @@ define_machine(warp) { static u32 post_info; -/* I am not sure this is the best place for this... */ static int __init warp_post_info(void) { struct device_node *np; @@ -194,9 +194,9 @@ static int pika_setup_leds(void) return 0; } -static void pika_setup_critical_temp(struct i2c_client *client) +static void pika_setup_critical_temp(struct device_node *np, + struct i2c_client *client) { - struct device_node *np; int irq, rc; /* Do this before enabling critical temp interrupt since we @@ -208,14 +208,7 @@ static void pika_setup_critical_temp(struct i2c_client *client) i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */ - np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); - if (np == NULL) { - printk(KERN_ERR __FILE__ ": Unable to find ad7414\n"); - return; - } - irq = irq_of_parse_and_map(np, 0); - of_node_put(np); if (irq == NO_IRQ) { printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n"); return; @@ -244,32 +237,24 @@ static inline void pika_dtm_check_fan(void __iomem *fpga) static int pika_dtm_thread(void __iomem *fpga) { - struct i2c_adapter *adap; + struct device_node *np; struct i2c_client *client; - /* We loop in case either driver was compiled as a module and - * has not been insmoded yet. - */ - while (!(adap = i2c_get_adapter(0))) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(HZ); - } - - while (1) { - list_for_each_entry(client, &adap->clients, list) - if (client->addr == 0x4a) - goto found_it; + np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); + if (np == NULL) + return -ENOENT; - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(HZ); + client = of_find_i2c_device_by_node(np); + if (client == NULL) { + of_node_put(np); + return -ENOENT; } -found_it: - pika_setup_critical_temp(client); + pika_setup_critical_temp(np, client); - i2c_put_adapter(adap); + of_node_put(np); - printk(KERN_INFO "PIKA DTM thread running.\n"); + printk(KERN_INFO "Warp DTM thread running.\n"); while (!kthread_should_stop()) { int val; @@ -291,7 +276,6 @@ found_it: return 0; } - static int __init pika_dtm_start(void) { struct task_struct *dtm_thread; -- cgit v1.2.3 From 6bb2ae535f2eee0334802724a542701bd969d055 Mon Sep 17 00:00:00 2001 From: Gerhard Pircher Date: Fri, 19 Jun 2009 11:42:36 +0000 Subject: powerpc/amigaone: Limit ISA I/O range to 4k in the device tree The kernel reserves the I/O address space from 0x0 to 0xfff for legacy ISA devices. Change the ranges property for the PCI2ISA bridge to match the kernels behavior, even if the ranges property isn't used for now. Signed-off-by: Gerhard Pircher Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/boot/dts/amigaone.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/boot/dts/amigaone.dts b/arch/powerpc/boot/dts/amigaone.dts index 26549fca2ed..49ac36b16dd 100644 --- a/arch/powerpc/boot/dts/amigaone.dts +++ b/arch/powerpc/boot/dts/amigaone.dts @@ -70,8 +70,8 @@ devsel-speed = <0x00000001>; min-grant = <0>; max-latency = <0>; - /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ - ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>; + /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ + ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; interrupt-parent = <&i8259>; #interrupt-cells = <2>; #address-cells = <2>; -- cgit v1.2.3 From 7ccbe504b5ee766d33211a507189a06f3079b29b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 18 Jun 2009 23:30:07 +0000 Subject: powerpc/pmac: Fix issues with PowerMac "PowerSurge" SMP The old PowerSurge SMP (ie, dual or quad 604 machines) code has numerous issues in modern world. One is cpu_possible_map is set too late (the device-tree is bogus) so we fail to allocate the interrupt stacks and crash. Another problem is the fact the timebase is frozen by the bringup of the second CPU so the delays in the generic code will hang, we need to move some of the calling procedure to inside the powermac code. This makes it boot again for me Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/smp.c | 3 +- arch/powerpc/platforms/powermac/setup.c | 41 ++------ arch/powerpc/platforms/powermac/smp.c | 166 ++++++++++++++++++++------------ 3 files changed, 112 insertions(+), 98 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 65484b2200b..0b47de07302 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -68,7 +68,8 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map); /* SMP operations for this machine */ struct smp_ops_t *smp_ops; -static volatile unsigned int cpu_callin_map[NR_CPUS]; +/* Can't be static due to PowerMac hackery */ +volatile unsigned int cpu_callin_map[NR_CPUS]; int smt_enabled_at_boot = 1; diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index 86f69a4eb49..c2052265636 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c @@ -103,11 +103,6 @@ unsigned long smu_cmdbuf_abs; EXPORT_SYMBOL(smu_cmdbuf_abs); #endif -#ifdef CONFIG_SMP -extern struct smp_ops_t psurge_smp_ops; -extern struct smp_ops_t core99_smp_ops; -#endif /* CONFIG_SMP */ - static void pmac_show_cpuinfo(struct seq_file *m) { struct device_node *np; @@ -341,34 +336,6 @@ static void __init pmac_setup_arch(void) ROOT_DEV = DEFAULT_ROOT_DEVICE; #endif -#ifdef CONFIG_SMP - /* Check for Core99 */ - ic = of_find_node_by_name(NULL, "uni-n"); - if (!ic) - ic = of_find_node_by_name(NULL, "u3"); - if (!ic) - ic = of_find_node_by_name(NULL, "u4"); - if (ic) { - of_node_put(ic); - smp_ops = &core99_smp_ops; - } -#ifdef CONFIG_PPC32 - else { - /* - * We have to set bits in cpu_possible_map here since the - * secondary CPU(s) aren't in the device tree, and - * setup_per_cpu_areas only allocates per-cpu data for - * CPUs in the cpu_possible_map. - */ - int cpu; - - for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) - cpu_set(cpu, cpu_possible_map); - smp_ops = &psurge_smp_ops; - } -#endif -#endif /* CONFIG_SMP */ - #ifdef CONFIG_ADB if (strstr(cmd_line, "adb_sync")) { extern int __adb_probe_sync; @@ -512,6 +479,14 @@ static void __init pmac_init_early(void) #ifdef CONFIG_PPC64 iommu_init_early_dart(); #endif + + /* SMP Init has to be done early as we need to patch up + * cpu_possible_map before interrupt stacks are allocated + * or kaboom... + */ +#ifdef CONFIG_SMP + pmac_setup_smp(); +#endif } static int __init pmac_declare_of_platform_devices(void) diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index cf1dbe75889..6d4da7b46b4 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -64,10 +64,11 @@ extern void __secondary_start_pmac_0(void); extern int pmac_pfunc_base_install(void); -#ifdef CONFIG_PPC32 +static void (*pmac_tb_freeze)(int freeze); +static u64 timebase; +static int tb_req; -/* Sync flag for HW tb sync */ -static volatile int sec_tb_reset = 0; +#ifdef CONFIG_PPC32 /* * Powersurge (old powermac SMP) support. @@ -294,6 +295,9 @@ static int __init smp_psurge_probe(void) psurge_quad_init(); /* All released cards using this HW design have 4 CPUs */ ncpus = 4; + /* No sure how timebase sync works on those, let's use SW */ + smp_ops->give_timebase = smp_generic_give_timebase; + smp_ops->take_timebase = smp_generic_take_timebase; } else { iounmap(quad_base); if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { @@ -308,18 +312,15 @@ static int __init smp_psurge_probe(void) psurge_start = ioremap(PSURGE_START, 4); psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); - /* - * This is necessary because OF doesn't know about the + /* This is necessary because OF doesn't know about the * secondary cpu(s), and thus there aren't nodes in the * device tree for them, and smp_setup_cpu_maps hasn't - * set their bits in cpu_possible_map and cpu_present_map. + * set their bits in cpu_present_map. */ if (ncpus > NR_CPUS) ncpus = NR_CPUS; - for (i = 1; i < ncpus ; ++i) { + for (i = 1; i < ncpus ; ++i) cpu_set(i, cpu_present_map); - set_hard_smp_processor_id(i, i); - } if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); @@ -329,8 +330,14 @@ static int __init smp_psurge_probe(void) static void __init smp_psurge_kick_cpu(int nr) { unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; - unsigned long a; - int i; + unsigned long a, flags; + int i, j; + + /* Defining this here is evil ... but I prefer hiding that + * crap to avoid giving people ideas that they can do the + * same. + */ + extern volatile unsigned int cpu_callin_map[NR_CPUS]; /* may need to flush here if secondary bats aren't setup */ for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) @@ -339,47 +346,52 @@ static void __init smp_psurge_kick_cpu(int nr) if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); + /* This is going to freeze the timeebase, we disable interrupts */ + local_irq_save(flags); + out_be32(psurge_start, start); mb(); psurge_set_ipi(nr); + /* * We can't use udelay here because the timebase is now frozen. */ for (i = 0; i < 2000; ++i) - barrier(); + asm volatile("nop" : : : "memory"); psurge_clr_ipi(nr); - if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); -} - -/* - * With the dual-cpu powersurge board, the decrementers and timebases - * of both cpus are frozen after the secondary cpu is started up, - * until we give the secondary cpu another interrupt. This routine - * uses this to get the timebases synchronized. - * -- paulus. - */ -static void __init psurge_dual_sync_tb(int cpu_nr) -{ - int t; - - set_dec(tb_ticks_per_jiffy); - /* XXX fixme */ - set_tb(0, 0); - - if (cpu_nr > 0) { + /* + * Also, because the timebase is frozen, we must not return to the + * caller which will try to do udelay's etc... Instead, we wait -here- + * for the CPU to callin. + */ + for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { + for (j = 1; j < 10000; j++) + asm volatile("nop" : : : "memory"); + asm volatile("sync" : : : "memory"); + } + if (!cpu_callin_map[nr]) + goto stuck; + + /* And we do the TB sync here too for standard dual CPU cards */ + if (psurge_type == PSURGE_DUAL) { + while(!tb_req) + barrier(); + tb_req = 0; + mb(); + timebase = get_tb(); + mb(); + while (timebase) + barrier(); mb(); - sec_tb_reset = 1; - return; } + stuck: + /* now interrupt the secondary, restarting both TBs */ + if (psurge_type == PSURGE_DUAL) + psurge_set_ipi(1); - /* wait for the secondary to have reset its TB before proceeding */ - for (t = 10000000; t > 0 && !sec_tb_reset; --t) - ; - - /* now interrupt the secondary, starting both TBs */ - psurge_set_ipi(1); + if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); } static struct irqaction psurge_irqaction = { @@ -390,36 +402,35 @@ static struct irqaction psurge_irqaction = { static void __init smp_psurge_setup_cpu(int cpu_nr) { + if (cpu_nr != 0) + return; - if (cpu_nr == 0) { - /* If we failed to start the second CPU, we should still - * send it an IPI to start the timebase & DEC or we might - * have them stuck. - */ - if (num_online_cpus() < 2) { - if (psurge_type == PSURGE_DUAL) - psurge_set_ipi(1); - return; - } - /* reset the entry point so if we get another intr we won't - * try to startup again */ - out_be32(psurge_start, 0x100); - if (setup_irq(30, &psurge_irqaction)) - printk(KERN_ERR "Couldn't get primary IPI interrupt"); - } - - if (psurge_type == PSURGE_DUAL) - psurge_dual_sync_tb(cpu_nr); + /* reset the entry point so if we get another intr we won't + * try to startup again */ + out_be32(psurge_start, 0x100); + if (setup_irq(30, &psurge_irqaction)) + printk(KERN_ERR "Couldn't get primary IPI interrupt"); } void __init smp_psurge_take_timebase(void) { - /* Dummy implementation */ + if (psurge_type != PSURGE_DUAL) + return; + + tb_req = 1; + mb(); + while (!timebase) + barrier(); + mb(); + set_tb(timebase >> 32, timebase & 0xffffffff); + timebase = 0; + mb(); + set_dec(tb_ticks_per_jiffy/2); } void __init smp_psurge_give_timebase(void) { - /* Dummy implementation */ + /* Nothing to do here */ } /* PowerSurge-style Macs */ @@ -437,9 +448,6 @@ struct smp_ops_t psurge_smp_ops = { * Core 99 and later support */ -static void (*pmac_tb_freeze)(int freeze); -static u64 timebase; -static int tb_req; static void smp_core99_give_timebase(void) { @@ -478,7 +486,6 @@ static void __devinit smp_core99_take_timebase(void) set_tb(timebase >> 32, timebase & 0xffffffff); timebase = 0; mb(); - set_dec(tb_ticks_per_jiffy/2); local_irq_restore(flags); } @@ -920,3 +927,34 @@ struct smp_ops_t core99_smp_ops = { # endif #endif }; + +void __init pmac_setup_smp(void) +{ + struct device_node *np; + + /* Check for Core99 */ + np = of_find_node_by_name(NULL, "uni-n"); + if (!np) + np = of_find_node_by_name(NULL, "u3"); + if (!np) + np = of_find_node_by_name(NULL, "u4"); + if (np) { + of_node_put(np); + smp_ops = &core99_smp_ops; + } +#ifdef CONFIG_PPC32 + else { + /* We have to set bits in cpu_possible_map here since the + * secondary CPU(s) aren't in the device tree. Various + * things won't be initialized for CPUs not in the possible + * map, so we really need to fix it up here. + */ + int cpu; + + for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) + cpu_set(cpu, cpu_possible_map); + smp_ops = &psurge_smp_ops; + } +#endif /* CONFIG_PPC32 */ +} + -- cgit v1.2.3 From a2367194183d6ab6b05e5d7d9b40db6ba48afc06 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Jun 2009 22:29:55 +0000 Subject: powerpc: Fix output from show_regs For some reason we've had an explicit KERN_INFO for GPR dumps. With recent changes we get output like: <6>GPR00: 00000000 ef855eb0 ef858000 00000001 000000d0 f1000000 ffbc8000 ffffffff The KERN_INFO is causing the <6>. Don't see any reason to keep it around. Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/process.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 3e7135bbe40..892a9f2e6d7 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -528,7 +528,7 @@ void show_regs(struct pt_regs * regs) for (i = 0; i < 32; i++) { if ((i % REGS_PER_LINE) == 0) - printk("\n" KERN_INFO "GPR%02d: ", i); + printk("\nGPR%02d: ", i); printk(REG " ", regs->gpr[i]); if (i == LAST_VOLATILE && !FULL_REGS(regs)) break; -- cgit v1.2.3 From 85355bb272db31a3f2dd99d547eef794805e1319 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Jun 2009 22:01:20 +0000 Subject: powerpc: Fix mpic alloc warning Since we can use kmalloc earlier we are getting the following since the mpic_alloc() code calls alloc_bootmem(). Move to using kzalloc() to remove the warning. ------------[ cut here ]------------ Badness at c0583248 [verbose debug info unavailable] NIP: c0583248 LR: c0583210 CTR: 00000004 REGS: c0741de0 TRAP: 0700 Not tainted (2.6.30-06736-g12a31df) MSR: 00021000 CR: 22024024 XER: 00000000 TASK = c070d3b8[0] 'swapper' THREAD: c0740000 CPU: 0 <6>GPR00: 00000001 c0741e90 c070d3b8 00000001 00000210 00000020 3fffffff 00000000 <6>GPR08: 00000000 c0c85700 c04f8c40 0000002d 22044022 1004a388 7ffd9400 00000000 <6>GPR16: 00000000 7ffcd100 7ffcd100 7ffcd100 c04f8c40 00000000 c059f62c c075a0c0 <6>GPR24: c059f648 00000000 0000000f 00000210 00000020 00000000 3fffffff 00000210 NIP [c0583248] alloc_arch_preferred_bootmem+0x50/0x80 LR [c0583210] alloc_arch_preferred_bootmem+0x18/0x80 Call Trace: [c0741e90] [c07343b0] devtree_lock+0x0/0x24 (unreliable) [c0741ea0] [c0583b14] ___alloc_bootmem_nopanic+0x54/0x108 [c0741ee0] [c0583e18] ___alloc_bootmem+0x18/0x50 [c0741ef0] [c057b9cc] mpic_alloc+0x48/0x710 [c0741f40] [c057ecf4] mpc85xx_ds_pic_init+0x190/0x1b8 [c0741f90] [c057633c] init_IRQ+0x24/0x34 [c0741fa0] [c05738b8] start_kernel+0x260/0x3dc [c0741ff0] [c00003c8] skpinv+0x2e0/0x31c Instruction dump: 409e001c 7c030378 80010014 83e1000c 38210010 7c0803a6 4e800020 3d20c0c8 39295700 80090004 7c000034 5400d97e <0f000000> 2f800000 409e001c 38800000 BenH: Changed to use GFP_KERNEL, the allocator will do the right thing Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/mpic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 32a2e950f56..d46de1f0f3e 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1053,11 +1053,10 @@ struct mpic * __init mpic_alloc(struct device_node *node, int intvec_top; u64 paddr = phys_addr; - mpic = alloc_bootmem(sizeof(struct mpic)); + mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); if (mpic == NULL) return NULL; - - memset(mpic, 0, sizeof(struct mpic)); + mpic->name = name; mpic->hc_irq = mpic_irq_chip; -- cgit v1.2.3 From 850f6ac316cf84bba63fdb775c897834eccbfaa3 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 18 Jun 2009 19:25:00 +0000 Subject: powerpc/mm: Make k(un)map_atomic out of line Those functions are way too big to be inline, besides, kmap_atomic() wants to call debug_kmap_atomic() which isn't exported for modules and causes module link failures. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/highmem.h | 57 ++-------------------------- arch/powerpc/mm/Makefile | 1 + arch/powerpc/mm/highmem.c | 77 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 53 deletions(-) create mode 100644 arch/powerpc/mm/highmem.c (limited to 'arch') diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h index 684a73f4324..a74c4ee6c02 100644 --- a/arch/powerpc/include/asm/highmem.h +++ b/arch/powerpc/include/asm/highmem.h @@ -22,9 +22,7 @@ #ifdef __KERNEL__ -#include #include -#include #include #include #include @@ -62,6 +60,9 @@ extern pte_t *pkmap_page_table; extern void *kmap_high(struct page *page); extern void kunmap_high(struct page *page); +extern void *kmap_atomic_prot(struct page *page, enum km_type type, + pgprot_t prot); +extern void kunmap_atomic(void *kvaddr, enum km_type type); static inline void *kmap(struct page *page) { @@ -79,62 +80,11 @@ static inline void kunmap(struct page *page) kunmap_high(page); } -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) -{ - unsigned int idx; - unsigned long vaddr; - - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ - pagefault_disable(); - if (!PageHighMem(page)) - return page_address(page); - - debug_kmap_atomic(type); - idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); -#ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(!pte_none(*(kmap_pte-idx))); -#endif - __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); - local_flush_tlb_page(NULL, vaddr); - - return (void*) vaddr; -} - static inline void *kmap_atomic(struct page *page, enum km_type type) { return kmap_atomic_prot(page, type, kmap_prot); } -static inline void kunmap_atomic(void *kvaddr, enum km_type type) -{ -#ifdef CONFIG_DEBUG_HIGHMEM - unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); - - if (vaddr < __fix_to_virt(FIX_KMAP_END)) { - pagefault_enable(); - return; - } - - BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); - - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(&init_mm, vaddr, kmap_pte-idx); - local_flush_tlb_page(NULL, vaddr); -#endif - pagefault_enable(); -} - static inline struct page *kmap_atomic_to_page(void *ptr) { unsigned long idx, vaddr = (unsigned long) ptr; @@ -148,6 +98,7 @@ static inline struct page *kmap_atomic_to_page(void *ptr) return pte_page(*pte); } + #define flush_cache_kmaps() flush_cache_all() #endif /* __KERNEL__ */ diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 2d2192e48de..3e68363405b 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o +obj-$(CONFIG_HIGHMEM) += highmem.o diff --git a/arch/powerpc/mm/highmem.c b/arch/powerpc/mm/highmem.c new file mode 100644 index 00000000000..c2186c74c85 --- /dev/null +++ b/arch/powerpc/mm/highmem.c @@ -0,0 +1,77 @@ +/* + * highmem.c: virtual kernel memory mappings for high memory + * + * PowerPC version, stolen from the i386 version. + * + * Used in CONFIG_HIGHMEM systems for memory pages which + * are not addressable by direct kernel virtual addresses. + * + * Copyright (C) 1999 Gerhard Wichert, Siemens AG + * Gerhard.Wichert@pdb.siemens.de + * + * + * Redesigned the x86 32-bit VM architecture to deal with + * up to 16 Terrabyte physical memory. With current x86 CPUs + * we now support up to 64 Gigabytes physical RAM. + * + * Copyright (C) 1999 Ingo Molnar + * + * Reworked for PowerPC by various contributors. Moved from + * highmem.h by Benjamin Herrenschmidt (c) 2009 IBM Corp. + */ + +#include +#include + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) +{ + unsigned int idx; + unsigned long vaddr; + + /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + pagefault_disable(); + if (!PageHighMem(page)) + return page_address(page); + + debug_kmap_atomic(type); + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); +#ifdef CONFIG_DEBUG_HIGHMEM + BUG_ON(!pte_none(*(kmap_pte-idx))); +#endif + __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); + local_flush_tlb_page(NULL, vaddr); + + return (void*) vaddr; +} +EXPORT_SYMBOL(kmap_atomic_prot); + +void kunmap_atomic(void *kvaddr, enum km_type type) +{ +#ifdef CONFIG_DEBUG_HIGHMEM + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < __fix_to_virt(FIX_KMAP_END)) { + pagefault_enable(); + return; + } + + BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(&init_mm, vaddr, kmap_pte-idx); + local_flush_tlb_page(NULL, vaddr); +#endif + pagefault_enable(); +} +EXPORT_SYMBOL(kunmap_atomic); -- cgit v1.2.3 From 4a5cbf17c49a6024a6d7baf03efdffb8ed252bb1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 18 Jun 2009 19:17:39 +0000 Subject: powerpc: Map more memory early on 601 processors The 32-bit kernel relies on some memory being mapped covering the kernel text,data and bss at least, early during boot before the full MMU setup is done. On 32-bit "classic" processors, this is done using BAT registers. On 601, the size of BATs is limited to 8M and we use 2 of them for that initial mapping. This can become quite tight when enabling features like lockdep, so let's use a 3rd one to bump that mapping from 16M to 24M. We keep the 4th BAT free as it can be useful for debugging early boot code to map things like serial ports. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/head_32.S | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 48469463f89..fc213294275 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -1124,9 +1124,8 @@ mmu_off: RFI /* - * Use the first pair of BAT registers to map the 1st 16MB - * of RAM to PAGE_OFFSET. From this point on we can't safely - * call OF any more. + * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET + * (we keep one for debugging) and on others, we use one 256M BAT. */ initial_bats: lis r11,PAGE_OFFSET@h @@ -1136,12 +1135,16 @@ initial_bats: bne 4f ori r11,r11,4 /* set up BAT registers for 601 */ li r8,0x7f /* valid, block length = 8MB */ - oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ - oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ mtspr SPRN_IBAT0L,r8 /* lower BAT register */ - mtspr SPRN_IBAT1U,r9 - mtspr SPRN_IBAT1L,r10 + addis r11,r11,0x800000@h + addis r8,r8,0x800000@h + mtspr SPRN_IBAT1U,r11 + mtspr SPRN_IBAT1L,r8 + addis r11,r11,0x800000@h + addis r8,r8,0x800000@h + mtspr SPRN_IBAT2U,r11 + mtspr SPRN_IBAT2L,r8 isync blr -- cgit v1.2.3 From 5d38902c483881645ba16058cffaa478b81e5cfa Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 17 Jun 2009 17:43:59 +0000 Subject: powerpc: Add irqtrace support for 32-bit powerpc Based on initial work from: Dale Farnsworth Add the low level irq tracing hooks for 32-bit powerpc needed to enable full lockdep functionality. The approach taken to deal with the code in entry_32.S is that we don't trace all the transitions of MSR:EE when we just turn it off to peek at TI_FLAGS without races. Only when we are calling into C code or returning from exceptions with a state that have changed from what lockdep thinks. There's a little bugger though: If we take an exception that keeps interrupts enabled (such as an alignment exception) while interrupts are enabled, we will call trace_hardirqs_on() on the way back spurriously. Not a big deal, but to get rid of it would require remembering in pt_regs that the exception was one of the type that kept interrupts enabled which we don't know at this stage. (Well, we could test all cases for regs->trap but that sucks too much). Signed-off-by: Benjamin Herrenschmidt Tested-by: Kumar Gala --- arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/hw_irq.h | 20 +++--- arch/powerpc/kernel/entry_32.S | 127 ++++++++++++++++++++++++++++++++++++-- arch/powerpc/kernel/setup_32.c | 2 + 4 files changed, 135 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index bf6cedfa05d..d00131ca083 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -62,7 +62,6 @@ config HAVE_LATENCYTOP_SUPPORT config TRACE_IRQFLAGS_SUPPORT bool - depends on PPC64 default y config LOCKDEP_SUPPORT diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index 867ab8ed69b..8b505eaaa38 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -68,13 +68,13 @@ static inline int irqs_disabled_flags(unsigned long flags) #if defined(CONFIG_BOOKE) #define SET_MSR_EE(x) mtmsr(x) -#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") +#define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") #else #define SET_MSR_EE(x) mtmsr(x) -#define local_irq_restore(flags) mtmsr(flags) +#define raw_local_irq_restore(flags) mtmsr(flags) #endif -static inline void local_irq_disable(void) +static inline void raw_local_irq_disable(void) { #ifdef CONFIG_BOOKE __asm__ __volatile__("wrteei 0": : :"memory"); @@ -86,7 +86,7 @@ static inline void local_irq_disable(void) #endif } -static inline void local_irq_enable(void) +static inline void raw_local_irq_enable(void) { #ifdef CONFIG_BOOKE __asm__ __volatile__("wrteei 1": : :"memory"); @@ -98,7 +98,7 @@ static inline void local_irq_enable(void) #endif } -static inline void local_irq_save_ptr(unsigned long *flags) +static inline void raw_local_irq_save_ptr(unsigned long *flags) { unsigned long msr; msr = mfmsr(); @@ -110,12 +110,12 @@ static inline void local_irq_save_ptr(unsigned long *flags) #endif } -#define local_save_flags(flags) ((flags) = mfmsr()) -#define local_irq_save(flags) local_irq_save_ptr(&flags) -#define irqs_disabled() ((mfmsr() & MSR_EE) == 0) +#define raw_local_save_flags(flags) ((flags) = mfmsr()) +#define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags) +#define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0) +#define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0) -#define hard_irq_enable() local_irq_enable() -#define hard_irq_disable() local_irq_disable() +#define hard_irq_disable() raw_local_irq_disable() static inline int irqs_disabled_flags(unsigned long flags) { diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 4dd38f12915..3cadba60a4b 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -191,11 +191,49 @@ transfer_to_handler_cont: mflr r9 lwz r11,0(r9) /* virtual address of handler */ lwz r9,4(r9) /* where to go when done */ +#ifdef CONFIG_TRACE_IRQFLAGS + lis r12,reenable_mmu@h + ori r12,r12,reenable_mmu@l + mtspr SPRN_SRR0,r12 + mtspr SPRN_SRR1,r10 + SYNC + RFI +reenable_mmu: /* re-enable mmu so we can */ + mfmsr r10 + lwz r12,_MSR(r1) + xor r10,r10,r12 + andi. r10,r10,MSR_EE /* Did EE change? */ + beq 1f + + /* Save handler and return address into the 2 unused words + * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything + * else can be recovered from the pt_regs except r3 which for + * normal interrupts has been set to pt_regs and for syscalls + * is an argument, so we temporarily use ORIG_GPR3 to save it + */ + stw r9,8(r1) + stw r11,12(r1) + stw r3,ORIG_GPR3(r1) + bl trace_hardirqs_off + lwz r0,GPR0(r1) + lwz r3,ORIG_GPR3(r1) + lwz r4,GPR4(r1) + lwz r5,GPR5(r1) + lwz r6,GPR6(r1) + lwz r7,GPR7(r1) + lwz r8,GPR8(r1) + lwz r9,8(r1) + lwz r11,12(r1) +1: mtctr r11 + mtlr r9 + bctr /* jump to handler */ +#else /* CONFIG_TRACE_IRQFLAGS */ mtspr SPRN_SRR0,r11 mtspr SPRN_SRR1,r10 mtlr r9 SYNC RFI /* jump to handler, enable MMU */ +#endif /* CONFIG_TRACE_IRQFLAGS */ #if defined (CONFIG_6xx) || defined(CONFIG_E500) 4: rlwinm r12,r12,0,~_TLF_NAPPING @@ -251,6 +289,31 @@ _GLOBAL(DoSyscall) #ifdef SHOW_SYSCALLS bl do_show_syscall #endif /* SHOW_SYSCALLS */ +#ifdef CONFIG_TRACE_IRQFLAGS + /* Return from syscalls can (and generally will) hard enable + * interrupts. You aren't supposed to call a syscall with + * interrupts disabled in the first place. However, to ensure + * that we get it right vs. lockdep if it happens, we force + * that hard enable here with appropriate tracing if we see + * that we have been called with interrupts off + */ + mfmsr r11 + andi. r12,r11,MSR_EE + bne+ 1f + /* We came in with interrupts disabled, we enable them now */ + bl trace_hardirqs_on + mfmsr r11 + lwz r0,GPR0(r1) + lwz r3,GPR3(r1) + lwz r4,GPR4(r1) + ori r11,r11,MSR_EE + lwz r5,GPR5(r1) + lwz r6,GPR6(r1) + lwz r7,GPR7(r1) + lwz r8,GPR8(r1) + mtmsr r11 +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A @@ -275,6 +338,7 @@ ret_from_syscall: rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ /* disable interrupts so current_thread_info()->flags can't change */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ + /* Note: We don't bother telling lockdep about it */ SYNC MTMSRD(r10) lwz r9,TI_FLAGS(r12) @@ -288,6 +352,19 @@ ret_from_syscall: oris r11,r11,0x1000 /* Set SO bit in CR */ stw r11,_CCR(r1) syscall_exit_cont: + lwz r8,_MSR(r1) +#ifdef CONFIG_TRACE_IRQFLAGS + /* If we are going to return from the syscall with interrupts + * off, we trace that here. It shouldn't happen though but we + * want to catch the bugger if it does right ? + */ + andi. r10,r8,MSR_EE + bne+ 1f + stw r3,GPR3(r1) + bl trace_hardirqs_off + lwz r3,GPR3(r1) +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) /* If the process has its own DBCR0 value, load it up. The internal debug mode bit tells us that dbcr0 should be loaded. */ @@ -311,7 +388,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) mtlr r4 mtcr r5 lwz r7,_NIP(r1) - lwz r8,_MSR(r1) FIX_SRR1(r8, r0) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -394,7 +470,9 @@ syscall_exit_work: andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) beq ret_from_except - /* Re-enable interrupts */ + /* Re-enable interrupts. There is no need to trace that with + * lockdep as we are supposed to have IRQs on at this point + */ ori r10,r10,MSR_EE SYNC MTMSRD(r10) @@ -705,6 +783,7 @@ ret_from_except: /* Hard-disable interrupts so that current_thread_info()->flags * can't change between when we test it and when we return * from the interrupt. */ + /* Note: We don't bother telling lockdep about it */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) SYNC /* Some chip revs have problems here... */ MTMSRD(r10) /* disable interrupts */ @@ -744,11 +823,24 @@ resume_kernel: beq+ restore andi. r0,r3,MSR_EE /* interrupts off? */ beq restore /* don't schedule if so */ +#ifdef CONFIG_TRACE_IRQFLAGS + /* Lockdep thinks irqs are enabled, we need to call + * preempt_schedule_irq with IRQs off, so we inform lockdep + * now that we -did- turn them off already + */ + bl trace_hardirqs_off +#endif 1: bl preempt_schedule_irq rlwinm r9,r1,0,0,(31-THREAD_SHIFT) lwz r3,TI_FLAGS(r9) andi. r0,r3,_TIF_NEED_RESCHED bne- 1b +#ifdef CONFIG_TRACE_IRQFLAGS + /* And now, to properly rebalance the above, we tell lockdep they + * are being turned back on, which will happen when we return + */ + bl trace_hardirqs_on +#endif #else resume_kernel: #endif /* CONFIG_PREEMPT */ @@ -765,6 +857,28 @@ restore: stw r6,icache_44x_need_flush@l(r4) 1: #endif /* CONFIG_44x */ + + lwz r9,_MSR(r1) +#ifdef CONFIG_TRACE_IRQFLAGS + /* Lockdep doesn't know about the fact that IRQs are temporarily turned + * off in this assembly code while peeking at TI_FLAGS() and such. However + * we need to inform it if the exception turned interrupts off, and we + * are about to trun them back on. + * + * The problem here sadly is that we don't know whether the exceptions was + * one that turned interrupts off or not. So we always tell lockdep about + * turning them on here when we go back to wherever we came from with EE + * on, even if that may meen some redudant calls being tracked. Maybe later + * we could encode what the exception did somewhere or test the exception + * type in the pt_regs but that sounds overkill + */ + andi. r10,r9,MSR_EE + beq 1f + bl trace_hardirqs_on + lwz r9,_MSR(r1) +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ + lwz r0,GPR0(r1) lwz r2,GPR2(r1) REST_4GPRS(3, r1) @@ -782,7 +896,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) stwcx. r0,0,r1 /* to clear the reservation */ #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) - lwz r9,_MSR(r1) andi. r10,r9,MSR_RI /* check if this exception occurred */ beql nonrecoverable /* at a bad place (MSR:RI = 0) */ @@ -805,7 +918,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) MTMSRD(r10) /* clear the RI bit */ .globl exc_exit_restart exc_exit_restart: - lwz r9,_MSR(r1) lwz r12,_NIP(r1) FIX_SRR1(r9,r10) mtspr SPRN_SRR0,r12 @@ -1035,11 +1147,18 @@ do_work: /* r10 contains MSR_KERNEL here */ beq do_user_signal do_resched: /* r10 contains MSR_KERNEL here */ + /* Note: We don't need to inform lockdep that we are enabling + * interrupts here. As far as it knows, they are already enabled + */ ori r10,r10,MSR_EE SYNC MTMSRD(r10) /* hard-enable interrupts */ bl schedule recheck: + /* Note: And we don't tell it we are disabling them again + * neither. Those disable/enable cycles used to peek at + * TI_FLAGS aren't advertised. + */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) SYNC MTMSRD(r10) /* disable interrupts */ diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 1d154248cf4..e1e3059cf34 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -119,6 +119,8 @@ notrace unsigned long __init early_init(unsigned long dt_ptr) */ notrace void __init machine_init(unsigned long dt_ptr) { + lockdep_init(); + /* Enable early debugging if any specified (see udbg.h) */ udbg_early_init(); -- cgit v1.2.3 From f97bb36f705da0a86b3ea77bfeee3415fee0b025 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 16 Jun 2009 16:42:49 +0000 Subject: powerpc/rtas: Turn rtas lock into a raw spinlock RTAS currently uses a normal spinlock. However it can be called from contexts where this is not necessarily a good idea. For example, it can be called while syncing timebases, with the core timebase being frozen. Unfortunately, that will deadlock in case of lock contention when spinlock debugging is enabled as the spin lock debugging code will try to use __delay() which ... relies on the timebase being enabled. Also RTAS can be used in some low level IRQ handling code path so it may as well be a raw spinlock for -rt sake. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/rtas.h | 2 +- arch/powerpc/kernel/rtas.c | 38 +++++++++++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h index 01c12339b30..0af42d20b69 100644 --- a/arch/powerpc/include/asm/rtas.h +++ b/arch/powerpc/include/asm/rtas.h @@ -58,7 +58,7 @@ struct rtas_t { unsigned long entry; /* physical address pointer */ unsigned long base; /* physical address pointer */ unsigned long size; - spinlock_t lock; + raw_spinlock_t lock; struct rtas_args args; struct device_node *dev; /* virtual address pointer */ }; diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index ee4c7609b64..d9a9974c693 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -40,7 +40,7 @@ #include struct rtas_t rtas = { - .lock = SPIN_LOCK_UNLOCKED + .lock = __RAW_SPIN_LOCK_UNLOCKED }; EXPORT_SYMBOL(rtas); @@ -67,6 +67,28 @@ unsigned long rtas_rmo_buf; void (*rtas_flash_term_hook)(int); EXPORT_SYMBOL(rtas_flash_term_hook); +/* RTAS use home made raw locking instead of spin_lock_irqsave + * because those can be called from within really nasty contexts + * such as having the timebase stopped which would lockup with + * normal locks and spinlock debugging enabled + */ +static unsigned long lock_rtas(void) +{ + unsigned long flags; + + local_irq_save(flags); + preempt_disable(); + __raw_spin_lock_flags(&rtas.lock, flags); + return flags; +} + +static void unlock_rtas(unsigned long flags) +{ + __raw_spin_unlock(&rtas.lock); + local_irq_restore(flags); + preempt_enable(); +} + /* * call_rtas_display_status and call_rtas_display_status_delay * are designed only for very early low-level debugging, which @@ -79,7 +101,7 @@ static void call_rtas_display_status(char c) if (!rtas.base) return; - spin_lock_irqsave(&rtas.lock, s); + s = lock_rtas(); args->token = 10; args->nargs = 1; @@ -89,7 +111,7 @@ static void call_rtas_display_status(char c) enter_rtas(__pa(args)); - spin_unlock_irqrestore(&rtas.lock, s); + unlock_rtas(s); } static void call_rtas_display_status_delay(char c) @@ -411,8 +433,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) return -1; - /* Gotta do something different here, use global lock for now... */ - spin_lock_irqsave(&rtas.lock, s); + s = lock_rtas(); rtas_args = &rtas.args; rtas_args->token = token; @@ -439,8 +460,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) outputs[i] = rtas_args->rets[i+1]; ret = (nret > 0)? rtas_args->rets[0]: 0; - /* Gotta do something different here, use global lock for now... */ - spin_unlock_irqrestore(&rtas.lock, s); + unlock_rtas(s); if (buff_copy) { log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0); @@ -837,7 +857,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) buff_copy = get_errorlog_buffer(); - spin_lock_irqsave(&rtas.lock, flags); + flags = lock_rtas(); rtas.args = args; enter_rtas(__pa(&rtas.args)); @@ -848,7 +868,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) if (args.rets[0] == -1) errbuf = __fetch_rtas_last_error(buff_copy); - spin_unlock_irqrestore(&rtas.lock, flags); + unlock_rtas(flags); if (buff_copy) { if (errbuf) -- cgit v1.2.3 From c4007a2fbf5f82b7e694c22b5929c87e38415a56 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 16 Jun 2009 16:42:50 +0000 Subject: powerpc: Use one common impl. of RTAS timebase sync and use raw spinlock Several platforms use their own copy of what is essentially the same code, using RTAS to synchronize the timebases when bringing up new CPUs. This moves it all into a single common implementation and additionally turns the spinlock into a raw spinlock since the former can rely on the timebase not being frozen when spinlock debugging is enabled, and finally masks interrupts while the timebase is disabled. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/rtas.h | 3 +++ arch/powerpc/kernel/rtas.c | 31 +++++++++++++++++++++++++++++++ arch/powerpc/platforms/cell/smp.c | 30 ++---------------------------- arch/powerpc/platforms/chrp/smp.c | 33 ++------------------------------- arch/powerpc/platforms/pseries/smp.c | 30 ++---------------------------- 5 files changed, 40 insertions(+), 87 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h index 0af42d20b69..168fce72620 100644 --- a/arch/powerpc/include/asm/rtas.h +++ b/arch/powerpc/include/asm/rtas.h @@ -245,5 +245,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg) (devfn << 8) | (reg & 0xff); } +extern void __cpuinit rtas_give_timebase(void); +extern void __cpuinit rtas_take_timebase(void); + #endif /* __KERNEL__ */ #endif /* _POWERPC_RTAS_H */ diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index d9a9974c693..c434823b8c8 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -38,6 +38,7 @@ #include #include #include +#include struct rtas_t rtas = { .lock = __RAW_SPIN_LOCK_UNLOCKED @@ -971,3 +972,33 @@ int __init early_init_dt_scan_rtas(unsigned long node, /* break now */ return 1; } + +static raw_spinlock_t timebase_lock; +static u64 timebase = 0; + +void __cpuinit rtas_give_timebase(void) +{ + unsigned long flags; + + local_irq_save(flags); + hard_irq_disable(); + __raw_spin_lock(&timebase_lock); + rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); + timebase = get_tb(); + __raw_spin_unlock(&timebase_lock); + + while (timebase) + barrier(); + rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); + local_irq_restore(flags); +} + +void __cpuinit rtas_take_timebase(void) +{ + while (!timebase) + barrier(); + __raw_spin_lock(&timebase_lock); + set_tb(timebase >> 32, timebase & 0xffffffff); + timebase = 0; + __raw_spin_unlock(&timebase_lock); +} diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index 9046803c827..bc97fada48c 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -140,31 +139,6 @@ static void __devinit smp_cell_setup_cpu(int cpu) mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); } -static DEFINE_SPINLOCK(timebase_lock); -static unsigned long timebase = 0; - -static void __devinit cell_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase = get_tb(); - spin_unlock(&timebase_lock); - - while (timebase) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -static void __devinit cell_take_timebase(void) -{ - while (!timebase) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase >> 32, timebase & 0xffffffff); - timebase = 0; - spin_unlock(&timebase_lock); -} - static void __devinit smp_cell_kick_cpu(int nr) { BUG_ON(nr < 0 || nr >= NR_CPUS); @@ -224,8 +198,8 @@ void __init smp_init_cell(void) /* Non-lpar has additional take/give timebase */ if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { - smp_ops->give_timebase = cell_give_timebase; - smp_ops->take_timebase = cell_take_timebase; + smp_ops->give_timebase = rtas_give_timebase; + smp_ops->take_timebase = rtas_take_timebase; } DBG(" <- smp_init_cell()\n"); diff --git a/arch/powerpc/platforms/chrp/smp.c b/arch/powerpc/platforms/chrp/smp.c index 10a4a4d063b..02cafecc90e 100644 --- a/arch/powerpc/platforms/chrp/smp.c +++ b/arch/powerpc/platforms/chrp/smp.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -42,40 +41,12 @@ static void __devinit smp_chrp_setup_cpu(int cpu_nr) mpic_setup_this_cpu(); } -static DEFINE_SPINLOCK(timebase_lock); -static unsigned int timebase_upper = 0, timebase_lower = 0; - -void __devinit smp_chrp_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase_upper = get_tbu(); - timebase_lower = get_tbl(); - spin_unlock(&timebase_lock); - - while (timebase_upper || timebase_lower) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -void __devinit smp_chrp_take_timebase(void) -{ - while (!(timebase_upper || timebase_lower)) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase_upper, timebase_lower); - timebase_upper = 0; - timebase_lower = 0; - spin_unlock(&timebase_lock); - printk("CPU %i taken timebase\n", smp_processor_id()); -} - /* CHRP with openpic */ struct smp_ops_t chrp_smp_ops = { .message_pass = smp_mpic_message_pass, .probe = smp_mpic_probe, .kick_cpu = smp_chrp_kick_cpu, .setup_cpu = smp_chrp_setup_cpu, - .give_timebase = smp_chrp_give_timebase, - .take_timebase = smp_chrp_take_timebase, + .give_timebase = rtas_give_timebase, + .take_timebase = rtas_take_timebase, }; diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 1a231c389ba..1f8f6cfb94f 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -118,31 +117,6 @@ static void __devinit smp_xics_setup_cpu(int cpu) } #endif /* CONFIG_XICS */ -static DEFINE_SPINLOCK(timebase_lock); -static unsigned long timebase = 0; - -static void __devinit pSeries_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase = get_tb(); - spin_unlock(&timebase_lock); - - while (timebase) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -static void __devinit pSeries_take_timebase(void) -{ - while (!timebase) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase >> 32, timebase & 0xffffffff); - timebase = 0; - spin_unlock(&timebase_lock); -} - static void __devinit smp_pSeries_kick_cpu(int nr) { BUG_ON(nr < 0 || nr >= NR_CPUS); @@ -209,8 +183,8 @@ static void __init smp_init_pseries(void) /* Non-lpar has additional take/give timebase */ if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { - smp_ops->give_timebase = pSeries_give_timebase; - smp_ops->take_timebase = pSeries_take_timebase; + smp_ops->give_timebase = rtas_give_timebase; + smp_ops->take_timebase = rtas_take_timebase; } pr_debug(" <- smp_init_pSeries()\n"); -- cgit v1.2.3 From 6893ce6c1cdcf489b7ca8e6b6596208aa971a083 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 16 Jun 2009 16:42:51 +0000 Subject: powerpc/pasemi: Use raw spinlock in SMP TB sync spin_lock() can hang if called while the timebase is frozen, so use a raw lock instead, also disable interrupts while at it. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/pasemi/setup.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index 153051eb6d9..a4619347aa7 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c @@ -71,20 +71,25 @@ static void pas_restart(char *cmd) } #ifdef CONFIG_SMP -static DEFINE_SPINLOCK(timebase_lock); +static raw_spinlock_t timebase_lock; static unsigned long timebase; static void __devinit pas_give_timebase(void) { - spin_lock(&timebase_lock); + unsigned long flags; + + local_irq_save(flags); + hard_irq_disable(); + __raw_spin_lock(&timebase_lock); mtspr(SPRN_TBCTL, TBCTL_FREEZE); isync(); timebase = get_tb(); - spin_unlock(&timebase_lock); + __raw_spin_unlock(&timebase_lock); while (timebase) barrier(); mtspr(SPRN_TBCTL, TBCTL_RESTART); + local_irq_restore(flags); } static void __devinit pas_take_timebase(void) @@ -92,10 +97,10 @@ static void __devinit pas_take_timebase(void) while (!timebase) smp_rmb(); - spin_lock(&timebase_lock); + __raw_spin_lock(&timebase_lock); set_tb(timebase >> 32, timebase & 0xffffffff); timebase = 0; - spin_unlock(&timebase_lock); + __raw_spin_unlock(&timebase_lock); } struct smp_ops_t pas_smp_ops = { -- cgit v1.2.3 From 03c01aa740d4137ea2884328f2c29956c6084834 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 16 Jun 2009 15:55:18 +0000 Subject: powerpc/of: Fix usage of dev_set_name() in of_device_alloc() dev_set_name() takes a format string, so use it properly and avoid a warning with recent gcc's Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/of_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c index fa983a59c4c..a359cb08e90 100644 --- a/arch/powerpc/kernel/of_device.c +++ b/arch/powerpc/kernel/of_device.c @@ -76,7 +76,7 @@ struct of_device *of_device_alloc(struct device_node *np, dev->dev.archdata.of_node = np; if (bus_id) - dev_set_name(&dev->dev, bus_id); + dev_set_name(&dev->dev, "%s", bus_id); else of_device_make_bus_id(dev); -- cgit v1.2.3 From f694cda89250f38782a5fd0b2d32fe33a39dcf37 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 16 Jun 2009 15:55:19 +0000 Subject: powerpc/440: Fix warning early debug code The function udbg_44x_as1_flush() has the wrong prototype causing a warning when enabling 440 early debug. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/udbg_16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c index 0362a891e54..acb74a17bbb 100644 --- a/arch/powerpc/kernel/udbg_16550.c +++ b/arch/powerpc/kernel/udbg_16550.c @@ -219,7 +219,7 @@ void udbg_init_pas_realmode(void) #ifdef CONFIG_PPC_EARLY_DEBUG_44x #include -static int udbg_44x_as1_flush(void) +static void udbg_44x_as1_flush(void) { if (udbg_comport) { while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) -- cgit v1.2.3 From 6c16a74d423f584ed80815ee7b944f5b578dd37a Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 15 Jun 2009 16:53:43 +0000 Subject: powerpc/mm: Fix potential access to freed pages when using hugetlbfs When using 64k page sizes, our PTE pages are split in two halves, the second half containing the "extension" used to keep track of individual 4k pages when not using HW 64k pages. However, our page tables used for hugetlb have a slightly different format and don't carry that "second half". Our code that batched PTEs to be invalidated unconditionally reads the "second half" (to put it into the batch), which means that when called to invalidate hugetlb PTEs, it will access unrelated memory. It breaks when CONFIG_DEBUG_PAGEALLOC is enabled. This fixes it by only accessing the second half when the _PAGE_COMBO bit is set in the first half, which indicates that we are dealing with a "combo" page which represents 16x4k subpages. Anything else shouldn't have this bit set and thus not require loading from the second half. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/pte-hash64-64k.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h index e05d26fa372..82b72207c51 100644 --- a/arch/powerpc/include/asm/pte-hash64-64k.h +++ b/arch/powerpc/include/asm/pte-hash64-64k.h @@ -47,7 +47,8 @@ * generic accessors and iterators here */ #define __real_pte(e,p) ((real_pte_t) { \ - (e), pte_val(*((p) + PTRS_PER_PTE)) }) + (e), ((e) & _PAGE_COMBO) ? \ + (pte_val(*((p) + PTRS_PER_PTE))) : 0 }) #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) #define __rpte_to_pte(r) ((r).pte) -- cgit v1.2.3 From a80cad950f2a562e60db1869dd29bc007c5a4b66 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 26 Jun 2009 07:05:39 +0000 Subject: sh: ms7724se: Add sh_eth support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7724/setup.c | 106 +++++++++++++++++++++++++++++++++- arch/sh/include/mach-se/mach/se7724.h | 5 ++ 2 files changed, 109 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index 9cd04bd558b..21d18005fb4 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include #include #include @@ -272,6 +274,34 @@ static struct platform_device keysc_device = { }, }; +/* SH Eth */ +static struct resource sh_eth_resources[] = { + [0] = { + .start = SH_ETH_ADDR, + .end = SH_ETH_ADDR + 0x1FC, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 91, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +struct sh_eth_plat_data sh_eth_plat = { + .phy = 0x1f, /* SMSC LAN8187 */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh_eth_device = { + .name = "sh-eth", + .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .resource = sh_eth_resources, +}; + static struct platform_device *ms7724se_devices[] __initdata = { &heartbeat_device, &smc91x_eth_device, @@ -280,8 +310,57 @@ static struct platform_device *ms7724se_devices[] __initdata = { &ceu0_device, &ceu1_device, &keysc_device, + &sh_eth_device, }; +#define EEPROM_OP 0xBA206000 +#define EEPROM_ADR 0xBA206004 +#define EEPROM_DATA 0xBA20600C +#define EEPROM_STAT 0xBA206010 +#define EEPROM_STRT 0xBA206014 +static int __init sh_eth_is_eeprom_ready(void) +{ + int t = 10000; + + while (t--) { + if (!ctrl_inw(EEPROM_STAT)) + return 1; + cpu_relax(); + } + + printk(KERN_ERR "ms7724se can not access to eeprom\n"); + return 0; +} + +static void __init sh_eth_init(void) +{ + int i; + u16 mac[3]; + + /* check EEPROM status */ + if (!sh_eth_is_eeprom_ready()) + return; + + /* read MAC addr from EEPROM */ + for (i = 0 ; i < 3 ; i++) { + ctrl_outw(0x0, EEPROM_OP); /* read */ + ctrl_outw(i*2, EEPROM_ADR); + ctrl_outw(0x1, EEPROM_STRT); + if (!sh_eth_is_eeprom_ready()) + return; + + mac[i] = ctrl_inw(EEPROM_DATA); + mac[i] = ((mac[i] & 0xFF) << 8) | (mac[i] >> 8); /* swap */ + } + + /* reset sh-eth */ + ctrl_outl(0x1, SH_ETH_ADDR + 0x0); + + /* set MAC addr */ + ctrl_outl(((mac[0] << 16) | (mac[1])), SH_ETH_MAHR); + ctrl_outl((mac[2]), SH_ETH_MALR); +} + #define SW4140 0xBA201000 #define FPGA_OUT 0xBA200400 #define PORT_HIZA 0xA4050158 @@ -302,7 +381,8 @@ static int __init devices_setup(void) ctrl_outw(ctrl_inw(FPGA_OUT) & ~((1 << 1) | /* LAN */ (1 << 6) | /* VIDEO DAC */ - (1 << 12)), /* USB0 */ + (1 << 12) | /* USB0 */ + (1 << 14)), /* RMII */ FPGA_OUT); /* enable IRQ 0,1,2 */ @@ -404,6 +484,28 @@ static int __init devices_setup(void) gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT0, NULL); + /* + * enable SH-Eth + * + * please remove J33 pin from your board !! + * + * ms7724 board should not use GPIO_FN_LNKSTA pin + * So, This time PTX5 is set to input pin + */ + gpio_request(GPIO_FN_RMII_RXD0, NULL); + gpio_request(GPIO_FN_RMII_RXD1, NULL); + gpio_request(GPIO_FN_RMII_TXD0, NULL); + gpio_request(GPIO_FN_RMII_TXD1, NULL); + gpio_request(GPIO_FN_RMII_REF_CLK, NULL); + gpio_request(GPIO_FN_RMII_TX_EN, NULL); + gpio_request(GPIO_FN_RMII_RX_ER, NULL); + gpio_request(GPIO_FN_RMII_CRS_DV, NULL); + gpio_request(GPIO_FN_MDIO, NULL); + gpio_request(GPIO_FN_MDC, NULL); + gpio_request(GPIO_PTX5, NULL); + gpio_direction_input(GPIO_PTX5); + sh_eth_init(); + if (sw & SW41_B) { /* SVGA */ lcdc_info.ch[0].lcd_cfg.xres = 800; @@ -437,7 +539,7 @@ static int __init devices_setup(void) } return platform_add_devices(ms7724se_devices, - ARRAY_SIZE(ms7724se_devices)); + ARRAY_SIZE(ms7724se_devices)); } device_initcall(devices_setup); diff --git a/arch/sh/include/mach-se/mach/se7724.h b/arch/sh/include/mach-se/mach/se7724.h index 74164b60d0d..29514a39d0f 100644 --- a/arch/sh/include/mach-se/mach/se7724.h +++ b/arch/sh/include/mach-se/mach/se7724.h @@ -20,6 +20,11 @@ */ #include +/* SH Eth */ +#define SH_ETH_ADDR (0xA4600000) +#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) +#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) + #define PA_LED (0xba203000) /* 8bit LED */ #define IRQ_MODE (0xba200010) #define IRQ0_SR (0xba200014) -- cgit v1.2.3 From 9a24ee03aebc55cec00cc388b6727bff24ed433f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 24 Jun 2009 17:13:48 +0100 Subject: [ARM] 5563/1: at91: at91sam9rlek lcd interface correction Here is a little update to the at91sam9rlek lcd interface. This will correct the power pin of the LCD. It will also add precision to the struct atmel_lcdfb_info scructure: backlight enabling and wiring mode correction: RGB wiring on the -EK board. Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/board-sam9rlek.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 35e12a49d1a..f6b5672cabd 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -186,19 +186,21 @@ static struct fb_monspecs at91fb_default_monspecs = { static void at91_lcdc_power_control(int on) { if (on) - at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ + at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */ else - at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ + at91_set_gpio_value(AT91_PIN_PC1, 1); /* power down */ } /* Driver datas */ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { + .lcdcon_is_backlight = true, .default_bpp = 16, .default_dmacon = ATMEL_LCDC_DMAEN, .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, .default_monspecs = &at91fb_default_monspecs, .atmel_lcdfb_power_control = at91_lcdc_power_control, .guard_time = 1, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, }; #else -- cgit v1.2.3 From ff8a4bae459a9b6455504127fcb78fdbc8e50e4c Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Sat, 27 Jun 2009 12:22:27 -0700 Subject: Revert "x86: cap iomem_resource to addressable physical memory" This reverts commit 95ee14e4379c5e19c0897c872350570402014742. Mikael Petterson reported that at least one of his systems will not boot as a result. We have ruled out the detection algorithm malfunctioning, so it is not a matter of producing the incorrect bitmasks; rather, something in the application of them fails. Revert the commit until we can root cause and correct this problem. -stable team: this means the underlying commit should be rejected. Reported-and-isolated-by: Mikael Petterson Signed-off-by: H. Peter Anvin LKML-Reference: <200906261559.n5QFxJH8027336@pilspetsen.it.uu.se> Cc: stable@kernel.org Cc: Grant Grundler --- arch/x86/kernel/cpu/common.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 6b26d4deada..f1961c07af9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -848,9 +848,6 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) numa_add_cpu(smp_processor_id()); #endif - - /* Cap the iomem address space to what is addressable on all CPUs */ - iomem_resource.end &= (1ULL << c->x86_phys_bits) - 1; } #ifdef CONFIG_X86_64 -- cgit v1.2.3 From 29a4b9333bf9ffef12b3dd7cbf2e3dbe01152968 Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Tue, 19 May 2009 13:29:27 +0300 Subject: KVM: MMU: Allow 4K ptes with bit 7 (PAT) set Bit 7 is perfectly legal in the 4K page leve; it is used for the PAT. Signed-off-by: Avi Kivity --- arch/x86/kvm/mmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 5c3d6e81a7d..7030b5f911b 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2157,7 +2157,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) else /* 32 bits PSE 4MB page */ context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; case PT32E_ROOT_LEVEL: context->rsvd_bits_mask[0][2] = @@ -2170,7 +2170,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 62) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; case PT64_ROOT_LEVEL: context->rsvd_bits_mask[0][3] = exb_bit_rsvd | @@ -2186,7 +2186,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; } } -- cgit v1.2.3 From ffdfa071bd6fa8f5e5964569bef41e067540d424 Mon Sep 17 00:00:00 2001 From: Jes Sorensen Date: Wed, 17 Jun 2009 11:08:08 +0200 Subject: KVM: ia64: fix ia64 build due to missing kallsyms_lookup() and double export Fix problem with double export of certain symbols from vsprintf.c which we do not wish to export from the kvm-intel.ko module. In addition, we do not have access to kallsyms_lookup() from the module, so make sure to #undef CONFIG_KALLSYMS Signed-off-by: Jes Sorensen Acked-by: Xiantao Zhang Signed-off-by: Avi Kivity --- arch/ia64/kvm/kvm_lib.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/ia64/kvm/kvm_lib.c b/arch/ia64/kvm/kvm_lib.c index a85cb611ecd..f1268b8e6f9 100644 --- a/arch/ia64/kvm/kvm_lib.c +++ b/arch/ia64/kvm/kvm_lib.c @@ -11,5 +11,11 @@ * */ #undef CONFIG_MODULES +#include +#undef CONFIG_KALLSYMS +#undef EXPORT_SYMBOL +#undef EXPORT_SYMBOL_GPL +#define EXPORT_SYMBOL(sym) +#define EXPORT_SYMBOL_GPL(sym) #include "../../../lib/vsprintf.c" #include "../../../lib/ctype.c" -- cgit v1.2.3 From a3f9d3981cd82d65232b733eb792382237d686bd Mon Sep 17 00:00:00 2001 From: Jaswinder Singh Rajput Date: Thu, 18 Jun 2009 16:53:25 +0530 Subject: KVM: kvm/x86_emulate.c toggle_interruptibility() should be static toggle_interruptibility() is used only by same file, it should be static. Fixed following sparse warning : arch/x86/kvm/x86_emulate.c:1364:6: warning: symbol 'toggle_interruptibility' was not declared. Should it be static? Signed-off-by: Jaswinder Singh Rajput Signed-off-by: Avi Kivity --- arch/x86/kvm/x86_emulate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index c1b6c232e02..616de4628d6 100644 --- a/arch/x86/kvm/x86_emulate.c +++ b/arch/x86/kvm/x86_emulate.c @@ -1361,7 +1361,7 @@ static inline int writeback(struct x86_emulate_ctxt *ctxt, return 0; } -void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) +static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) { u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); /* -- cgit v1.2.3 From ef50f7ac7e234f9696555e41eab3de69c3d86166 Mon Sep 17 00:00:00 2001 From: Christian Borntraeger Date: Tue, 23 Jun 2009 17:24:07 +0200 Subject: KVM: s390: Allow stfle instruction in the guest 2.6.31-rc introduced an architecture level set checker based on facility bits. e.g. if the kernel is compiled to run only on z9, several facility bits are checked very early and the kernel refuses to boot if a z9 specific facility is missing. Until now kvm on s390 did not implement the store facility extended (STFLE) instruction. A 2.6.31-rc kernel that was compiled for z9 or higher did not boot in kvm. This patch implements stfle. This patch should go in before 2.6.31. Signed-off-by: Christian Borntraeger Signed-off-by: Avi Kivity --- arch/s390/include/asm/kvm_host.h | 4 +++- arch/s390/kvm/kvm-s390.c | 23 ++++++++++++++++++++++- arch/s390/kvm/priv.c | 2 +- 3 files changed, 26 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index a27d0d5a6f8..1cd02f6073a 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -99,7 +99,9 @@ struct kvm_s390_sie_block { __u8 reservedd0[48]; /* 0x00d0 */ __u64 gcr[16]; /* 0x0100 */ __u64 gbea; /* 0x0180 */ - __u8 reserved188[120]; /* 0x0188 */ + __u8 reserved188[24]; /* 0x0188 */ + __u32 fac; /* 0x01a0 */ + __u8 reserved1a4[92]; /* 0x01a4 */ } __attribute__((packed)); struct kvm_vcpu_stat { diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index c18b21d6991..90d9d1ba258 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "kvm-s390.h" #include "gaccess.h" @@ -69,6 +70,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; +static unsigned long long *facilities; /* Section: not file related */ void kvm_arch_hardware_enable(void *garbage) @@ -288,6 +290,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->gmsor = vcpu->kvm->arch.guest_origin; vcpu->arch.sie_block->ecb = 2; vcpu->arch.sie_block->eca = 0xC1002001U; + vcpu->arch.sie_block->fac = (int) (long) facilities; hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); tasklet_init(&vcpu->arch.tasklet, kvm_s390_tasklet, (unsigned long) vcpu); @@ -739,11 +742,29 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) static int __init kvm_s390_init(void) { - return kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); + int ret; + ret = kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); + if (ret) + return ret; + + /* + * guests can ask for up to 255+1 double words, we need a full page + * to hold the maximum amount of facilites. On the other hand, we + * only set facilities that are known to work in KVM. + */ + facilities = (unsigned long long *) get_zeroed_page(GFP_DMA); + if (!facilities) { + kvm_exit(); + return -ENOMEM; + } + stfle(facilities, 1); + facilities[0] &= 0xff00fff3f0700000ULL; + return 0; } static void __exit kvm_s390_exit(void) { + free_page((unsigned long) facilities); kvm_exit(); } diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 93ecd06e1a7..d426aac8095 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -158,7 +158,7 @@ static int handle_stfl(struct kvm_vcpu *vcpu) vcpu->stat.instruction_stfl++; /* only pass the facility bits, which we can handle */ - facility_list &= 0xfe00fff3; + facility_list &= 0xff00fff3; rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list), &facility_list, sizeof(facility_list)); -- cgit v1.2.3 From e3c7cb6ad7191e92ba89d00a7ae5f5dd1ca0c214 Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Tue, 16 Jun 2009 14:19:52 +0300 Subject: KVM: VMX: Handle vmx instruction vmexits IF a guest tries to use vmx instructions, inject a #UD to let it know the instruction is not implemented, rather than crashing. This prevents guest userspace from crashing the guest kernel. Cc: stable@kernel.org Signed-off-by: Avi Kivity --- arch/x86/kvm/vmx.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index e770bf349ec..356a0ce85c6 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3012,6 +3012,12 @@ static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) return 1; } +static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) +{ + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; +} + static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) { unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); @@ -3198,6 +3204,15 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, [EXIT_REASON_HLT] = handle_halt, [EXIT_REASON_INVLPG] = handle_invlpg, [EXIT_REASON_VMCALL] = handle_vmcall, + [EXIT_REASON_VMCLEAR] = handle_vmx_insn, + [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, + [EXIT_REASON_VMPTRLD] = handle_vmx_insn, + [EXIT_REASON_VMPTRST] = handle_vmx_insn, + [EXIT_REASON_VMREAD] = handle_vmx_insn, + [EXIT_REASON_VMRESUME] = handle_vmx_insn, + [EXIT_REASON_VMWRITE] = handle_vmx_insn, + [EXIT_REASON_VMOFF] = handle_vmx_insn, + [EXIT_REASON_VMON] = handle_vmx_insn, [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, [EXIT_REASON_APIC_ACCESS] = handle_apic_access, [EXIT_REASON_WBINVD] = handle_wbinvd, -- cgit v1.2.3 From 9e6996240afcbe61682eab8eeaeb65c34333164d Mon Sep 17 00:00:00 2001 From: Amit Shah Date: Mon, 15 Jun 2009 13:25:34 +0530 Subject: KVM: Ignore reads to K7 EVNTSEL MSRs In commit 7fe29e0faacb650d31b9e9f538203a157bec821d we ignored the reads to the P6 EVNTSEL MSRs. That fixed crashes on Intel machines. Ignore the reads to K7 EVNTSEL MSRs as well to fix this on AMD hosts. This fixes Kaspersky antivirus crashing Windows guests on AMD hosts. Signed-off-by: Amit Shah Signed-off-by: Avi Kivity --- arch/x86/kvm/x86.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 249540f9851..fe5474aec41 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -898,6 +898,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) case MSR_VM_HSAVE_PA: case MSR_P6_EVNTSEL0: case MSR_P6_EVNTSEL1: + case MSR_K7_EVNTSEL0: data = 0; break; case MSR_MTRRcap: -- cgit v1.2.3 From bde892232532ed522bb56b04576d07f91e59b3c7 Mon Sep 17 00:00:00 2001 From: Jaswinder Singh Rajput Date: Wed, 20 May 2009 09:59:35 +0530 Subject: KVM: shut up uninit compiler warning in paging_tmpl.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Dixes compilation warning: CC arch/x86/kernel/io_delay.o arch/x86/kvm/paging_tmpl.h: In function ‘paging64_fetch’: arch/x86/kvm/paging_tmpl.h:279: warning: ‘sptep’ may be used uninitialized in this function arch/x86/kvm/paging_tmpl.h: In function ‘paging32_fetch’: arch/x86/kvm/paging_tmpl.h:279: warning: ‘sptep’ may be used uninitialized in this function warning is bogus (always have a least one level), but need to shut the compiler up. Signed-off-by: Jaswinder Singh Rajput Signed-off-by: Avi Kivity --- arch/x86/kvm/paging_tmpl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 258e4591e1c..67785f63539 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -281,7 +281,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, { unsigned access = gw->pt_access; struct kvm_mmu_page *shadow_page; - u64 spte, *sptep; + u64 spte, *sptep = NULL; int direct; gfn_t table_gfn; int r; -- cgit v1.2.3 From 9a660a6e1a0ebef72cf792583777234483a40022 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Sun, 28 Jun 2009 16:26:13 +0000 Subject: arch/sh/boards/mach-se/7206/io.c: Remove unnecessary semicolons Signed-off-by: Joe Perches Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7206/io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c index 9c3a33210d6..180455642a4 100644 --- a/arch/sh/boards/mach-se/7206/io.c +++ b/arch/sh/boards/mach-se/7206/io.c @@ -50,7 +50,7 @@ unsigned char se7206_inb_p(unsigned long port) unsigned short se7206_inw(unsigned long port) { - return *port2adr(port);; + return *port2adr(port); } void se7206_outb(unsigned char value, unsigned long port) -- cgit v1.2.3 From ec87805c63a96e8863385d79c864801a572a4ab8 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 29 Jun 2009 07:40:00 +0000 Subject: sh: ms7724se: Enable sh_eth in defconfig. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/sh/configs/se7724_defconfig | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig index 3840270283e..3ee783a0a07 100644 --- a/arch/sh/configs/se7724_defconfig +++ b/arch/sh/configs/se7724_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.30 -# Thu Jun 18 16:09:05 2009 +# Mon Jun 29 16:28:43 2009 # CONFIG_SUPERH=y CONFIG_SUPERH32=y @@ -14,6 +14,7 @@ CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -28,7 +29,9 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_NO_VIRT_TO_BUS=y CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -88,10 +91,12 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y # # Performance Counters # +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y # CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y @@ -107,6 +112,10 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# # CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y @@ -119,7 +128,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -584,7 +593,6 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_SCSI_DEBUG is not set @@ -624,7 +632,7 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_STNIC is not set -# CONFIG_SH_ETH is not set +CONFIG_SH_ETH=y CONFIG_SMC91X=y # CONFIG_ENC28J60 is not set # CONFIG_ETHOC is not set @@ -801,6 +809,11 @@ CONFIG_SPI_BITBANG=y # # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_GPIO_SYSFS is not set @@ -851,6 +864,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y @@ -1196,6 +1211,7 @@ CONFIG_RTC_DRV_PCF8563=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1260,6 +1276,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y -- cgit v1.2.3 From 4078c444cf667f018c3fc7ebf141131a2b7c9480 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Mon, 29 Jun 2009 00:41:11 -0700 Subject: perf_counter, x86: Update x86_pmu after WARN() The print out should read the value before changing the value. Signed-off-by: Yinghai Lu Cc: Peter Zijlstra LKML-Reference: <4A487017.4090007@kernel.org> Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_counter.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index b83474b6021..d4cf4ce19aa 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -1496,17 +1496,17 @@ void __init init_hw_perf_counters(void) pr_cont("%s PMU driver.\n", x86_pmu.name); if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { - x86_pmu.num_counters = X86_PMC_MAX_GENERIC; WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", x86_pmu.num_counters, X86_PMC_MAX_GENERIC); + x86_pmu.num_counters = X86_PMC_MAX_GENERIC; } perf_counter_mask = (1 << x86_pmu.num_counters) - 1; perf_max_counters = x86_pmu.num_counters; if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { - x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); + x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; } perf_counter_mask |= -- cgit v1.2.3 From 59c5fe6d848cae8fd51498d17532f5aad3866f98 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 29 Jun 2009 12:11:50 +0100 Subject: [ARM] 5562/2: at91: add gpio button support for at91sam9g20ek This adds input keyboard gpio support on at91sam9g20ek board. It adds button 3 and 4. Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/board-sam9g20ek.c | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index cc270beadd5..a55398ed121 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include @@ -218,6 +220,56 @@ static struct gpio_led ek_leds[] = { } }; + +/* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button ek_buttons[] = { + { + .gpio = AT91_PIN_PA30, + .code = BTN_3, + .desc = "Button 3", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PA31, + .code = BTN_4, + .desc = "Button 4", + .active_low = 1, + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data ek_button_data = { + .buttons = ek_buttons, + .nbuttons = ARRAY_SIZE(ek_buttons), +}; + +static struct platform_device ek_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_button_data, + } +}; + +static void __init ek_add_device_buttons(void) +{ + at91_set_gpio_input(AT91_PIN_PA30, 1); /* btn3 */ + at91_set_deglitch(AT91_PIN_PA30, 1); + at91_set_gpio_input(AT91_PIN_PA31, 1); /* btn4 */ + at91_set_deglitch(AT91_PIN_PA31, 1); + + platform_device_register(&ek_button_device); +} +#else +static void __init ek_add_device_buttons(void) {} +#endif + + static struct i2c_board_info __initdata ek_i2c_devices[] = { { I2C_BOARD_INFO("24c512", 0x50), @@ -245,6 +297,8 @@ static void __init ek_board_init(void) at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LEDs */ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); + /* Push Buttons */ + ek_add_device_buttons(); /* PCK0 provides MCLK to the WM8731 */ at91_set_B_periph(AT91_PIN_PC1, 0); /* SSC (for WM8731) */ -- cgit v1.2.3 From c7ab48d2acaf959e4d59c3f55d12fdb7ca9afd7c Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Fri, 26 Jun 2009 19:10:36 +0100 Subject: intel-iommu: Clean up identity mapping code, remove CONFIG_DMAR_GFX_WA There's no need for the GFX workaround now we have 'iommu=pt' for the cases where people really care about performance. There's no need to have a special case for just one type of device. This also speeds up the iommu=pt path and reduces memory usage by setting up the si_domain _once_ and then using it for all devices, rather than giving each device its own private page tables. Signed-off-by: David Woodhouse --- arch/x86/Kconfig | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d1430ef6b4f..c07f7220590 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1913,25 +1913,14 @@ config DMAR_DEFAULT_ON recommended you say N here while the DMAR code remains experimental. -config DMAR_GFX_WA - def_bool y - prompt "Support for Graphics workaround" - depends on DMAR - ---help--- - Current Graphics drivers tend to use physical address - for DMA and avoid using DMA APIs. Setting this config - option permits the IOMMU driver to set a unity map for - all the OS-visible memory. Hence the driver can continue - to use physical addresses for DMA. - config DMAR_FLOPPY_WA def_bool y depends on DMAR ---help--- - Floppy disk drivers are know to bypass DMA API calls + Floppy disk drivers are known to bypass DMA API calls thereby failing to work when IOMMU is enabled. This workaround will setup a 1:1 mapping for the first - 16M to make floppy (an ISA device) work. + 16MiB to make floppy (an ISA device) work. config INTR_REMAP bool "Support for Interrupt Remapping (EXPERIMENTAL)" -- cgit v1.2.3 From 2be8412c6cef97b01dfaae71c04bf585d3d93a3b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Tue, 30 Jun 2009 14:02:00 -0700 Subject: [IA64] sprintf should not be used with same source & destination address This happens to work at the moment but isn't a good idea so fix it the simple way. Resolves-bug: http://bugzilla.kernel.org/show_bug.cgi?id=13576 Signed-off-by: Alan Cox Signed-off-by: Tony Luck --- arch/ia64/sn/kernel/io_common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c index 76645cf6ac5..25831c47c57 100644 --- a/arch/ia64/sn/kernel/io_common.c +++ b/arch/ia64/sn/kernel/io_common.c @@ -435,7 +435,8 @@ void sn_generate_path(struct pci_bus *pci_bus, char *address) bricktype = MODULE_GET_BTYPE(moduleid); if ((bricktype == L1_BRICKTYPE_191010) || (bricktype == L1_BRICKTYPE_1932)) - sprintf(address, "%s^%d", address, geo_slot(geoid)); + sprintf(address + strlen(address), "^%d", + geo_slot(geoid)); } void __devinit -- cgit v1.2.3 From 58782b34e9ffcc04619634efe9658263344ed188 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Sun, 28 Jun 2009 09:26:07 -0700 Subject: [IA64] Remove unnecessary semicolons Signed-off-by: Joe Perches Signed-off-by: Tony Luck --- arch/ia64/kernel/esi.c | 2 +- arch/ia64/kvm/process.c | 6 +++--- arch/ia64/kvm/vcpu.c | 2 +- arch/ia64/kvm/vtlb.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/ia64/kernel/esi.c b/arch/ia64/kernel/esi.c index ebf4e988e78..d5764a3d74a 100644 --- a/arch/ia64/kernel/esi.c +++ b/arch/ia64/kernel/esi.c @@ -65,7 +65,7 @@ static int __init esi_init (void) } if (!esi) - return -ENODEV;; + return -ENODEV; systab = __va(esi); diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c index a8f84da04b4..bb862fb224f 100644 --- a/arch/ia64/kvm/process.c +++ b/arch/ia64/kvm/process.c @@ -130,7 +130,7 @@ static void collect_interruption(struct kvm_vcpu *vcpu) if (vdcr & IA64_DCR_PP) { vpsr |= IA64_PSR_PP; } else { - vpsr &= ~IA64_PSR_PP;; + vpsr &= ~IA64_PSR_PP; } vcpu_set_psr(vcpu, vpsr); @@ -594,11 +594,11 @@ static void set_pal_call_data(struct kvm_vcpu *vcpu) p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); break; case PAL_BRAND_INFO: - p->u.pal_data.gr29 = gr29;; + p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); break; default: - p->u.pal_data.gr29 = gr29;; + p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); } p->u.pal_data.gr28 = gr28; diff --git a/arch/ia64/kvm/vcpu.c b/arch/ia64/kvm/vcpu.c index a2c6c15e476..46b02cbcc87 100644 --- a/arch/ia64/kvm/vcpu.c +++ b/arch/ia64/kvm/vcpu.c @@ -406,7 +406,7 @@ void getreg(unsigned long regnum, unsigned long *val, * Now look at registers in [0-31] range and init correct UNAT */ addr = (unsigned long)regs; - unat = ®s->eml_unat;; + unat = ®s->eml_unat; addr += gr_info[regnum]; diff --git a/arch/ia64/kvm/vtlb.c b/arch/ia64/kvm/vtlb.c index 4290a429bf7..20b3852f7a6 100644 --- a/arch/ia64/kvm/vtlb.c +++ b/arch/ia64/kvm/vtlb.c @@ -135,7 +135,7 @@ struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type) u64 rid; rid = vcpu_get_rr(vcpu, va); - rid = rid & RR_RID_MASK;; + rid = rid & RR_RID_MASK; if (type == D_TLB) { if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; @@ -518,7 +518,7 @@ struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data) struct thash_cb *hcb = &v->arch.vtlb; - cch = __vtr_lookup(v, va, is_data);; + cch = __vtr_lookup(v, va, is_data); if (cch) return cch; -- cgit v1.2.3 From fa276f36f3d8743295e067fb483b42dca8bd1ece Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 30 Jun 2009 12:01:57 +0100 Subject: [IA64] address compiler warnings perfmon.c/salinfo.c perfmon.c has a dubious cast directly from "int" to "void *". Add an intermediate cast to "long" to keep gcc happy. salinfo.c uses "down_trylock()" in a highly creative way (explained in the comments in the file) ... but it does kick out this warning: arch/ia64/kernel/salinfo.c:195: warning: ignoring return value of 'down_trylock' which people occasionally try to "fix" in ways that do not work. Use some casts to keep gcc quiet. Signed-off-by: Jan Beulich Signed-off-by: Tony Luck --- arch/ia64/kernel/perfmon.c | 2 +- arch/ia64/kernel/salinfo.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index abce2468a40..f1782705b1f 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -5603,7 +5603,7 @@ pfm_interrupt_handler(int irq, void *arg) * /proc/perfmon interface, for debug only */ -#define PFM_PROC_SHOW_HEADER ((void *)nr_cpu_ids+1) +#define PFM_PROC_SHOW_HEADER ((void *)(long)nr_cpu_ids+1) static void * pfm_proc_start(struct seq_file *m, loff_t *pos) diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c index 7053c55b764..e6676fca482 100644 --- a/arch/ia64/kernel/salinfo.c +++ b/arch/ia64/kernel/salinfo.c @@ -192,7 +192,7 @@ struct salinfo_platform_oemdata_parms { static void salinfo_work_to_do(struct salinfo_data *data) { - down_trylock(&data->mutex); + (void)(down_trylock(&data->mutex) ?: 0); up(&data->mutex); } -- cgit v1.2.3 From b01e8dc34379f4ba2f454390e340a025edbaaa7e Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Tue, 30 Jun 2009 11:41:18 -0700 Subject: alpha: fix percpu build breakage alpha percpu access requires custom SHIFT_PERCPU_PTR() definition for modules to work around addressing range limitation. This is done via generating inline assembly using C preprocessing which forces the assembler to generate external reference. This happens behind the compiler's back and makes the compiler think that static percpu variables in modules are unused. This used to be worked around by using __unused attribute for percpu variables which prevent the compiler from omitting the variable; however, recent declare/definition attribute unification change broke this as __used can't be used for declaration. Also, in the process, PER_CPU_ATTRIBUTES definition in alpha percpu.h got broken. This patch adds PER_CPU_DEF_ATTRIBUTES which is only used for definitions and make alpha use it to add __used for percpu variables in modules. This also fixes the PER_CPU_ATTRIBUTES double definition bug. Signed-off-by: Tejun Heo Tested-by: maximilian attems Acked-by: Ivan Kokshaysky Cc: Richard Henderson Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/include/asm/percpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/alpha/include/asm/percpu.h b/arch/alpha/include/asm/percpu.h index 06c5c7a4afd..b663f1f10b6 100644 --- a/arch/alpha/include/asm/percpu.h +++ b/arch/alpha/include/asm/percpu.h @@ -30,7 +30,7 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; #ifndef MODULE #define SHIFT_PERCPU_PTR(var, offset) RELOC_HIDE(&per_cpu_var(var), (offset)) -#define PER_CPU_ATTRIBUTES +#define PER_CPU_DEF_ATTRIBUTES #else /* * To calculate addresses of locally defined variables, GCC uses 32-bit @@ -49,7 +49,7 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; : "=&r"(__ptr), "=&r"(tmp_gp)); \ (typeof(&per_cpu_var(var)))(__ptr + (offset)); }) -#define PER_CPU_ATTRIBUTES __used +#define PER_CPU_DEF_ATTRIBUTES __used #endif /* MODULE */ @@ -71,7 +71,7 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; #define __get_cpu_var(var) per_cpu_var(var) #define __raw_get_cpu_var(var) per_cpu_var(var) -#define PER_CPU_ATTRIBUTES +#define PER_CPU_DEF_ATTRIBUTES #endif /* SMP */ -- cgit v1.2.3 From 66918dcdf91ad101194c749c18099e836ba3de2b Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Tue, 30 Jun 2009 11:41:37 -0700 Subject: x86: only clear node_states for 64bit Nathan reported that | commit 73d60b7f747176dbdff826c4127d22e1fd3f9f74 | Author: Yinghai Lu | Date: Tue Jun 16 15:33:00 2009 -0700 | | page-allocator: clear N_HIGH_MEMORY map before we set it again | | SRAT tables may contains nodes of very small size. The arch code may | decide to not activate such a node. However, currently the early boot | code sets N_HIGH_MEMORY for such nodes. These nodes therefore seem to be | active although these nodes have no present pages. | | For 64bit N_HIGH_MEMORY == N_NORMAL_MEMORY, so that works for 64 bit too unintentionally and incorrectly clears the cpuset.mems cgroup attribute on an i386 kvm guest, meaning that cpuset.mems can not be used. Fix this by only clearing node_states[N_NORMAL_MEMORY] for 64bit only. and need to do save/restore for that in find_zone_movable_pfn Reported-by: Nathan Lynch Tested-by: Nathan Lynch Signed-off-by: Yinghai Lu Cc: Christoph Lameter Cc: Ingo Molnar , Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/x86/mm/init_64.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index c4378f4fd4a..b177652251a 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -598,6 +598,8 @@ void __init paging_init(void) sparse_memory_present_with_active_regions(MAX_NUMNODES); sparse_init(); + /* clear the default setting with node 0 */ + nodes_clear(node_states[N_NORMAL_MEMORY]); free_area_init_nodes(max_zone_pfns); } -- cgit v1.2.3 From aee3ff1b413cff44e7d91dd1901cacd8988ce9cf Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 30 Jun 2009 22:24:54 +0100 Subject: FRV: Wire up new syscalls Wire up new syscalls rt_tgsigqueueinfo and perf_counter_open. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/frv/include/asm/unistd.h | 4 +++- arch/frv/kernel/entry.S | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h index 96d78d5d2c4..4a8fb427ce0 100644 --- a/arch/frv/include/asm/unistd.h +++ b/arch/frv/include/asm/unistd.h @@ -341,10 +341,12 @@ #define __NR_inotify_init1 332 #define __NR_preadv 333 #define __NR_pwritev 334 +#define __NR_rt_tgsigqueueinfo 335 +#define __NR_perf_counter_open 336 #ifdef __KERNEL__ -#define NR_syscalls 335 +#define NR_syscalls 337 #define __ARCH_WANT_IPC_PARSE_VERSION /* #define __ARCH_WANT_OLD_READDIR */ diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S index 356e0e327a8..fde1e446b44 100644 --- a/arch/frv/kernel/entry.S +++ b/arch/frv/kernel/entry.S @@ -1524,5 +1524,7 @@ sys_call_table: .long sys_inotify_init1 .long sys_preadv .long sys_pwritev + .long sys_rt_tgsigqueueinfo /* 335 */ + .long sys_perf_counter_open syscall_table_size = (. - sys_call_table) -- cgit v1.2.3 From 6086071005674eb982d898c75269c931240154cf Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 30 Jun 2009 22:33:15 +0100 Subject: MN10300: Wire up new syscalls Wire up new syscalls rt_tgsigqueueinfo and perf_counter_open. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/include/asm/unistd.h | 4 +++- arch/mn10300/kernel/entry.S | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h index fef5b434dad..fad68616af3 100644 --- a/arch/mn10300/include/asm/unistd.h +++ b/arch/mn10300/include/asm/unistd.h @@ -346,10 +346,12 @@ #define __NR_inotify_init1 333 #define __NR_preadv 334 #define __NR_pwritev 335 +#define __NR_rt_tgsigqueueinfo 336 +#define __NR_perf_counter_open 337 #ifdef __KERNEL__ -#define NR_syscalls 326 +#define NR_syscalls 338 /* * specify the deprecated syscalls we want to support on this arch diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S index 7408a27199f..e0d2563af4f 100644 --- a/arch/mn10300/kernel/entry.S +++ b/arch/mn10300/kernel/entry.S @@ -722,6 +722,8 @@ ENTRY(sys_call_table) .long sys_inotify_init1 .long sys_preadv .long sys_pwritev /* 335 */ + .long sys_rt_tgsigqueueinfo + .long sys_perf_counter_open nr_syscalls=(.-sys_call_table)/4 -- cgit v1.2.3 From 84f7597c116f811cfcb762e645fa258b7e585155 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 1 Jul 2009 04:55:35 +0000 Subject: sh: fix se7724 ceu names Use "ceu0" and "ceu1" as CEU names instead of "ceu". This fixes "memchunk" kernel command line selection on the solution engine 7724 board. With this patch applied use "memchunk.ceu0=1m" or "memchunk.ceu1=1m" on kernel command line to override physically memory size to one meg for CEU0 or CEU1. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7724/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index 21d18005fb4..c050a8d76df 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -454,7 +454,7 @@ static int __init devices_setup(void) gpio_request(GPIO_FN_VIO0_CLK, NULL); gpio_request(GPIO_FN_VIO0_FLD, NULL); gpio_request(GPIO_FN_VIO0_HD, NULL); - platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20); + platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); /* enable CEU1 */ gpio_request(GPIO_FN_VIO1_D7, NULL); @@ -469,7 +469,7 @@ static int __init devices_setup(void) gpio_request(GPIO_FN_VIO1_HD, NULL); gpio_request(GPIO_FN_VIO1_VD, NULL); gpio_request(GPIO_FN_VIO1_CLK, NULL); - platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20); + platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); /* KEYSC */ gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); -- cgit v1.2.3 From 0802d9e55cc6be6bd1b13f9dc9ef5aa6d24bca77 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 1 Jul 2009 05:16:31 +0000 Subject: sh: re-add LCDC fbdev support to the Migo-R defconfig Re-add LCDC fbdev support to the Migo-R defconfig. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/configs/migor_defconfig | 53 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig index da627d22c00..b18cfd39cac 100644 --- a/arch/sh/configs/migor_defconfig +++ b/arch/sh/configs/migor_defconfig @@ -309,7 +309,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000 CONFIG_BOOT_LINK_OFFSET=0x00800000 CONFIG_ENTRY_OFFSET=0x00001000 CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp" +CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp" # # Bus options @@ -858,7 +858,35 @@ CONFIG_VIDEO_SH_MOBILE_CEU=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_SH_MOBILE_LCDC=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -870,6 +898,27 @@ CONFIG_VIDEO_SH_MOBILE_CEU=y # Console display driver support # CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +CONFIG_LOGO_SUPERH_VGA16=y +# CONFIG_LOGO_SUPERH_CLUT224 is not set # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -- cgit v1.2.3 From 3238c0c4d68d9a9022b411a11a4b933fbdb53a14 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Wed, 1 Jul 2009 18:56:16 +0100 Subject: intel-iommu: Make iommu=pt work on i386 too Signed-off-by: David Woodhouse --- arch/x86/kernel/pci-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 47630479b06..1a041bcf506 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -211,11 +211,11 @@ static __init int iommu_setup(char *p) #ifdef CONFIG_SWIOTLB if (!strncmp(p, "soft", 4)) swiotlb = 1; +#endif if (!strncmp(p, "pt", 2)) { iommu_pass_through = 1; return 1; } -#endif gart_parse_options(p); -- cgit v1.2.3 From 788d84bba47ea3eb377f7a3ae4fd1ee84b84877b Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Wed, 1 Jul 2009 18:34:52 +0100 Subject: Fix pci_unmap_addr() et al on i386. We can run a 32-bit kernel on boxes with an IOMMU, so we need pci_unmap_addr() etc. to work -- without it, drivers will leak mappings. To be honest, this whole thing looks like it's more pain than it's worth; I'm half inclined to remove the no-op #else case altogether. But this is the minimal fix, which just does the right thing if CONFIG_DMAR is set. Signed-off-by: David Woodhouse Cc: stable@kernel.org [ for 2.6.30 ] Signed-off-by: Linus Torvalds --- arch/x86/include/asm/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 927958d13c1..1ff685ca221 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -91,7 +91,7 @@ extern void pci_iommu_alloc(void); #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) -#if defined(CONFIG_X86_64) || defined(CONFIG_DMA_API_DEBUG) +#if defined(CONFIG_X86_64) || defined(CONFIG_DMAR) || defined(CONFIG_DMA_API_DEBUG) #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ dma_addr_t ADDR_NAME; -- cgit v1.2.3 From 34e19ada994fb9cb3d11873f2b734602e2135f3a Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Wed, 1 Jul 2009 18:14:18 +0000 Subject: sh: Fix compiler error and include the definition of IS_ERR_VALUE When arch/sh/include/asm/syscall_32.h is included from a file that doesn't also include linux/err.h the following error is produced, In file included from /home/matt/src/kernels/sh-2.6/arch/sh/include/asm/syscall.h:5, from kernel/trace/trace_syscalls.c:3: /home/matt/src/kernels/sh-2.6/arch/sh/include/asm/syscall_32.h: In function 'syscall_get_error': /home/matt/src/kernels/sh-2.6/arch/sh/include/asm/syscall_32.h:28: error: implicit declaration of function 'IS_ERR_VALUE' make[2]: *** [kernel/trace/trace_syscalls.o] Error 1 make[1]: *** [kernel/trace] Error 2 make: *** [kernel] Error 2 Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt --- arch/sh/include/asm/syscall_32.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/include/asm/syscall_32.h b/arch/sh/include/asm/syscall_32.h index 5bc34681d99..6f83f2cc45c 100644 --- a/arch/sh/include/asm/syscall_32.h +++ b/arch/sh/include/asm/syscall_32.h @@ -3,6 +3,7 @@ #include #include +#include #include /* The system call number is given by the user in R3 */ -- cgit v1.2.3 From 00460f41fffc0435dbb6ab4b058a190163d57ce6 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 2 Jul 2009 00:46:16 +0100 Subject: FRV: Implement atomic64_t Implement atomic64_t and its ops for FRV. Tested with the following patch: diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c index 55e4fab..086d50d 100644 --- a/arch/frv/kernel/setup.c +++ b/arch/frv/kernel/setup.c @@ -746,6 +746,52 @@ static void __init parse_cmdline_early(char *cmdline) } /* end parse_cmdline_early() */ +static atomic64_t xxx; + +static void test_atomic64(void) +{ + atomic64_set(&xxx, 0x12300000023LL); + + mb(); + BUG_ON(atomic64_read(&xxx) != 0x12300000023LL); + mb(); + if (atomic64_inc_return(&xxx) != 0x12300000024LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x12300000024LL); + mb(); + if (atomic64_sub_return(0x36900000050LL, &xxx) != -0x2460000002cLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != -0x2460000002cLL); + mb(); + if (atomic64_dec_return(&xxx) != -0x2460000002dLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != -0x2460000002dLL); + mb(); + if (atomic64_add_return(0x36800000001LL, &xxx) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL); + mb(); + if (atomic64_cmpxchg(&xxx, 0x123456789abcdefLL, 0x121ffffffd4LL) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL); + mb(); + if (atomic64_cmpxchg(&xxx, 0x121ffffffd4LL, 0x123456789abcdefLL) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x123456789abcdefLL); + mb(); + if (atomic64_xchg(&xxx, 0xabcdef123456789LL) != 0x123456789abcdefLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0xabcdef123456789LL); + mb(); +} + /*****************************************************************************/ /* * @@ -845,6 +891,8 @@ void __init setup_arch(char **cmdline_p) // asm volatile("movgs %0,timerd" :: "r"(10000000)); // __set_HSR(0, __get_HSR(0) | HSR0_ETMD); + test_atomic64(); + } /* end setup_arch() */ #if 0 Note that this doesn't cover all the trivial wrappers, but does cover all the substantial implementations. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/frv/include/asm/atomic.h | 68 +++++++++++++++++- arch/frv/include/asm/system.h | 2 + arch/frv/kernel/frv_ksyms.c | 4 ++ arch/frv/lib/Makefile | 2 +- arch/frv/lib/atomic-ops.S | 3 +- arch/frv/lib/atomic64-ops.S | 162 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 236 insertions(+), 5 deletions(-) create mode 100644 arch/frv/lib/atomic64-ops.S (limited to 'arch') diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h index 0409d981fd3..00a57af79af 100644 --- a/arch/frv/include/asm/atomic.h +++ b/arch/frv/include/asm/atomic.h @@ -121,10 +121,72 @@ static inline void atomic_dec(atomic_t *v) #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) +/* + * 64-bit atomic ops + */ +typedef struct { + volatile long long counter; +} atomic64_t; + +#define ATOMIC64_INIT(i) { (i) } + +static inline long long atomic64_read(atomic64_t *v) +{ + long long counter; + + asm("ldd%I1 %M1,%0" + : "=e"(counter) + : "m"(v->counter)); + return counter; +} + +static inline void atomic64_set(atomic64_t *v, long long i) +{ + asm volatile("std%I0 %1,%M0" + : "=m"(v->counter) + : "e"(i)); +} + +extern long long atomic64_inc_return(atomic64_t *v); +extern long long atomic64_dec_return(atomic64_t *v); +extern long long atomic64_add_return(long long i, atomic64_t *v); +extern long long atomic64_sub_return(long long i, atomic64_t *v); + +static inline long long atomic64_add_negative(long long i, atomic64_t *v) +{ + return atomic64_add_return(i, v) < 0; +} + +static inline void atomic64_add(long long i, atomic64_t *v) +{ + atomic64_add_return(i, v); +} + +static inline void atomic64_sub(long long i, atomic64_t *v) +{ + atomic64_sub_return(i, v); +} + +static inline void atomic64_inc(atomic64_t *v) +{ + atomic64_inc_return(v); +} + +static inline void atomic64_dec(atomic64_t *v) +{ + atomic64_dec_return(v); +} + +#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) +#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) +#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0) + /*****************************************************************************/ /* * exchange value with memory */ +extern uint64_t __xchg_64(uint64_t i, volatile void *v); + #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS #define xchg(ptr, x) \ @@ -174,8 +236,10 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v); #define tas(ptr) (xchg((ptr), 1)) -#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) +#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new)) +#define atomic_xchg(v, new) (xchg(&(v)->counter, new)) +#define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter)) +#define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter)) static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) { diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h index 7742ec000cc..efd22d9077a 100644 --- a/arch/frv/include/asm/system.h +++ b/arch/frv/include/asm/system.h @@ -208,6 +208,8 @@ extern void free_initmem(void); * - if (*ptr == test) then orig = *ptr; *ptr = test; * - if (*ptr != test) then orig = *ptr; */ +extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v); + #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS #define cmpxchg(ptr, test, new) \ diff --git a/arch/frv/kernel/frv_ksyms.c b/arch/frv/kernel/frv_ksyms.c index 0316b3c50ef..a89803b58b9 100644 --- a/arch/frv/kernel/frv_ksyms.c +++ b/arch/frv/kernel/frv_ksyms.c @@ -67,6 +67,10 @@ EXPORT_SYMBOL(atomic_sub_return); EXPORT_SYMBOL(__xchg_32); EXPORT_SYMBOL(__cmpxchg_32); #endif +EXPORT_SYMBOL(atomic64_add_return); +EXPORT_SYMBOL(atomic64_sub_return); +EXPORT_SYMBOL(__xchg_64); +EXPORT_SYMBOL(__cmpxchg_64); EXPORT_SYMBOL(__debug_bug_printk); EXPORT_SYMBOL(__delay_loops_MHz); diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile index 08be305c9f4..4ff2fb1e6b1 100644 --- a/arch/frv/lib/Makefile +++ b/arch/frv/lib/Makefile @@ -4,5 +4,5 @@ lib-y := \ __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ - checksum.o memcpy.o memset.o atomic-ops.o \ + checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \ outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o diff --git a/arch/frv/lib/atomic-ops.S b/arch/frv/lib/atomic-ops.S index ee0ac905fb0..5e9e6ab5dd0 100644 --- a/arch/frv/lib/atomic-ops.S +++ b/arch/frv/lib/atomic-ops.S @@ -163,11 +163,10 @@ __cmpxchg_32: ld.p @(gr11,gr0),gr8 orcr cc7,cc7,cc3 subcc gr8,gr9,gr7,icc0 - bne icc0,#0,1f + bnelr icc0,#0 cst.p gr10,@(gr11,gr0) ,cc3,#1 corcc gr29,gr29,gr0 ,cc3,#1 beq icc3,#0,0b -1: bralr .size __cmpxchg_32, .-__cmpxchg_32 diff --git a/arch/frv/lib/atomic64-ops.S b/arch/frv/lib/atomic64-ops.S new file mode 100644 index 00000000000..b6194eeac12 --- /dev/null +++ b/arch/frv/lib/atomic64-ops.S @@ -0,0 +1,162 @@ +/* kernel atomic64 operations + * + * For an explanation of how atomic ops work in this arch, see: + * Documentation/frv/atomic-ops.txt + * + * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include + + .text + .balign 4 + + +############################################################################### +# +# long long atomic64_inc_return(atomic64_t *v) +# +############################################################################### + .globl atomic64_inc_return + .type atomic64_inc_return,@function +atomic64_inc_return: + or.p gr8,gr8,gr10 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 /* set CC3 to true */ + addicc gr9,#1,gr9,icc0 + addxi gr8,#0,gr8,icc0 + cstd.p gr8,@(gr10,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size atomic64_inc_return, .-atomic64_inc_return + +############################################################################### +# +# long long atomic64_dec_return(atomic64_t *v) +# +############################################################################### + .globl atomic64_dec_return + .type atomic64_dec_return,@function +atomic64_dec_return: + or.p gr8,gr8,gr10 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 /* set CC3 to true */ + subicc gr9,#1,gr9,icc0 + subxi gr8,#0,gr8,icc0 + cstd.p gr8,@(gr10,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size atomic64_dec_return, .-atomic64_dec_return + +############################################################################### +# +# long long atomic64_add_return(long long i, atomic64_t *v) +# +############################################################################### + .globl atomic64_add_return + .type atomic64_add_return,@function +atomic64_add_return: + or.p gr8,gr8,gr4 + or gr9,gr9,gr5 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 /* set CC3 to true */ + addcc gr9,gr5,gr9,icc0 + addx gr8,gr4,gr8,icc0 + cstd.p gr8,@(gr10,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size atomic64_add_return, .-atomic64_add_return + +############################################################################### +# +# long long atomic64_sub_return(long long i, atomic64_t *v) +# +############################################################################### + .globl atomic64_sub_return + .type atomic64_sub_return,@function +atomic64_sub_return: + or.p gr8,gr8,gr4 + or gr9,gr9,gr5 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 /* set CC3 to true */ + subcc gr9,gr5,gr9,icc0 + subx gr8,gr4,gr8,icc0 + cstd.p gr8,@(gr10,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size atomic64_sub_return, .-atomic64_sub_return + +############################################################################### +# +# uint64_t __xchg_64(uint64_t i, uint64_t *v) +# +############################################################################### + .globl __xchg_64 + .type __xchg_64,@function +__xchg_64: + or.p gr8,gr8,gr4 + or gr9,gr9,gr5 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 /* set CC3 to true */ + cstd.p gr4,@(gr10,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size __xchg_64, .-__xchg_64 + +############################################################################### +# +# uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v) +# +############################################################################### + .globl __cmpxchg_64 + .type __cmpxchg_64,@function +__cmpxchg_64: + or.p gr8,gr8,gr4 + or gr9,gr9,gr5 +0: + orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ + ckeq icc3,cc7 + ldd.p @(gr12,gr0),gr8 /* LDD.P/ORCR must be atomic */ + orcr cc7,cc7,cc3 + subcc gr8,gr4,gr0,icc0 + subcc.p gr9,gr5,gr0,icc1 + bnelr icc0,#0 + bnelr icc1,#0 + cstd.p gr10,@(gr12,gr0) ,cc3,#1 + corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ + beq icc3,#0,0b + bralr + + .size __cmpxchg_64, .-__cmpxchg_64 + -- cgit v1.2.3 From 42ca4fb69126dd9d0e25112edca1cacf846aa5c3 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 2 Jul 2009 00:46:21 +0100 Subject: FRV: Add basic performance counter support Add basic performance counter support to the FRV arch. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/frv/Kconfig | 1 + arch/frv/include/asm/perf_counter.h | 17 +++++++++++++++++ arch/frv/lib/Makefile | 2 +- arch/frv/lib/perf_counter.c | 19 +++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 arch/frv/include/asm/perf_counter.h create mode 100644 arch/frv/lib/perf_counter.c (limited to 'arch') diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index 8a5bd7a9c6f..b86e19c9b5b 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -7,6 +7,7 @@ config FRV default y select HAVE_IDE select HAVE_ARCH_TRACEHOOK + select HAVE_PERF_COUNTERS config ZONE_DMA bool diff --git a/arch/frv/include/asm/perf_counter.h b/arch/frv/include/asm/perf_counter.h new file mode 100644 index 00000000000..ccf726e61b2 --- /dev/null +++ b/arch/frv/include/asm/perf_counter.h @@ -0,0 +1,17 @@ +/* FRV performance counter support + * + * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_PERF_COUNTER_H +#define _ASM_PERF_COUNTER_H + +#define PERF_COUNTER_INDEX_OFFSET 0 + +#endif /* _ASM_PERF_COUNTER_H */ diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile index 4ff2fb1e6b1..0a377210c89 100644 --- a/arch/frv/lib/Makefile +++ b/arch/frv/lib/Makefile @@ -5,4 +5,4 @@ lib-y := \ __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \ - outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o + outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o perf_counter.o diff --git a/arch/frv/lib/perf_counter.c b/arch/frv/lib/perf_counter.c new file mode 100644 index 00000000000..2000feecd57 --- /dev/null +++ b/arch/frv/lib/perf_counter.c @@ -0,0 +1,19 @@ +/* Performance counter handling + * + * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#include + +/* + * mark the performance counter as pending + */ +void set_perf_counter_pending(void) +{ +} -- cgit v1.2.3 From 43644679a1e80f53e6e0155ab75b1093ba3c0365 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 2 Jul 2009 12:05:10 -0700 Subject: x86: fix power-of-2 round_up/round_down macros These macros had two bugs: - the type of the mask was not correctly expanded to the full size of the argument being expanded, resulting in possible loss of high bits when mixing types. - the alignment argument was evaluated twice, despite the macro looking like a fancy function (but it really does need to be a macro, since it works on arbitrary integer types) Noticed by Peter Anvin, and with a fix that is a modification of his suggestion (bug noticed by Yinghai Lu). Cc: Peter Anvin Cc: Yinghai Lu Signed-off-by: Linus Torvalds --- arch/x86/include/asm/proto.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/proto.h b/arch/x86/include/asm/proto.h index 49fb3ecf3bb..621f56d7312 100644 --- a/arch/x86/include/asm/proto.h +++ b/arch/x86/include/asm/proto.h @@ -22,7 +22,14 @@ extern int reboot_force; long do_arch_prctl(struct task_struct *task, int code, unsigned long addr); -#define round_up(x, y) (((x) + (y) - 1) & ~((y) - 1)) -#define round_down(x, y) ((x) & ~((y) - 1)) +/* + * This looks more complex than it should be. But we need to + * get the type for the ~ right in round_down (it needs to be + * as wide as the result!), and we want to evaluate the macro + * arguments just once each. + */ +#define __round_mask(x,y) ((__typeof__(x))((y)-1)) +#define round_up(x,y) ((((x)-1) | __round_mask(x,y))+1) +#define round_down(x,y) ((x) & ~__round_mask(x,y)) #endif /* _ASM_X86_PROTO_H */ -- cgit v1.2.3 From 7c5371c403abb29f01bc6cff6c5096abdf2dc524 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 1 Jul 2009 12:32:18 -0700 Subject: x86: add boundary check for 32bit res before expand e820 resource to alignment fix hang with HIGHMEM_64G and 32bit resource. According to hpa and Linus, use (resource_size_t)-1 to fend off big ranges. Analyzed by hpa Reported-and-tested-by: Mikael Pettersson Signed-off-by: Yinghai Lu Signed-off-by: Linus Torvalds --- arch/x86/kernel/e820.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 7271fa33d79..c4ca89d9aaf 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -1383,6 +1383,8 @@ static unsigned long ram_alignment(resource_size_t pos) return 32*1024*1024; } +#define MAX_RESOURCE_SIZE ((resource_size_t)-1) + void __init e820_reserve_resources_late(void) { int i; @@ -1400,17 +1402,19 @@ void __init e820_reserve_resources_late(void) * avoid stolen RAM: */ for (i = 0; i < e820.nr_map; i++) { - struct e820entry *entry = &e820_saved.map[i]; - resource_size_t start, end; + struct e820entry *entry = &e820.map[i]; + u64 start, end; if (entry->type != E820_RAM) continue; start = entry->addr + entry->size; - end = round_up(start, ram_alignment(start)); - if (start == end) + end = round_up(start, ram_alignment(start)) - 1; + if (end > MAX_RESOURCE_SIZE) + end = MAX_RESOURCE_SIZE; + if (start >= end) continue; - reserve_region_with_split(&iomem_resource, start, - end - 1, "RAM buffer"); + reserve_region_with_split(&iomem_resource, start, end, + "RAM buffer"); } } -- cgit v1.2.3