From 65cb15a686cedab52abc336d7a400fe3a110ac4c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 18 Sep 2009 14:31:48 +1000 Subject: drm/radeon: avivo chips have no separate int bit for display display interrupts are not enabled via this register, the DISPLAY_INT bit is a status only to show that other regs need to be read. Noticed by Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/rs600.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index c31bd843925..6af0331cae0 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -272,11 +272,9 @@ int rs600_irq_set(struct radeon_device *rdev) tmp |= RADEON_SW_INT_ENABLE; } if (rdev->irq.crtc_vblank_int[0]) { - tmp |= AVIVO_DISPLAY_INT_STATUS; mode_int |= AVIVO_D1MODE_INT_MASK; } if (rdev->irq.crtc_vblank_int[1]) { - tmp |= AVIVO_DISPLAY_INT_STATUS; mode_int |= AVIVO_D2MODE_INT_MASK; } WREG32(RADEON_GEN_INT_CNTL, tmp); -- cgit v1.2.3