From a6c0c37db654444dfce91cd75ad8a56bb15a0d25 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 15 Oct 2008 22:03:44 -0700 Subject: radeonfb: misc cleanup of engine and dst cache handling Fix a couple of incomplete tests of the chip families in the engine init/reset code and proper initialization of the destination cache mode. The result should better match what the latest X radeon driver does. Signed-off-by: Benjamin Herrenschmidt Acked-by: David S. Miller Cc: Krzysztof Halasa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/aty/radeonfb.h | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) (limited to 'drivers/video/aty/radeonfb.h') diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h index ccbfffd1280..3ea1b00fdd2 100644 --- a/drivers/video/aty/radeonfb.h +++ b/drivers/video/aty/radeonfb.h @@ -53,6 +53,7 @@ enum radeon_family { CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ CHIP_FAMILY_R420, /* R420/R423/M18 */ CHIP_FAMILY_RC410, + CHIP_FAMILY_RS400, CHIP_FAMILY_RS480, CHIP_FAMILY_LAST, }; @@ -533,33 +534,39 @@ static inline u32 radeon_get_dstbpp(u16 depth) /* * 2D Engine helper routines */ -static inline void radeon_engine_flush (struct radeonfb_info *rinfo) + +static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) { int i; - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + for (i=0; i<2000000; i++) { + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) return; udelay(1); } - printk(KERN_ERR "radeonfb: Flush Timeout !\n"); + printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); } - -static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +static inline void radeon_engine_flush (struct radeonfb_info *rinfo) { int i; - for (i=0; i<2000000; i++) { - if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + /* Initiate flush */ + OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + /* Ensure FIFO is empty, ie, make sure the flush commands + * has reached the cache + */ + _radeon_fifo_wait (rinfo, 64); + + /* Wait for the flush to complete */ + for (i=0; i < 2000000; i++) { + if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) return; udelay(1); } - printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); + printk(KERN_ERR "radeonfb: Flush Timeout !\n"); } -- cgit v1.2.3