From 3c8cd0cce9ab8a25dbcf519cb0de00d2716f8379 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Wed, 6 Dec 2006 17:25:04 +0100 Subject: [ARM] 3992/1: i.MX/MX1 CPU Frequency scaling support Support to change MX1 CPU frequency at runtime. Tested on PiKRON's PiMX1 board and seems to be fully stable up to 200 MHz end even as low as 8 MHz. Signed-off-by: Pavel Pisa Signed-off-by: Russell King --- include/asm-arm/arch-imx/imx-regs.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'include/asm-arm/arch-imx/imx-regs.h') diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index a6912b3d867..e56a4e247d6 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -41,7 +41,13 @@ /* PLL registers */ #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_SPLL_RESTART (1<<22) +#define CSCR_MPLL_RESTART (1<<21) +#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_BCLK_DIV (0xf<<10) +#define CSCR_MPU_PRESC (1<<15) +#define CSCR_SPEN (1<<1) +#define CSCR_MPEN (1<<0) #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ @@ -49,8 +55,6 @@ #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ -#define CSCR_MPLL_RESTART (1<<21) - /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D -- cgit v1.2.3