From 3e062b07ada88edb9ffdd147e39c7df4b4418f64 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 5 Jun 2007 16:36:55 +0100 Subject: [ARM] 4430/1: davinci: clock control support Support clock control driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov Signed-off-by: Kevin Hilman Signed-off-by: Russell King --- include/asm-arm/arch-davinci/clock.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/asm-arm/arch-davinci/clock.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h new file mode 100644 index 00000000000..cc168b7a14f --- /dev/null +++ b/include/asm-arm/arch-davinci/clock.h @@ -0,0 +1,22 @@ +/* + * include/asm-arm/arch-davinci/clock.h + * + * Clock control driver for DaVinci - header file + * + * Authors: Vladimir Barinov + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_CLOCK_H +#define __ASM_ARCH_DAVINCI_CLOCK_H + +struct clk; + +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); +extern int davinci_clk_init(void); + +#endif -- cgit v1.2.3 From 3d9edf09d4525dad95f98b31f31aa86b8071fab9 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 10 Jul 2007 13:03:43 +0100 Subject: [ARM] 4457/2: davinci: GPIO support Support GPIO driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov Acked-by: David Brownell Acked-by: Kevin Hilman Signed-off-by: Russell King --- include/asm-arm/arch-davinci/gpio.h | 156 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-davinci/hardware.h | 38 ++++++++ 2 files changed, 194 insertions(+) create mode 100644 include/asm-arm/arch-davinci/gpio.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h new file mode 100644 index 00000000000..ea24a0e0bfd --- /dev/null +++ b/include/asm-arm/arch-davinci/gpio.h @@ -0,0 +1,156 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DAVINCI_GPIO_H +#define __DAVINCI_GPIO_H + +/* + * basic gpio routines + * + * board-specific init should be done by arch/.../.../board-XXX.c (maybe + * initializing banks together) rather than boot loaders; kexec() won't + * go through boot loaders. + * + * the gpio clock will be turned on when gpios are used, and you may also + * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are + * used as gpios, not with other peripherals. + * + * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe + * for later updates, code should write GPIO(N) or: + * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) + * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) + * + * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc + * for now, that's != GPIO(N) + */ +#define GPIO(X) (X) /* 0 <= X <= 70 */ +#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ +#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ + +struct gpio_controller { + u32 dir; + u32 out_data; + u32 set_data; + u32 clr_data; + u32 in_data; + u32 set_rising; + u32 clr_rising; + u32 set_falling; + u32 clr_falling; + u32 intstat; +}; + +/* The __gpio_to_controller() and __gpio_mask() functions inline to constants + * with constant parameters; or in outlined code they execute at runtime. + * + * You'd access the controller directly when reading or writing more than + * one gpio value at a time, and to support wired logic where the value + * being driven by the cpu need not match the value read back. + * + * These are NOT part of the cross-platform GPIO interface + */ +static inline struct gpio_controller *__iomem +__gpio_to_controller(unsigned gpio) +{ + void *__iomem ptr; + + if (gpio < 32) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); + else if (gpio < 64) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); + else if (gpio < DAVINCI_N_GPIO) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + else + ptr = NULL; + return ptr; +} + +static inline u32 __gpio_mask(unsigned gpio) +{ + return 1 << (gpio % 32); +} + +/* The get/set/clear functions will inline when called with constant + * parameters, for low-overhead bitbanging. Illegal constant parameters + * cause link-time errors. + * + * Otherwise, calls with variable parameters use outlined functions. + */ +extern int __error_inval_gpio(void); + +extern void __gpio_set(unsigned gpio, int value); +extern int __gpio_get(unsigned gpio); + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(value)) { + struct gpio_controller *__iomem g; + u32 mask; + + if (gpio >= DAVINCI_N_GPIO) + __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, &g->set_data); + else + __raw_writel(mask, &g->clr_data); + return; + } + + __gpio_set(gpio, value); +} + +/* Returns zero or nonzero; works for gpios configured as inputs OR + * as outputs. + * + * NOTE: changes in reported values are synchronized to the GPIO clock. + * This is most easily seen after calling gpio_set_value() and then immediatly + * gpio_get_value(), where the gpio_get_value() would return the old value + * until the GPIO clock ticks and the new value gets latched. + */ + +static inline int gpio_get_value(unsigned gpio) +{ + struct gpio_controller *__iomem g; + + if (!__builtin_constant_p(gpio)) + return __gpio_get(gpio); + + if (gpio >= DAVINCI_N_GPIO) + return __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); +} + +/* powerup default direction is IN */ +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); + +#include /* cansleep wrappers */ + +extern int gpio_request(unsigned gpio, const char *tag); +extern void gpio_free(unsigned gpio); + +static inline int gpio_to_irq(unsigned gpio) +{ + return DAVINCI_N_AINTC_IRQ + gpio; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - DAVINCI_N_AINTC_IRQ; +} + +#endif /* __DAVINCI_GPIO_H */ diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 60362d80229..a2e8969afac 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -11,4 +11,42 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) + #endif /* __ASM_ARCH_HARDWARE_H */ -- cgit v1.2.3 From 83f53220f8313f097cdf181928be13bafbb697ea Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 10 Jul 2007 13:10:04 +0100 Subject: [ARM] 4432/5: davinci: pin mux support Support pin multiplexing configurations driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov Acked-by: Kevin Hilman Signed-off-by: Russell King --- include/asm-arm/arch-davinci/mux.h | 55 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 include/asm-arm/arch-davinci/mux.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h new file mode 100644 index 00000000000..c24b6782804 --- /dev/null +++ b/include/asm-arm/arch-davinci/mux.h @@ -0,0 +1,55 @@ +/* + * DaVinci pin multiplexing defines + * + * Author: Vladimir Barinov, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +#define DAVINCI_MUX_AEAW0 0 +#define DAVINCI_MUX_AEAW1 1 +#define DAVINCI_MUX_AEAW2 2 +#define DAVINCI_MUX_AEAW3 3 +#define DAVINCI_MUX_AEAW4 4 +#define DAVINCI_MUX_AECS4 10 +#define DAVINCI_MUX_AECS5 11 +#define DAVINCI_MUX_VLYNQWD0 12 +#define DAVINCI_MUX_VLYNQWD1 13 +#define DAVINCI_MUX_VLSCREN 14 +#define DAVINCI_MUX_VLYNQEN 15 +#define DAVINCI_MUX_HDIREN 16 +#define DAVINCI_MUX_ATAEN 17 +#define DAVINCI_MUX_RGB666 22 +#define DAVINCI_MUX_RGB888 23 +#define DAVINCI_MUX_LOEEN 24 +#define DAVINCI_MUX_LFLDEN 25 +#define DAVINCI_MUX_CWEN 26 +#define DAVINCI_MUX_CFLDEN 27 +#define DAVINCI_MUX_HPIEN 29 +#define DAVINCI_MUX_1394EN 30 +#define DAVINCI_MUX_EMACEN 31 + +#define DAVINCI_MUX_LEVEL2 32 +#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) +#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) +#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) +#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) +#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) +#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) +#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) +#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) +#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) +#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) +#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) +#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) +#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) +#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) + +extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); + +#endif /* __ASM_ARCH_MUX_H */ -- cgit v1.2.3 From b54942f8203689014f80ec89c55ccb1f48ab1166 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 18 May 2007 06:28:01 +0100 Subject: [ARM] 4391/1: make at91 debug unit support optional The AT91x40 family doesn't have the debug unit like its bigger brothers. But it does have the ID and extension registers (with the bit meanings the same). Reorganize at91_dbgu.h to cater for this. This also affects the load uncompressor, since it outputs to the debug port. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_dbgu.h | 13 ++++++++++--- include/asm-arm/arch-at91/uncompress.h | 4 ++++ 2 files changed, 14 insertions(+), 3 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h index b0369e176f7..8019ffd0ad3 100644 --- a/include/asm-arm/arch-at91/at91_dbgu.h +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -16,6 +16,7 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H +#ifdef AT91_DBGU #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ @@ -30,6 +31,15 @@ #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ @@ -53,7 +63,4 @@ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - #endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 30ac587b3b4..272a7e0dc6c 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -33,20 +33,24 @@ */ static void putc(int c) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) barrier(); __raw_writel(c, sys + AT91_DBGU_THR); +#endif } static inline void flush(void) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ /* wait for transmission to complete */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) barrier(); +#endif } #define arch_decomp_setup() -- cgit v1.2.3 From 70672224009bc3d4d6713337b3456bc7ab71d52b Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 4 Jun 2007 06:45:38 +0100 Subject: [ARM] 4427/1: base Atmel at91x40 architecture defines Base at91x40 architecture support defines. These parts are somewhat simpler than the ARM9 Atmel based parts. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91x40.h | 55 +++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 5 ++++ include/asm-arm/arch-at91/timex.h | 5 ++++ 3 files changed, 65 insertions(+) create mode 100644 include/asm-arm/arch-at91/at91x40.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h new file mode 100644 index 00000000000..612203e0177 --- /dev/null +++ b/include/asm-arm/arch-at91/at91x40.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-at91/at91x40.h + * + * (C) Copyright 2007, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91X40_H +#define AT91X40_H + +/* + * IRQ list. + */ +#define AT91_ID_FIQ 0 /* FIQ */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91X40_ID_USART0 2 /* USART port 0 */ +#define AT91X40_ID_USART1 3 /* USART port 1 */ +#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ +#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ +#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ +#define AT91X40_ID_WD 7 /* Watchdog? */ +#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ + +#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ +#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ +#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_BASE_SYS 0xffc00000 + +#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ +#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ +#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ +#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ +#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ +#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ +#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ +#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ + +/* + * The AT91x40 series doesn't have a debug unit like the other AT91 parts. + * But it does have a chip identify register and extension ID, so define at + * least these here. + */ +#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ +#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ + +#endif /* AT91X40_H */ diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index ef93c30a9c5..080cbb401a8 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -28,6 +28,11 @@ #define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index 2df1ee12dfb..a310698fb4d 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -42,6 +42,11 @@ #define AT91SAM9_MASTER_CLOCK 100000000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91X40) + +#define AT91X40_MASTER_CLOCK 40000000 +#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) + #endif #endif -- cgit v1.2.3 From feb47225525a4194e7f6db5e745265793626ceb0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 4 Jun 2007 06:46:26 +0100 Subject: [ARM] 4428/1: modify at91 includes to handle non-MMU at91x40 family Modify the common at91 hardware support to deal with the non-MMU at91x40 family. The base RAM (which is most likely not DRAM) is set to the configured value. Virtual IO device mapping is set to be 1 to 1 with the physical addresses. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/hardware.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 46835e945ae..8f1cdd38a96 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -26,18 +26,29 @@ #include #elif defined(CONFIG_ARCH_AT91SAM9RL) #include +#elif defined(CONFIG_ARCH_AT91X40) +#include #else #error "Unsupported AT91 processor" #endif +#ifdef CONFIG_MMU /* * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#else +/* + * Identity mapping for the non MMU case. + */ +#define AT91_IO_PHYS_BASE AT91_BASE_SYS +#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#endif + +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) /* Convert a physical IO address to virtual IO address */ #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) @@ -66,7 +77,11 @@ #define AT91_CHIPSELECT_7 0x80000000 /* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -- cgit v1.2.3 From b3e6a508ed920698d367e5993ed056d70364d91f Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sat, 12 May 2007 14:31:17 +0100 Subject: [ARM] 4373/1: i.MX/MX1 GPIO support implementation Support for generic input output for MX1 family. The implementation prevents allocation of one pin by two users, but does not store pointer to the user description permanently, because this solution would have bigger memory overhead. The simple way to integrate code with per BSP pins setup and allocation is required else all GPIO registration checking is useless. The function imx_gpio_setup_multiple_pins() can be used for this purpose in future. Signed-off-by: Pavel Pisa Signed-off-by: Russell King --- include/asm-arm/arch-imx/gpio.h | 102 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-imx/imx-regs.h | 2 + 2 files changed, 104 insertions(+) create mode 100644 include/asm-arm/arch-imx/gpio.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h new file mode 100644 index 00000000000..486023263f3 --- /dev/null +++ b/include/asm-arm/arch-imx/gpio.h @@ -0,0 +1,102 @@ +#ifndef _IMX_GPIO_H + +#include + +#define IMX_GPIO_ALLOC_MODE_NORMAL 0 +#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 +#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 +#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 +#define IMX_GPIO_ALLOC_MODE_RELEASE 8 + +extern int imx_gpio_request(unsigned gpio, const char *label); + +extern void imx_gpio_free(unsigned gpio); + +extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label); + +extern int imx_gpio_direction_input(unsigned gpio); + +extern int imx_gpio_direction_output(unsigned gpio, int value); + +extern void __imx_gpio_set_value(unsigned gpio, int value); + +static inline int imx_gpio_get_value(unsigned gpio) +{ + return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); +} + +static inline void imx_gpio_set_value_inline(unsigned gpio, int value) +{ + unsigned long flags; + + raw_local_irq_save(flags); + if(value) + DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); + else + DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); + raw_local_irq_restore(flags); +} + +static inline void imx_gpio_set_value(unsigned gpio, int value) +{ + if(__builtin_constant_p(gpio)) + imx_gpio_set_value_inline(gpio, value); + else + __imx_gpio_set_value(gpio, value); +} + +extern int imx_gpio_to_irq(unsigned gpio); + +extern int imx_irq_to_gpio(unsigned irq); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions + * to allow future extension of GPIO logic. + */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return imx_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + imx_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return imx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return imx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return imx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); +} + +#include /* cansleep wrappers */ + +static inline int gpio_to_irq(unsigned gpio) +{ + return imx_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return imx_irq_to_gpio(irq); +} + + +#endif diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 30de404c61f..fb9de273387 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -77,6 +77,8 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define GPIO_PORT_MAX 3 + #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) -- cgit v1.2.3 From 4ad48b4bfa121a67ec04162d584afcfa75ed151a Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 16 May 2007 20:39:02 +0100 Subject: [ARM] 4385/2: ixdp425: NAND support IXDP425 NAND support (arch specific part). The generic platform driver that is used by ixdp425 platfrom is already in upstream kernel in 2.6.22-rc1. Signed-off-by: Vladimir Barinov Signed-off-by: Ruslan Sushko Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/ixdp425.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h index 3d3820d7ba0..e0791af3bfe 100644 --- a/include/asm-arm/arch-ixp4xx/ixdp425.h +++ b/include/asm-arm/arch-ixp4xx/ixdp425.h @@ -32,4 +32,8 @@ #define IXDP425_PCI_INTC_PIN 9 #define IXDP425_PCI_INTD_PIN 8 +/* NAND Flash pins */ +#define IXDP425_NAND_NCE_PIN 12 +#define IXDP425_NAND_CMD_BYTE 0x01 +#define IXDP425_NAND_ADDR_BYTE 0x02 -- cgit v1.2.3 From 46918bd13b887e8f0ae2987e690bc2af9c6c08a4 Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Sat, 2 Jun 2007 15:44:08 +0100 Subject: [ARM] 4425/2: Gateway 7001 series support This patch provides support for the Gateway 7001 AccessPoint series. Updated to stay below the 80 char limit in uncompress.h Signed-off-by: Imre Kaloz Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/uncompress.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index 09ae6c91be6..bf7a7882bf7 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -38,9 +38,10 @@ static void flush(void) static __inline__ void __arch_decomp_setup(unsigned long arch_id) { /* - * Coyote and gtwx5715 only have UART2 connected + * Some boards are using UART2 as console */ - if (machine_is_adi_coyote() || machine_is_gtwx5715()) + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; -- cgit v1.2.3 From dcdeeb21c010e9b5cb2e91f865cd5bebb65bc31f Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Sat, 2 Jun 2007 15:47:51 +0100 Subject: [ARM] 4426/2: Netgear WG302 v2 and WAG302 v2 support This patch provides support for the Netgear WG302 v2 and WAG302 v2 AccessPoint series. This patch relies on the patch "Gateway 7001 series support" minimally, as they only have UART2 connected. Updated to stay below the 80 char limit in uncompress.h Signed-off-by: Imre Kaloz Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/uncompress.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index bf7a7882bf7..f7a35b78823 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -41,7 +41,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) * Some boards are using UART2 as console */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || - machine_is_gateway7001()) + machine_is_gateway7001() || machine_is_wg302v2()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; -- cgit v1.2.3 From 8a87a996eae3d25b0670a243f4829ea4aa9eb63d Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Mon, 14 May 2007 14:30:15 +0100 Subject: [ARM] 4377/1: KS8695: GPIO driver Driver to control the GPIO pins on the KS8695 processor. The driver natively supports the Generic GPIO interface. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-ks8695/gpio.h | 79 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 include/asm-arm/arch-ks8695/gpio.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h new file mode 100644 index 00000000000..65ceea28607 --- /dev/null +++ b/include/asm-arm/arch-ks8695/gpio.h @@ -0,0 +1,79 @@ +/* + * include/asm-arm/arch-ks8695/gpio.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_GPIO_H_ +#define __ASM_ARCH_GPIO_H_ + +#define KS8695_GPIO_0 0 +#define KS8695_GPIO_1 1 +#define KS8695_GPIO_2 2 +#define KS8695_GPIO_3 3 +#define KS8695_GPIO_4 4 +#define KS8695_GPIO_5 5 +#define KS8695_GPIO_6 6 +#define KS8695_GPIO_7 7 +#define KS8695_GPIO_8 8 +#define KS8695_GPIO_9 9 +#define KS8695_GPIO_10 10 +#define KS8695_GPIO_11 11 +#define KS8695_GPIO_12 12 +#define KS8695_GPIO_13 13 +#define KS8695_GPIO_14 14 +#define KS8695_GPIO_15 15 + + +/* + * Configure GPIO pin as external interrupt source. + */ +int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); + +/* + * Configure the GPIO line as an input. + */ +int __init_or_module gpio_direction_input(unsigned int pin); + +/* + * Configure the GPIO line as an output, with default state. + */ +int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); + +/* + * Set the state of an output GPIO line. + */ +void gpio_set_value(unsigned int pin, unsigned int state); + +/* + * Read the state of a GPIO line. + */ +int gpio_get_value(unsigned int pin); + +/* + * Map GPIO line to IRQ number. + */ +int gpio_to_irq(unsigned int pin); + +/* + * Map IRQ number to GPIO line. + */ +int irq_to_gpio(unsigned int irq); + + +#include + +static inline int gpio_request(unsigned int pin, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int pin) +{ +} + +#endif -- cgit v1.2.3 From 909d6c6c80311f800aee338e5fa528818b115951 Mon Sep 17 00:00:00 2001 From: "George G. Davis" Date: Tue, 26 Jun 2007 01:38:27 +0100 Subject: [ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstone The ARM show_regs() tombstone only partially decodes which ARM ISA was executing at the time a fault occurred displaying either "(T)" for the Thumb case or nothing at all for other cases. This patch therefore explicitly identifies which state the processor is in at the time of a fault: ARM, Thumb, Jazelle or JazelleEE. Signed-off-by: George G. Davis Acked-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/ptrace.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index ee3d93c281d..ff038b65f37 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -103,6 +103,10 @@ struct pt_regs { #define thumb_mode(regs) (0) #endif +#define isa_mode(regs) \ + ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ + (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) + #define processor_mode(regs) \ ((regs)->ARM_cpsr & MODE_MASK) -- cgit v1.2.3 From f62c3f2c35874713ebbb6b6a4b9d9c6caaed4f14 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 15 May 2007 11:03:24 +0100 Subject: [ARM] pxa: remove useless pxa_pm_finish() function pxa_pm_finish() does nothing but return zero. The core code does nothing with this return value, and will not try to call the finish method in the pm_ops structure if it is NULL. Therefore, we can remove this useless function. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pm.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h index 7a8a1cdf430..52243a62c4e 100644 --- a/include/asm-arm/arch-pxa/pm.h +++ b/include/asm-arm/arch-pxa/pm.h @@ -9,4 +9,3 @@ extern int pxa_pm_prepare(suspend_state_t state); extern int pxa_pm_enter(suspend_state_t state); -extern int pxa_pm_finish(suspend_state_t state); -- cgit v1.2.3 From 7a2b94bc39915041304578188441f0f21aa5532a Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 16 May 2007 15:44:37 +0100 Subject: [ARM] pxa: remove MMC register defines from pxa-regs.h pxamci.h redefines the MMC registers differently so they can be used with ioremap. Remove the incompatible definitions from pxa-regs.h. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxa-regs.h | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index dbcc9298b0c..e68b593d69d 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1765,29 +1765,9 @@ #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) /* - * MultiMediaCard (MMC) controller + * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - - /* * Core Clock */ -- cgit v1.2.3 From b23170c01f6e4ea043df7cd9486c2488e01f3d60 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 15 May 2007 10:26:49 +0100 Subject: [ARM] pxa: introduce cpu_is_pxaXXX macros Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e2bdc2fbede..38612174641 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,42 @@ #ifndef __ASSEMBLY__ +#define __cpu_is_pxa21x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xf3f; \ + _id == 0x212; \ + }) + +#define __cpu_is_pxa25x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x2d0 || _id == 0x290; \ + }) + +#define __cpu_is_pxa27x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x411; \ + }) + +#define cpu_is_pxa21x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa21x(id); \ + }) + +#define cpu_is_pxa25x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa25x(id); \ + }) + +#define cpu_is_pxa27x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa27x(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ -- cgit v1.2.3 From 486c955118dbbb0f13dc4d40cc5dac2b23f82676 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 6 Jun 2007 06:22:20 +0100 Subject: [ARM] 4434/1: PXA: remove PXA_IRQ_SKIP 1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ starts from zero. This makes IRQ numbering inconsistent between PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX definition has the same value on both PXA25x and PXA27x. 2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this avoids unintentional use of these macros on PXA25x Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/entry-macro.S | 2 +- include/asm-arm/arch-pxa/irqs.h | 11 ++++------- 2 files changed, 5 insertions(+), 8 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S index 1d5fbb9b379..b7bf0dd4fa4 100644 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ b/include/asm-arm/arch-pxa/entry-macro.S @@ -34,6 +34,6 @@ rsb \irqstat, \irqnr, #0 and \irqstat, \irqstat, \irqnr clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP) + rsb \irqnr, \irqnr, #31 1001: .endm diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 67ed43674c6..dc4e7548b7d 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -11,14 +11,9 @@ */ -#ifdef CONFIG_PXA27x -#define PXA_IRQ_SKIP 0 -#else -#define PXA_IRQ_SKIP 7 -#endif - -#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) +#define PXA_IRQ(x) (x) +#ifdef CONFIG_PXA27x #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ @@ -26,6 +21,8 @@ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ +#endif + #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ -- cgit v1.2.3 From c08b7b3ef6bf489ddabadc03e050f3db2ea44b5d Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 6 Jun 2007 06:32:38 +0100 Subject: [ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQS 1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs, and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants 2. make the code specific to the high IRQ numbers (32..64) to be PXA27x specific 3. add a function pxa_init_irq_high() to initialize the internal high IRQ chip, the invoke of this function could be moved to PXA27x specific initialization code Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/irqs.h | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index dc4e7548b7d..a07fe0f928c 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -55,18 +55,15 @@ #ifdef CONFIG_PXA27x #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ - -#define PXA_INTERNAL_IRQS 34 -#else -#define PXA_INTERNAL_IRQS 32 #endif -#define GPIO_2_x_TO_IRQ(x) \ - PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) +#define PXA_GPIO_IRQ_BASE (64) +#define PXA_GPIO_IRQ_NUM (128) + +#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -#define IRQ_TO_GPIO_2_x(i) \ - ((i) - IRQ_GPIO(2) + 2) +#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) #if defined(CONFIG_PXA25x) @@ -81,7 +78,7 @@ * these. If you need more, increase IRQ_BOARD_END, but keep it * within sensible limits. */ -#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #define IRQ_SA1111_START (IRQ_BOARD_END) -- cgit v1.2.3 From 8118d124949ed8ff1a450e0c0d13cfab8c2ff7aa Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 6 Jun 2007 06:49:59 +0100 Subject: [ARM] 4440/1: PXA: enable the checking of ICIP2 for IRQs ICIP2 is not examined during IRQ entrance, this patch add the checking if the processor is PXA27x or later, with CoreG bits in CPUID (Core Generation) > 1 Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/entry-macro.S | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S index b7bf0dd4fa4..b7e73085146 100644 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ b/include/asm-arm/arch-pxa/entry-macro.S @@ -20,15 +20,33 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -#ifdef CONFIG_PXA27x - mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP - mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR -#else + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + mov \tmp, \tmp, lsr #13 + and \tmp, \tmp, #0x7 @ Core G + cmp \tmp, #1 + bhi 1004f + mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 add \base, \base, #0x00d00000 ldr \irqstat, [\base, #0] @ ICIP ldr \irqnr, [\base, #4] @ ICMR -#endif + b 1002f + +1004: + mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 + mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 + ands \irqstat, \irqstat, \irqnr + beq 1003f + rsb \irqstat, \irqnr, #0 + and \irqstat, \irqstat, \irqnr + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + add \irqnr, \irqnr, #32 + b 1001f +1003: + mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP + mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR +1002: ands \irqnr, \irqstat, \irqnr beq 1001f rsb \irqstat, \irqnr, #0 -- cgit v1.2.3 From f53f066c25036210036730d64c876ea586114425 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 22 Jun 2007 05:40:17 +0100 Subject: [ARM] 4451/1: pxa: make dma.c generic and remove cpu specific dma code Since the number of dma channels varies between pxa25x and pxa27x, it introduces some specific code in dma.c. This patch moves the specific code to pxa25x.c and pxa27x.c and makes dma.c more generic. 1. add pxa_init_dma() for dma initialization, the number of channels are passed in by the argument 2. add a "prio" field to the "struct pxa_dma_channel" for the channel priority, and is initialized in pxa_init_dma() 3. use a general priority comparison with the channels "prio" field so to remove the processor specific pxa_for_each_dma_prio macro, this is not lightning fast as the original one, but it is acceptable as it happens when requesting dma, which is usually not so performance critical Signed-off-by: eric miao Acked-by: Nicolas Pitre Signed-off-by: Russell King --- include/asm-arm/arch-pxa/dma.h | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index bed042d71d6..3280ee2ddfa 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -30,30 +30,12 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; -#if defined(CONFIG_PXA27x) - -#define PXA_DMA_CHANNELS 32 - -#define pxa_for_each_dma_prio(ch, prio) \ -for ( \ - ch = prio * 4; \ - ch != (4 << prio) + 16; \ - ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \ -) - -#elif defined(CONFIG_PXA25x) - -#define PXA_DMA_CHANNELS 16 - -#define pxa_for_each_dma_prio(ch, prio) \ - for (ch = prio * 4; ch != (4 << prio); ch++) - -#endif - /* * DMA registration */ +int __init pxa_init_dma(int num_ch); + int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), -- cgit v1.2.3 From f884b1cf578e079f01682514ae1ae64c74586602 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 12 Jul 2007 16:10:22 +0100 Subject: [ARM] 4473/2: Take the HWCAP definitions out of the elf.h file The patch moves the HWCAP definitions and the extern elf_hwcap declaration to the hwcap.h header file. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/Kbuild | 2 ++ include/asm-arm/elf.h | 23 +---------------------- include/asm-arm/hwcap.h | 28 ++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 22 deletions(-) create mode 100644 include/asm-arm/hwcap.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/Kbuild b/include/asm-arm/Kbuild index c68e1680da0..73237bd130a 100644 --- a/include/asm-arm/Kbuild +++ b/include/asm-arm/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +unifdef-y += hwcap.h diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index 3679a8a8922..d7a777f0508 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -7,6 +7,7 @@ */ #include #include +#include typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; @@ -39,30 +40,8 @@ typedef struct user_fp elf_fpregset_t; #endif #define ELF_ARCH EM_ARM -/* - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP - */ -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 -#define HWCAP_IWMMXT 512 -#define HWCAP_CRUNCH 1024 - #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) -extern unsigned int elf_hwcap; - /* * This yields a string that ld.so will use to load implementation * specific libraries for optimization. This is more specific in diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h new file mode 100644 index 00000000000..01a1391d301 --- /dev/null +++ b/include/asm-arm/hwcap.h @@ -0,0 +1,28 @@ +#ifndef __ASMARM_HWCAP_H +#define __ASMARM_HWCAP_H + +/* + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP + */ +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) +extern unsigned int elf_hwcap; +#endif + +#endif -- cgit v1.2.3 From d1cbbd6b413510c6512f4f80ffd48db1a8dd554a Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 11 Jul 2007 11:29:39 +0100 Subject: [ARM] 4474/1: Do not check the PSR_F_BIT in valid_user_regs When running Linux in non-secure mode (on ARM1176 for example), depending on the CP15 secure configuration register, the CPSR.F bit (6) might only be modified from the secure mode. However, the valid_user_regs() function checks for this bit being cleared. With commit a6c61e9d, a SIGSEGV is forced in handle_signal() if the user registers are not considered valid. The patch also ensures that the CPSR.A bit is cleared and the USR mode is set if the CPU does not support the 26bit user mode. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/ptrace.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index ff038b65f37..7aaa206cb54 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -10,6 +10,8 @@ #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H +#include + #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 @@ -45,6 +47,7 @@ #define PSR_T_BIT 0x00000020 #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 +#define PSR_A_BIT 0x00000100 #define PSR_J_BIT 0x01000000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 @@ -121,14 +124,17 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { - if (user_mode(regs) && - (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) + if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { + regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); return 1; + } /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; + regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; + if (!(elf_hwcap & HWCAP_26BIT)) + regs->ARM_cpsr |= USR_MODE; return 0; } -- cgit v1.2.3