From 5d1617b247aa63698618215a9f39ecf905d55779 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:03:26 +0800 Subject: [Blackfin] arch: merge ip0x-specific board changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf533/mem_init.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'include/asm-blackfin/mach-bf533') diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h index 1620dae5254..f8f31901fca 100644 --- a/include/asm-blackfin/mach-bf533/mem_init.h +++ b/include/asm-blackfin/mach-bf533/mem_init.h @@ -29,7 +29,8 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD) #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -118,6 +119,13 @@ #define SDRAM_CL CL_3 #endif +#if (CONFIG_MEM_MT48LC32M16A2TG_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + #if (CONFIG_MEM_GENERIC_BOARD) /*SDRAM INFORMATION: Modify this for your board */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ -- cgit v1.2.3