From 17099b1142f6c0359fca60a3464dea8fb30badea Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 14 Jul 2007 13:24:05 +0100 Subject: [MIPS] Make support for weakly ordered LL/SC a config option. None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-mips/bitops.h') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d9e81af53f7..148bc79557f 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -38,8 +38,8 @@ /* * clear_bit() doesn't provide any barrier for the compiler. */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#define smp_mb__before_clear_bit() smp_llsc_mb() +#define smp_mb__after_clear_bit() smp_llsc_mb() /* * set_bit - Atomically set a bit in memory @@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } -- cgit v1.2.3