From 8f40611d2b184ca5d525075d273854929cf8d1d0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 14 Jul 2005 07:34:18 +0000 Subject: Detect the MIPS R2 vectored interrupt, external interrupt controller options and the precense of the MT ASE. Signed-off-by: Ralf Baechle --- include/asm-mips/cpu-features.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include/asm-mips/cpu-features.h') diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index bb2212cf460..698c21125a5 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -109,6 +109,14 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif +#ifdef CONFIG_MIPS_MT +#ifndef cpu_has_mipsmt +# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) +#endif +#else +# define cpu_has_mipsmt 0 +#endif + #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) @@ -145,6 +153,22 @@ # endif #endif +#ifdef CONFIG_CPU_MIPSR2 +# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +# else +# define cpu_has_vint 0 +# endif +# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +# else +# define cpu_has_veic 0 +# endif +#else +# define cpu_has_vint 0 +# define cpu_has_veic 0 +#endif + #ifndef cpu_has_subset_pcaches #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) #endif -- cgit v1.2.3