From a36920200c5b89d56120a5e839fe4a603d51b16c Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 10 Jul 2007 17:33:02 +0100 Subject: [MIPS] Enable support for the userlocal hardware register Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-mips/cpu.h') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 2924069075e..49c1f001186 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -257,6 +257,7 @@ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ /* * CPU ASE encodings -- cgit v1.2.3 From 2a21c7300b53b744d16903256a172d9cbcfdd03e Mon Sep 17 00:00:00 2001 From: Fuxin Zhang Date: Wed, 6 Jun 2007 14:52:43 +0800 Subject: [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 Signed-off-by: Fuxin Zhang Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/asm-mips/cpu.h') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 49c1f001186..a3623954dad 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,8 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -211,7 +213,10 @@ #define CPU_SB1A 62 #define CPU_74K 63 #define CPU_R14000 64 -#define CPU_LAST 64 +#define CPU_LOONGSON1 65 +#define CPU_LOONGSON2 66 + +#define CPU_LAST 66 /* * ISA Level encodings -- cgit v1.2.3 From 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa Mon Sep 17 00:00:00 2001 From: Marc St-Jean Date: Thu, 14 Jun 2007 15:55:31 -0600 Subject: [MIPS] PMC MSP71xx mips common Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-mips/cpu.h') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index a3623954dad..3857358fb6d 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -109,6 +109,7 @@ * Definitions for 7:0 on legacy processors */ +#define PRID_REV_MASK 0x00ff #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 @@ -125,6 +126,7 @@ #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +#define PRID_REV_34K_V1_0_2 0x0022 /* * Older processors used to encode processor version and revision in two -- cgit v1.2.3