From 97dcb82de6cc99a5669eb8e342efc24cceb1e77e Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 8 Jan 2007 02:14:29 +0900 Subject: [MIPS] Define MIPS_CPU_IRQ_BASE in generic header The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/ddb5xxx/ddb5477.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/asm-mips/ddb5xxx') diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index c5af4b73fdd..27655dbd23f 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h @@ -17,6 +17,7 @@ #ifndef __ASM_DDB5XXX_DDB5477_H #define __ASM_DDB5XXX_DDB5477_H +#include /* * This contains macros that are specific to DDB5477 or renamed from @@ -257,8 +258,8 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); #define DDB_IRQ_BASE 0 #define I8259_IRQ_BASE DDB_IRQ_BASE -#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) -#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ) +#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE +#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) /* * vrc5477 irq defs -- cgit v1.2.3