From d6ad39bc53521275d14fde86bfb94d9b2ddb7a08 Mon Sep 17 00:00:00 2001 From: Jeremy Kerr Date: Thu, 20 Dec 2007 16:39:59 +0900 Subject: [POWERPC] spufs: rework class 0 and 1 interrupt handling Based on original patches from Arnd Bergmann ; and Luke Browning Currently, spu contexts need to be loaded to the SPU in order to take class 0 and class 1 exceptions. This change makes the actual interrupt-handlers much simpler (ie, set the exception information in the context save area), and defers the handling code to the spufs_handle_class[01] functions, called from spufs_run_spu. This should improve the concurrency of the spu scheduling leading to greater SPU utilization when SPUs are overcommited. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras --- include/asm-powerpc/spu_csa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-powerpc/spu_csa.h') diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h index 34da5c68517..0ab6bff8607 100644 --- a/include/asm-powerpc/spu_csa.h +++ b/include/asm-powerpc/spu_csa.h @@ -254,7 +254,7 @@ struct spu_state { u64 spu_chnldata_RW[32]; u32 spu_mailbox_data[4]; u32 pu_mailbox_data[1]; - u64 dar, dsisr; + u64 dar, dsisr, class_0_pending; unsigned long suspend_time; spinlock_t register_lock; }; -- cgit v1.2.3