From aa42c69c67f82e88f0726258efe7306708e1cf14 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 8 Dec 2006 02:43:30 -0600 Subject: [POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- include/asm-powerpc/cputable.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 6fe5c9d4ca3..aca72f90849 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) +#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) /* * Add the 64-bit processor unique features in the top half of the word; @@ -295,6 +296,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ CPU_FTR_COMMON) +#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ + CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) @@ -364,7 +368,8 @@ enum { CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | - CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 | + CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | + CPU_FTRS_CLASSIC32 | #else CPU_FTRS_GENERIC_32 | #endif @@ -403,7 +408,8 @@ enum { CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & - CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 & + CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & + CPU_FTRS_CLASSIC32 & #else CPU_FTRS_GENERIC_32 & #endif -- cgit v1.2.3 From 45d8e7aaf47668550fdb6c2d3abbe42f48a76df2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 10 Dec 2006 23:15:47 -0600 Subject: [POWERPC] Only export __mtdcr/__mfdcr if CONFIG_PPC_DCR is set On 85xx we don't build in dcr support because the core doesn't implement the instructions. This caused problems when building an 85xx kernel. Additionally made it so we only build __mtdcr/__mfdcr if we are CONFIG_PPC_DCR_NATIVE. The 85xx build issue wasPointed out by Dai Haruki. Signed-off-by: Kumar Gala --- include/asm-powerpc/dcr-native.h | 37 +++++++++++++++++++++++++++++++++++-- include/asm-powerpc/dcr.h | 2 ++ include/asm-ppc/reg_booke.h | 36 ++---------------------------------- 3 files changed, 39 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index fd4a5f5e33d..d7a1bc1551c 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h @@ -20,8 +20,7 @@ #ifndef _ASM_POWERPC_DCR_NATIVE_H #define _ASM_POWERPC_DCR_NATIVE_H #ifdef __KERNEL__ - -#include +#ifndef __ASSEMBLY__ typedef struct {} dcr_host_t; @@ -32,7 +31,41 @@ typedef struct {} dcr_host_t; #define dcr_read(host, dcr_n) mfdcr(dcr_n) #define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value) +/* Device Control Registers */ +void __mtdcr(int reg, unsigned int val); +unsigned int __mfdcr(int reg); +#define mfdcr(rn) \ + ({unsigned int rval; \ + if (__builtin_constant_p(rn)) \ + asm volatile("mfdcr %0," __stringify(rn) \ + : "=r" (rval)); \ + else \ + rval = __mfdcr(rn); \ + rval;}) + +#define mtdcr(rn, v) \ +do { \ + if (__builtin_constant_p(rn)) \ + asm volatile("mtdcr " __stringify(rn) ",%0" \ + : : "r" (v)); \ + else \ + __mtdcr(rn, v); \ +} while (0) + +/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ +#define mfdcri(base, reg) \ +({ \ + mtdcr(base ## _CFGADDR, base ## _ ## reg); \ + mfdcr(base ## _CFGDATA); \ +}) + +#define mtdcri(base, reg, data) \ +do { \ + mtdcr(base ## _CFGADDR, base ## _ ## reg); \ + mtdcr(base ## _CFGDATA, data); \ +} while (0) +#endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_NATIVE_H */ diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h index 473f2c7fd89..b66c5e6941f 100644 --- a/include/asm-powerpc/dcr.h +++ b/include/asm-powerpc/dcr.h @@ -20,6 +20,7 @@ #ifndef _ASM_POWERPC_DCR_H #define _ASM_POWERPC_DCR_H #ifdef __KERNEL__ +#ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR_NATIVE #include @@ -38,5 +39,6 @@ extern unsigned int dcr_resource_len(struct device_node *np, unsigned int index); #endif /* CONFIG_PPC_MERGE */ +#endif /* CONFIG_PPC_DCR */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_H */ diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index 602fbadeaf4..a263fc1e65c 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h @@ -9,41 +9,9 @@ #ifndef __ASM_PPC_REG_BOOKE_H__ #define __ASM_PPC_REG_BOOKE_H__ -#ifndef __ASSEMBLY__ -/* Device Control Registers */ -void __mtdcr(int reg, unsigned int val); -unsigned int __mfdcr(int reg); -#define mfdcr(rn) \ - ({unsigned int rval; \ - if (__builtin_constant_p(rn)) \ - asm volatile("mfdcr %0," __stringify(rn) \ - : "=r" (rval)); \ - else \ - rval = __mfdcr(rn); \ - rval;}) - -#define mtdcr(rn, v) \ -do { \ - if (__builtin_constant_p(rn)) \ - asm volatile("mtdcr " __stringify(rn) ",%0" \ - : : "r" (v)); \ - else \ - __mtdcr(rn, v); \ -} while (0) - -/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ -#define mfdcri(base, reg) \ -({ \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mfdcr(base ## _CFGDATA); \ -}) - -#define mtdcri(base, reg, data) \ -do { \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mtdcr(base ## _CFGDATA, data); \ -} while (0) +#include +#ifndef __ASSEMBLY__ /* Performance Monitor Registers */ #define mfpmr(rn) ({unsigned int rval; \ asm volatile("mfpmr %0," __stringify(rn) \ -- cgit v1.2.3 From d10f73480b991da2aa1c000ed38eda3e4a987292 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 10 Dec 2006 23:26:16 -0600 Subject: [PPC] Fix compile failure do to introduction of PHY_POLL PHY_POLL is defined in include it in so board code will have it defined. Signed-off-by: Kumar Gala --- include/linux/fsl_devices.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 3da29e2d524..abb64c437f6 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -19,6 +19,7 @@ #define _FSL_DEVICE_H_ #include +#include /* * Some conventions on how we handle peripherals on Freescale chips -- cgit v1.2.3