From 76d08bb3f09054edc45326ce5c698a3f6c45f5d0 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 5 Jun 2006 13:54:14 -0700 Subject: [IA64] Add "model name" to /proc/cpuinfo Linux ia64 port tried to decode the processor family number to something human-readable, but Intel brandnames don't change synchronously with updates to the family number. Adopt a more i386-like approach and just print the family number in decimal. Add a new field "model name" that uses PAL_BRAND_INFO to find the official name for the cpu, or on older systems, falls back to using the well-known codenames (Merced, McKinley, Madison). Signed-off-by: Tony Luck --- include/asm-ia64/pal.h | 10 ++++++++++ include/asm-ia64/processor.h | 1 + 2 files changed, 11 insertions(+) (limited to 'include') diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 37e52a2836b..312109d7be9 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -78,6 +78,7 @@ #define PAL_VM_TR_READ 261 /* read contents of translation register */ #define PAL_GET_PSTATE 262 /* get the current P-state */ #define PAL_SET_PSTATE 263 /* set the P-state */ +#define PAL_BRAND_INFO 274 /* Processor branding information */ #ifndef __ASSEMBLY__ @@ -1133,6 +1134,15 @@ ia64_pal_set_pstate (u64 pstate_index) return iprv.status; } +/* Processor branding information*/ +static inline s64 +ia64_pal_get_brand_info (char *brand_info) +{ + struct ia64_pal_retval iprv; + PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0); + return iprv.status; +} + /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are * suspended, but cache and TLB coherency is maintained. */ diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index b3bd58e8069..03100c4272c 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -164,6 +164,7 @@ struct cpuinfo_ia64 { __u8 family; __u8 archrev; char vendor[16]; + char *model_name; #ifdef CONFIG_NUMA struct ia64_node_data *node_data; -- cgit v1.2.3 From 2ab561a116e16cdee3ae0e13d51910634c15aee9 Mon Sep 17 00:00:00 2001 From: David Mosberger-Tang Date: Wed, 21 Jun 2006 11:19:22 -0700 Subject: [IA64] esi-support Add support for making ESI calls [1]. ESI stands for "Extensible SAL specification" and is basically a way for invoking firmware subroutines which are identified by a GUID. I don't know whether ESI is used by vendors other than HP (if you do, please let me know) but as firmware "backdoors" go, this seems one of the cleaner methods, so it seems reasonable to support it, even though I'm not aware of any publicly documented ESI calls. I'd have liked to make the ESI module completely stand-alone, but unfortunately that is not easily (or not at all) possible because in order to make ESI calls in physical mode, a small stub similar to the EFI stub is needed in the kernel proper. I did try to create a stub that would work in user-level, but it quickly got ugly beyond recognition (e.g., the stub had to make assumptions about how the module-loader generated call-stubs work) and I didn't even get it to work (that's probably fixable, but I didn't bother because I concluded it was too ugly anyhow). While it's not terribly elegant to have kernel code which isn't actively used in the kernel proper, I think it might be worth making an exception here for two reasons: the code is trivially small (all that's really needed is esi_stub.S) and by including it in the normal kernel distro, it might encourage other OEMs to also use ESI, which I think would be far better than each inventing their own firmware "backdoor". The code was originally written by Alex. I just massaged and packaged it a bit (and perhaps messed up some things along the way...). Changes since first version of patch that was posted to mailing list: * Export ia64_esi_call and ia64_esi_call_phys() as GPL symbols. * Disallow building esi.c as a module for now. Building as a module would currently lead to an unresolved reference to "sal_lock" on SMP kernels because that symbol doesn't get exported. * Export esi_call_phys() only if ESI is enabled. * Remove internal stuff from esi.h and add a "proc_type" argument to ia64_esi_call() such that serialization-requirements can be expressed (ESI follows SAL here, where procedure calls may have to be serialized, are MP-safe, or MP-safe andr reentrant). [1] h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,919,00.html Signed-off-by: David Mosberger Signed-off-by: Alex Williamson Signed-off-by: Tony Luck --- include/asm-ia64/esi.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/asm-ia64/esi.h (limited to 'include') diff --git a/include/asm-ia64/esi.h b/include/asm-ia64/esi.h new file mode 100644 index 00000000000..84aac0e0b58 --- /dev/null +++ b/include/asm-ia64/esi.h @@ -0,0 +1,30 @@ +/* + * ESI service calls. + * + * Copyright (c) Copyright 2005-2006 Hewlett-Packard Development Company, L.P. + * Alex Williamson + */ +#ifndef esi_h +#define esi_h + +#include + +#define ESI_QUERY 0x00000001 +#define ESI_OPEN_HANDLE 0x02000000 +#define ESI_CLOSE_HANDLE 0x02000001 + +enum esi_proc_type { + ESI_PROC_SERIALIZED, /* calls need to be serialized */ + ESI_PROC_MP_SAFE, /* MP-safe, but not reentrant */ + ESI_PROC_REENTRANT /* MP-safe and reentrant */ +}; + +extern int ia64_esi_init (void); +extern struct ia64_sal_retval esi_call_phys (void *, u64 *); +extern int ia64_esi_call(efi_guid_t, struct ia64_sal_retval *, + enum esi_proc_type, + u64, u64, u64, u64, u64, u64, u64, u64); +extern int ia64_esi_call_phys(efi_guid_t, struct ia64_sal_retval *, u64, u64, + u64, u64, u64, u64, u64, u64); + +#endif /* esi_h */ -- cgit v1.2.3 From 214ddde2f95037e129eff7e895869771719c7c1b Mon Sep 17 00:00:00 2001 From: bibo mao Date: Tue, 26 Sep 2006 11:20:37 -0700 Subject: [IA64] kprobe opcode 16 bytes alignment on IA64 On IA64 instruction opcode must be 16 bytes alignment, in kprobe structure there is one element to save original instruction, currently saved opcode is not statically allocated in kprobe structure, that can not assure 16 bytes alignment. This patch dynamically allocated kprobe instruction opcode to assure 16 bytes alignment. Signed-off-by: bibo mao Acked-by: Anil S Keshavamurthy Signed-off-by: Tony Luck --- include/asm-ia64/kprobes.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/kprobes.h b/include/asm-ia64/kprobes.h index 93890491011..1b45b71c79b 100644 --- a/include/asm-ia64/kprobes.h +++ b/include/asm-ia64/kprobes.h @@ -29,7 +29,8 @@ #include #include -#define MAX_INSN_SIZE 16 +#define __ARCH_WANT_KPROBES_INSN_SLOT +#define MAX_INSN_SIZE 1 #define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6) typedef union cmp_inst { @@ -94,7 +95,7 @@ struct kprobe_ctlblk { #define IP_RELATIVE_PREDICT_OPCODE (7) #define LONG_BRANCH_OPCODE (0xC) #define LONG_CALL_OPCODE (0xD) -#define arch_remove_kprobe(p) do {} while (0) +#define flush_insn_slot(p) do { } while (0) typedef struct kprobe_opcode { bundle_t bundle; @@ -108,7 +109,7 @@ struct fnptr { /* Architecture specific copy of original instruction*/ struct arch_specific_insn { /* copy of the instruction to be emulated */ - kprobe_opcode_t insn; + kprobe_opcode_t *insn; #define INST_FLAG_FIX_RELATIVE_IP_ADDR 1 #define INST_FLAG_FIX_BRANCH_REG 2 #define INST_FLAG_BREAK_INST 4 @@ -125,6 +126,6 @@ static inline void jprobe_return(void) } extern void invalidate_stacked_regs(void); extern void flush_register_stack(void); -extern void flush_insn_slot(struct kprobe *p); +extern void arch_remove_kprobe(struct kprobe *p); #endif /* _ASM_KPROBES_H */ -- cgit v1.2.3 From dd562c05410e13e878a3ee0deb8ac06db2e132c7 Mon Sep 17 00:00:00 2001 From: Stephane Eranian Date: Thu, 21 Sep 2006 10:35:44 -0700 Subject: [IA64] Add interface so modules can discover whether multithreading is on. Add is_multithreading_enabled() to check whether multi-threading is enabled independently of which cpu is currently online Signed-off-by: stephane eranian Signed-off-by: Tony Luck --- include/asm-ia64/smp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index 719ff309ce0..6533eb4e86a 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -128,6 +128,7 @@ extern void smp_send_reschedule (int cpu); extern void lock_ipi_calllock(void); extern void unlock_ipi_calllock(void); extern void identify_siblings (struct cpuinfo_ia64 *); +extern int is_multithreading_enabled(void); #else -- cgit v1.2.3 From 35589a8fa8138244e7f2ef9317c440aa580c9335 Mon Sep 17 00:00:00 2001 From: Keshavamurthy Anil S Date: Tue, 26 Sep 2006 12:03:13 -0700 Subject: [IA64] Move perfmon tables from thread_struct to pfm_context This patch renders thread_struct->pmcs[] and thread_struct->pmds[] OBSOLETE. The actual table is moved to pfm_context structure which saves space in thread_struct (in turn saving space in task_struct which frees up more space for kernel stacks). Signed-off-by: Stephane Eranian Signed-off-by: Anil S Keshavamurthy Signed-off-by: Tony Luck --- include/asm-ia64/processor.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index ead68f8eb88..5830d36fd8e 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -20,12 +20,6 @@ #include #define IA64_NUM_DBG_REGS 8 -/* - * Limits for PMC and PMD are set to less than maximum architected values - * but should be sufficient for a while - */ -#define IA64_NUM_PMC_REGS 64 -#define IA64_NUM_PMD_REGS 64 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) @@ -263,13 +257,9 @@ struct thread_struct { # define INIT_THREAD_IA32 #endif /* CONFIG_IA32_SUPPORT */ #ifdef CONFIG_PERFMON - __u64 pmcs[IA64_NUM_PMC_REGS]; - __u64 pmds[IA64_NUM_PMD_REGS]; void *pfm_context; /* pointer to detailed PMU context */ unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */ -# define INIT_THREAD_PM .pmcs = {0UL, }, \ - .pmds = {0UL, }, \ - .pfm_context = NULL, \ +# define INIT_THREAD_PM .pfm_context = NULL, \ .pfm_needs_checking = 0UL, #else # define INIT_THREAD_PM -- cgit v1.2.3 From a192dc16000241dc02990a36b6830839b73c44de Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 26 Sep 2006 14:00:56 -0700 Subject: [IA64] Implement futex primitives Implement futex_atomic_op_inuser() and futex_atomic_cmpxchg_inatomic() on IA64 in order to fully support all futex functionality. Signed-off-by: Jakub Jelinek Signed-off-by: David Woodhouse Signed-off-by: Tony Luck --- include/asm-ia64/futex.h | 122 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/futex.h b/include/asm-ia64/futex.h index 6a332a9f099..07d77f3a8cb 100644 --- a/include/asm-ia64/futex.h +++ b/include/asm-ia64/futex.h @@ -1,6 +1,124 @@ #ifndef _ASM_FUTEX_H #define _ASM_FUTEX_H -#include +#include +#include +#include +#include -#endif +#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \ +do { \ + register unsigned long r8 __asm ("r8") = 0; \ + __asm__ __volatile__( \ + " mf;; \n" \ + "[1:] " insn ";; \n" \ + " .xdata4 \"__ex_table\", 1b-., 2f-. \n" \ + "[2:]" \ + : "+r" (r8), "=r" (oldval) \ + : "r" (uaddr), "r" (oparg) \ + : "memory"); \ + ret = r8; \ +} while (0) + +#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \ +do { \ + register unsigned long r8 __asm ("r8") = 0; \ + int val, newval; \ + do { \ + __asm__ __volatile__( \ + " mf;; \n" \ + "[1:] ld4 %3=[%4];; \n" \ + " mov %2=%3 \n" \ + insn ";; \n" \ + " mov ar.ccv=%2;; \n" \ + "[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \ + " .xdata4 \"__ex_table\", 1b-., 3f-.\n" \ + " .xdata4 \"__ex_table\", 2b-., 3f-.\n" \ + "[3:]" \ + : "+r" (r8), "=r" (val), "=&r" (oldval), \ + "=&r" (newval) \ + : "r" (uaddr), "r" (oparg) \ + : "memory"); \ + if (unlikely (r8)) \ + break; \ + } while (unlikely (val != oldval)); \ + ret = r8; \ +} while (0) + +static inline int +futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +{ + int op = (encoded_op >> 28) & 7; + int cmp = (encoded_op >> 24) & 15; + int oparg = (encoded_op << 8) >> 20; + int cmparg = (encoded_op << 20) >> 20; + int oldval = 0, ret; + if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) + oparg = 1 << oparg; + + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + inc_preempt_count(); + + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr, + oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr, + ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg); + break; + default: + ret = -ENOSYS; + } + + dec_preempt_count(); + + if (!ret) { + switch (cmp) { + case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; + case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; + case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; + case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; + case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; + case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; + default: ret = -ENOSYS; + } + } + return ret; +} + +static inline int +futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +{ + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + { + register unsigned long r8 __asm ("r8"); + __asm__ __volatile__( + " mf;; \n" + " mov ar.ccv=%3;; \n" + "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n" + " .xdata4 \"__ex_table\", 1b-., 2f-. \n" + "[2:]" + : "=r" (r8) + : "r" (uaddr), "r" (newval), + "rO" ((long) (unsigned) oldval) + : "memory"); + return r8; + } +} + +#endif /* _ASM_FUTEX_H */ -- cgit v1.2.3 From 5c55cd63a77a85f603c98c2171a8054ca34b6a9f Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Tue, 26 Sep 2006 14:04:42 -0700 Subject: Revert "[IA64] Unwire set/get_robust_list" This reverts commit 2636255488484e04d6d54303d2b0ec30f7ef7e02. Jakub Jelinek provided the missing futex_atomic_cmpxchg_inatomic() function, so now it should be safe to re-enable these syscalls. Signed-off-by: Tony Luck --- include/asm-ia64/unistd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index f581662c5ab..bb0eb727dcd 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -286,7 +286,8 @@ /* 1294, 1295 reserved for pselect/ppoll */ #define __NR_unshare 1296 #define __NR_splice 1297 -/* 1298, 1299 reserved for set_robust_list/get_robust_list */ +#define __NR_set_robust_list 1298 +#define __NR_get_robust_list 1299 #define __NR_sync_file_range 1300 #define __NR_tee 1301 #define __NR_vmsplice 1302 -- cgit v1.2.3 From f5a3f3dc189485d607fbd42678cc23958acc0a6e Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 14 Sep 2006 08:25:15 +0800 Subject: [IA64] Make gp value point to Region 5 in mca handler MCA dispatch code take physical address of GP passed from SAL, then call DATA_PA_TO_VA twice on GP before call into C code. The first time is in ia64_set_kernel_register, the second time is in VIRTUAL_MODE_ENTER. The gp is changed to a virtual address in region 7 because DATA_PA_TO_VA is implemented by dep instruction. However when notify blocks were called from MCA handler code, because notify blocks are supported by callback function pointers, gp value value was switched to region 5 again. The patch set gp register to kernel gp of region 5 at entry of MCA dispatch. Signed-off-by: Zou Nan hai Signed-off-by: Tony Luck --- include/asm-ia64/mca_asm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h index 27c9203d8ce..76203f9a871 100644 --- a/include/asm-ia64/mca_asm.h +++ b/include/asm-ia64/mca_asm.h @@ -197,9 +197,9 @@ movl temp2 = start_addr; \ ;; \ mov cr.iip = temp2; \ + movl gp = __gp \ ;; \ DATA_PA_TO_VA(sp, temp1); \ - DATA_PA_TO_VA(gp, temp2); \ srlz.i; \ ;; \ nop 1; \ -- cgit v1.2.3 From b29e7132b5a9f2496beed37beef7ba4d010afb2c Mon Sep 17 00:00:00 2001 From: Russ Anderson Date: Tue, 26 Sep 2006 14:47:48 -0500 Subject: [IA64] PAL calls need physical mode, stacked PAL_CACHE_READ and PAL_CACHE_WRITE need to be called in physical mode with stacked registers. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck --- include/asm-ia64/pal.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index d1587e4f575..2c8fd92d0ec 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -964,7 +964,8 @@ static inline s64 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) { struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0); + PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data, + physical_addr, 0); return iprv.status; } @@ -986,7 +987,8 @@ static inline s64 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) { struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data); + PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data, + physical_addr, data); return iprv.status; } -- cgit v1.2.3