From e7bd34a15b85655f24d1b45edbe3bdfebf9d027e Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Tue, 31 Jul 2007 17:07:28 +0900
Subject: sh: Support explicit L1 cache disabling.

This reworks the cache mode configuration in Kconfig, and allows for
explicit selection of write-back/write-through/off configurations.
All of the cache flushing routines are optimized away for the off
case.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cacheflush.h | 33 ++++++++++++++++++++++++++++++++-
 include/asm-sh/page.h       |  6 +++---
 include/asm-sh/pgtable.h    |  3 ++-
 3 files changed, 37 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
index 07f62ec9ff0..aa558da0847 100644
--- a/include/asm-sh/cacheflush.h
+++ b/include/asm-sh/cacheflush.h
@@ -1,16 +1,47 @@
 #ifndef __ASM_SH_CACHEFLUSH_H
 #define __ASM_SH_CACHEFLUSH_H
+
 #ifdef __KERNEL__
 
-#include <linux/mm.h>
+#ifdef CONFIG_CACHE_OFF
+/*
+ * Nothing to do when the cache is disabled, initial flush and explicit
+ * disabling is handled at CPU init time.
+ *
+ * See arch/sh/kernel/cpu/init.c:cache_init().
+ */
+#define p3_cache_init()				do { } while (0)
+#define flush_cache_all()			do { } while (0)
+#define flush_cache_mm(mm)			do { } while (0)
+#define flush_cache_dup_mm(mm)			do { } while (0)
+#define flush_cache_range(vma, start, end)	do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
+#define flush_dcache_page(page)			do { } while (0)
+#define flush_icache_range(start, end)		do { } while (0)
+#define flush_icache_page(vma,pg)		do { } while (0)
+#define flush_dcache_mmap_lock(mapping)		do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
+#define flush_cache_sigtramp(vaddr)		do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)
+#define __flush_wback_region(start, size)	do { (void)(start); } while (0)
+#define __flush_purge_region(start, size)	do { (void)(start); } while (0)
+#define __flush_invalidate_region(start, size)	do { (void)(start); } while (0)
+#else
 #include <asm/cpu/cacheflush.h>
 
+/*
+ * Consistent DMA requires that the __flush_xxx() primitives must be set
+ * for any of the enabled non-coherent caches (most of the UP CPUs),
+ * regardless of PIPT or VIPT cache configurations.
+ */
+
 /* Flush (write-back only) a region (smaller than a page) */
 extern void __flush_wback_region(void *start, int size);
 /* Flush (write-back & invalidate) a region (smaller than a page) */
 extern void __flush_purge_region(void *start, int size);
 /* Flush (invalidate only) a region (smaller than a page) */
 extern void __flush_invalidate_region(void *start, int size);
+#endif
 
 #define flush_cache_vmap(start, end)		flush_cache_all()
 #define flush_cache_vunmap(start, end)		flush_cache_all()
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 6bc9bba1010..48b718e7455 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -70,14 +70,14 @@ extern void clear_page_nommu(void *to);
 extern void copy_page_nommu(void *to, void *from);
 #endif
 
-#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
-	defined(CONFIG_SH7705_CACHE_32KB))
+#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
+	(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
 struct page;
 extern void clear_user_page(void *to, unsigned long address, struct page *pg);
 extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg);
 extern void __clear_user_page(void *to, void *orig_to);
 extern void __copy_user_page(void *to, void *from, void *orig_to);
-#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU)
+#else
 #define clear_user_page(page, vaddr, pg)	clear_page(page)
 #define copy_user_page(to, from, vaddr, pg)	copy_page(to, from)
 #endif
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index e3fae12c0e4..54ad5037fe4 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -563,7 +563,8 @@ struct mm_struct;
 extern unsigned int kobjsize(const void *objp);
 #endif /* !CONFIG_MMU */
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
+#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
+	defined(CONFIG_SH7705_CACHE_32KB))
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 #endif
-- 
cgit v1.2.3


From a0e23267d4c57cdaa88114c3d88e25c87ee32d84 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Tue, 31 Jul 2007 17:11:21 +0900
Subject: sh: intc - add support for SH7785

This patch converts the cpu specific interrupt setup code for sh7785
from intc2 to intc. New vectors are also added to match the information
provided by the datasheet.

No IRQ/IRL pin vectors are enabled by default. Use plat_irq_setup_pins()
to select between IRL and IRQ mode.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 20d42959f52..921ddec6ccf 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -115,7 +115,8 @@ void __init register_intc_controller(struct intc_desc *desc);
 
 void __init plat_irq_setup(void);
 
-enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
+       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
 void __init plat_irq_setup_pins(int mode);
 
 #endif /* __ASM_SH_HW_IRQ_H */
-- 
cgit v1.2.3


From ad89f87a84040a57c4a78ca2759b364f72f423ab Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Fri, 3 Aug 2007 14:19:58 +0900
Subject: rtc: rtc-sh: Support 4-digit year on SH7705/SH7710/SH7712.

All SH-4 parts have a 4-digit year, while the SH-3 parts typically
only use a 2-digit one. The SH7705, SH7710, and SH7712 SH-3 parts
however opted to extend it to 4-digit and still look and act like
an SH-3 RTC in all other ways.

This adds a capability flag (RTC_CAP_4_DIGIT_YEAR) that these
corner-case CPU subtypes can set in their platform data and cleans
up some of the ifdef mess in the driver as a result.

Reported-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/rtc.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'include')

diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h
index 91aacc96151..858da99d37e 100644
--- a/include/asm-sh/rtc.h
+++ b/include/asm-sh/rtc.h
@@ -5,4 +5,10 @@ extern void (*board_time_init)(void);
 extern void (*rtc_sh_get_time)(struct timespec *);
 extern int (*rtc_sh_set_time)(const time_t);
 
+#define RTC_CAP_4_DIGIT_YEAR	(1 << 0)
+
+struct sh_rtc_platform_info {
+	unsigned long capabilities;
+};
+
 #endif /* _ASM_RTC_H */
-- 
cgit v1.2.3


From d59645d6ba67337ff09369d9da4fc47f7dc361cc Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 3 Aug 2007 14:23:35 +0900
Subject: sh: intc - remove redundant irq code for sh03, snapgear and titan

This patch removes redundant board specific interrupt code for boards
using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode"
aka IRLM.

Three boards are affected: sh03, snapgear and titan.

The right way to do this is to use cpu specific code provided by intc.
A nice side effect is that sh03 now compiles, board not BROKEN any more.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h   |  5 -----
 include/asm-sh/sh03/io.h  |  9 ---------
 include/asm-sh/snapgear.h | 12 ++++--------
 3 files changed, 4 insertions(+), 22 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 921ddec6ccf..8f5bf98d053 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -41,11 +41,6 @@ struct ipr_desc {
 
 void register_ipr_controller(struct ipr_desc *);
 
-/*
- * Enable individual interrupt mode for external IPR IRQs.
- */
-void __init ipr_irq_enable_irlm(void);
-
 typedef unsigned char intc_enum;
 
 struct intc_vect {
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index 4ff1eb90030..c39c785bba9 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -11,22 +11,13 @@
 
 #include <linux/time.h>
 
-#define INTC_IPRD	0xffd00010UL
-
 #define IRL0_IRQ	2
-#define IRL0_IPR_POS	3
 #define IRL0_PRIORITY	13
-
 #define IRL1_IRQ	5
-#define IRL1_IPR_POS	2
 #define IRL1_PRIORITY	10
-
 #define IRL2_IRQ	8
-#define IRL2_IPR_POS	1
 #define IRL2_PRIORITY	7
-
 #define IRL3_IRQ	11
-#define IRL3_IPR_POS	0
 #define IRL3_PRIORITY	4
 
 void heartbeat_sh03(void);
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 3554e3a74e9..042d95f51c4 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -19,20 +19,16 @@
  * is the interrupt :-)
  */
 
-#define IRL0_IRQ		2
-#define IRL0_IPR_POS	3
+#define IRL0_IRQ	2
 #define IRL0_PRIORITY	13
 
-#define IRL1_IRQ		5
-#define IRL1_IPR_POS	2
+#define IRL1_IRQ	5
 #define IRL1_PRIORITY	10
 
-#define IRL2_IRQ		8
-#define IRL2_IPR_POS	1
+#define IRL2_IRQ	8
 #define IRL2_PRIORITY	7
 
-#define IRL3_IRQ		11
-#define IRL3_IPR_POS	0
+#define IRL3_IRQ	11
 #define IRL3_PRIORITY	4
 #endif
 
-- 
cgit v1.2.3


From 51da64264b8d59a1e5fceebd94a975690b70b086 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 3 Aug 2007 14:25:32 +0900
Subject: sh: intc - add single bitmap register support

This patch adds single bitmap register support to intc. The current
code only handles 16 and 32 bit registers where a set bit means
interrupt enabled, but this is easy to extend in the future.

The INTC_IRQ() macro is also added to provide a way to hook in
interrupt controllers for FPGAs in boards or companion chips.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 8f5bf98d053..9f55c2dc1b5 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -49,6 +49,7 @@ struct intc_vect {
 };
 
 #define INTC_VECT(enum_id, vect) { enum_id, vect }
+#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
 
 struct intc_prio {
 	intc_enum enum_id;
-- 
cgit v1.2.3


From 48180cab3adf4cb290c28b70e44e958b7fb8a5b0 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 3 Aug 2007 14:27:20 +0900
Subject: sh: intc - convert voyagergx code

This patch converts the sh-specific voyagergx interrupt code to make use
of intc. A lot of "interesting" old cruft gets replaced with intc tables
and some simple demux code.

- All interrupt sources in the sm501 data sheet are now in the header.
- The number and order of IRQ values are disconnected from register bits.
- Interrupt sources now start from IRQ 200.
- set_irq_chained_handler() is now used to hook up the demux function.

In the future it would probably make sense to move the interrupt demuxer
into into the mfd driver, but this is probably a nice step in the right
direction until that happens.

Tested on a R2D-1 board using the serial port hooked up to the sm501.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/voyagergx.h | 39 ++++++++++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/voyagergx.h b/include/asm-sh/voyagergx.h
index 64c936b2271..d825596562d 100644
--- a/include/asm-sh/voyagergx.h
+++ b/include/asm-sh/voyagergx.h
@@ -27,13 +27,35 @@
 #define VOYAGER_UART_BASE		(0x30000 + VOYAGER_BASE)
 #define	VOYAGER_AC97_BASE		(0xa0000 + VOYAGER_BASE)
 
-#define VOYAGER_IRQ_NUM			32
-#define VOYAGER_IRQ_BASE		50
-#define VOYAGER_USBH_IRQ		VOYAGER_IRQ_BASE + 6
-#define VOYAGER_8051_IRQ		VOYAGER_IRQ_BASE + 10
-#define VOYAGER_UART0_IRQ		VOYAGER_IRQ_BASE + 12
-#define VOYAGER_UART1_IRQ		VOYAGER_IRQ_BASE + 13
-#define	VOYAGER_AC97_IRQ		VOYAGER_IRQ_BASE + 17
+#define VOYAGER_IRQ_NUM			26
+#define VOYAGER_IRQ_BASE		200
+
+#define IRQ_SM501_UP			(VOYAGER_IRQ_BASE + 0)
+#define IRQ_SM501_G54			(VOYAGER_IRQ_BASE + 1)
+#define IRQ_SM501_G53			(VOYAGER_IRQ_BASE + 2)
+#define IRQ_SM501_G52			(VOYAGER_IRQ_BASE + 3)
+#define IRQ_SM501_G51			(VOYAGER_IRQ_BASE + 4)
+#define IRQ_SM501_G50			(VOYAGER_IRQ_BASE + 5)
+#define IRQ_SM501_G49			(VOYAGER_IRQ_BASE + 6)
+#define IRQ_SM501_G48			(VOYAGER_IRQ_BASE + 7)
+#define IRQ_SM501_I2C			(VOYAGER_IRQ_BASE + 8)
+#define IRQ_SM501_PW			(VOYAGER_IRQ_BASE + 9)
+#define IRQ_SM501_DMA			(VOYAGER_IRQ_BASE + 10)
+#define IRQ_SM501_PCI			(VOYAGER_IRQ_BASE + 11)
+#define IRQ_SM501_I2S			(VOYAGER_IRQ_BASE + 12)
+#define IRQ_SM501_AC			(VOYAGER_IRQ_BASE + 13)
+#define IRQ_SM501_US			(VOYAGER_IRQ_BASE + 14)
+#define IRQ_SM501_U1			(VOYAGER_IRQ_BASE + 15)
+#define IRQ_SM501_U0			(VOYAGER_IRQ_BASE + 16)
+#define IRQ_SM501_CV			(VOYAGER_IRQ_BASE + 17)
+#define IRQ_SM501_MC			(VOYAGER_IRQ_BASE + 18)
+#define IRQ_SM501_S1			(VOYAGER_IRQ_BASE + 19)
+#define IRQ_SM501_S0			(VOYAGER_IRQ_BASE + 20)
+#define IRQ_SM501_UH			(VOYAGER_IRQ_BASE + 21)
+#define IRQ_SM501_2D			(VOYAGER_IRQ_BASE + 22)
+#define IRQ_SM501_ZD			(VOYAGER_IRQ_BASE + 23)
+#define IRQ_SM501_PV			(VOYAGER_IRQ_BASE + 24)
+#define IRQ_SM501_CI			(VOYAGER_IRQ_BASE + 25)
 
 /* ----- MISC controle  register ------------------------------ */
 #define MISC_CTRL			(0x000004 + VOYAGER_BASE)
@@ -313,4 +335,7 @@
 void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t);
 int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t);
 
+/* arch/sh/cchips/voyagergx/irq.c */
+void setup_voyagergx_irq(void);
+
 #endif /* _VOYAGER_GX_REG_H */
-- 
cgit v1.2.3


From 96290d808fa4c9b8e744dc1cd032b005179f4710 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 3 Aug 2007 14:29:20 +0900
Subject: sh: remove intc2 code

There is no point in keeping around the now unused intc2 code.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 18 ------------------
 1 file changed, 18 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 9f55c2dc1b5..a4086ea313c 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -6,24 +6,6 @@
 
 extern atomic_t irq_err_count;
 
-struct intc2_data {
-	unsigned short irq;
-	unsigned char ipr_offset, ipr_shift;
-	unsigned char msk_offset, msk_shift;
-	unsigned char priority;
-};
-
-struct intc2_desc {
-	unsigned long prio_base;
-	unsigned long msk_base;
-	unsigned long mskclr_base;
-	struct intc2_data *intc2_data;
-	unsigned int nr_irqs;
-	struct irq_chip chip;
-};
-
-void register_intc2_controller(struct intc2_desc *);
-
 struct ipr_data {
 	unsigned char irq;
 	unsigned char ipr_idx;		/* Index for the IPR registered */
-- 
cgit v1.2.3


From fef96086270e8d3c99fb2bfc72eef94d95ab2240 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 8 Aug 2007 15:26:51 +0900
Subject: sh: x3proto: ILSEL IRQ support.

This adds functionality for the on-board ILSEL IRQs that chain
IRL mode events. Many on-board devices (ethernet, usb, etc.) rely
on ILSEL IRQs directly.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/ilsel.h | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 include/asm-sh/ilsel.h

(limited to 'include')

diff --git a/include/asm-sh/ilsel.h b/include/asm-sh/ilsel.h
new file mode 100644
index 00000000000..e3d304b280f
--- /dev/null
+++ b/include/asm-sh/ilsel.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_SH_ILSEL_H
+#define __ASM_SH_ILSEL_H
+
+typedef enum {
+	ILSEL_NONE,
+	ILSEL_LAN,
+	ILSEL_USBH_I,
+	ILSEL_USBH_S,
+	ILSEL_USBH_V,
+	ILSEL_RTC,
+	ILSEL_USBP_I,
+	ILSEL_USBP_S,
+	ILSEL_USBP_V,
+	ILSEL_KEY,
+
+	/*
+	 * ILSEL Aliases - corner cases for interleaved level tables.
+	 *
+	 * Someone thought this was a good idea and less hassle than
+	 * demuxing a shared vector, really.
+	 */
+
+	/* ILSEL0 and 2 */
+	ILSEL_FPGA0,
+	ILSEL_FPGA1,
+	ILSEL_EX1,
+	ILSEL_EX2,
+	ILSEL_EX3,
+	ILSEL_EX4,
+
+	/* ILSEL1 and 3 */
+	ILSEL_FPGA2 = ILSEL_FPGA0,
+	ILSEL_FPGA3 = ILSEL_FPGA1,
+	ILSEL_EX5 = ILSEL_EX1,
+	ILSEL_EX6 = ILSEL_EX2,
+	ILSEL_EX7 = ILSEL_EX3,
+	ILSEL_EX8 = ILSEL_EX4,
+} ilsel_source_t;
+
+/* arch/sh/boards/renesas/x3proto/ilsel.c */
+int ilsel_enable(ilsel_source_t set);
+int ilsel_enable_fixed(ilsel_source_t set, unsigned int level);
+void ilsel_disable(unsigned int irq);
+
+#endif /* __ASM_SH_ILSEL_H */
-- 
cgit v1.2.3


From dfc5ed2a939baf08f9385a8c6249b719cac63665 Mon Sep 17 00:00:00 2001
From: Markus Brunner <super.firetwister@gmail.com>
Date: Mon, 20 Aug 2007 08:58:12 +0900
Subject: sh: Add gpio.h stubs for PFC definitions.

This adds the PFC definitions for SH-3, as well as consolidating the
gpio.h mess within sh-sci. Stub in sh64, as it's the odd one out
between the sh-sci architectures (sh, sh64, h8300) in this capacity.

Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cpu-sh3/gpio.h | 66 +++++++++++++++++++++++++++++++++++++++++++
 include/asm-sh/gpio.h         | 19 +++++++++++++
 include/asm-sh64/gpio.h       |  8 ++++++
 3 files changed, 93 insertions(+)
 create mode 100644 include/asm-sh/cpu-sh3/gpio.h
 create mode 100644 include/asm-sh/gpio.h
 create mode 100644 include/asm-sh64/gpio.h

(limited to 'include')

diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
new file mode 100644
index 00000000000..48770c1c7bd
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/gpio.h
@@ -0,0 +1,66 @@
+/*
+ *  include/asm-sh/cpu-sh3/gpio.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _CPU_SH3_GPIO_H
+#define _CPU_SH3_GPIO_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+
+/* Control registers */
+#define PORT_PACR	0xA4050100UL
+#define PORT_PBCR	0xA4050102UL
+#define PORT_PCCR	0xA4050104UL
+#define PORT_PDCR	0xA4050106UL
+#define PORT_PECR	0xA4050108UL
+#define PORT_PFCR	0xA405010AUL
+#define PORT_PGCR	0xA405010CUL
+#define PORT_PHCR	0xA405010EUL
+#define PORT_PJCR	0xA4050110UL
+#define PORT_PKCR	0xA4050112UL
+#define PORT_PLCR	0xA4050114UL
+#define PORT_PMCR	0xA4050116UL
+#define PORT_PPCR	0xA4050118UL
+#define PORT_PRCR	0xA405011AUL
+#define PORT_PSCR	0xA405011CUL
+#define PORT_PTCR	0xA405011EUL
+#define PORT_PUCR	0xA4050120UL
+#define PORT_PVCR	0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR	0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR	0xA4050142UL
+#define PORT_PCDR	0xA4050144UL
+#define PORT_PDDR	0xA4050146UL
+#define PORT_PEDR	0xA4050148UL
+#define PORT_PFDR	0xA405014AUL
+#define PORT_PGDR	0xA405014CUL
+#define PORT_PHDR	0xA405014EUL
+#define PORT_PJDR	0xA4050150UL
+#define PORT_PKDR	0xA4050152UL
+#define PORT_PLDR	0xA4050154UL
+#define PORT_PMDR	0xA4050156UL
+#define PORT_PPDR	0xA4050158UL
+#define PORT_PRDR	0xA405015AUL
+#define PORT_PSDR	0xA405015CUL
+#define PORT_PTDR	0xA405015EUL
+#define PORT_PUDR	0xA4050160UL
+#define PORT_PVDR	0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA	0xA4050124UL
+#define PORT_PSELB	0xA4050126UL
+#define PORT_PSELC	0xA4050128UL
+#define PORT_PSELD	0xA405012AUL
+
+#endif
+
+#endif
diff --git a/include/asm-sh/gpio.h b/include/asm-sh/gpio.h
new file mode 100644
index 00000000000..9bb27e0f11a
--- /dev/null
+++ b/include/asm-sh/gpio.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-sh/gpio.h
+ *
+ *  Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_GPIO_H
+#define __ASM_SH_GPIO_H
+
+#if defined(CONFIG_CPU_SH3)
+#include <asm/cpu/gpio.h>
+#endif
+
+#endif /* __ASM_SH_GPIO_H */
diff --git a/include/asm-sh64/gpio.h b/include/asm-sh64/gpio.h
new file mode 100644
index 00000000000..6bc5a13d841
--- /dev/null
+++ b/include/asm-sh64/gpio.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH64_GPIO_H
+#define __ASM_SH64_GPIO_H
+
+/*
+ * This is just a stub, so that every arch using sh-sci has a gpio.h
+ */
+
+#endif /* __ASM_SH64_GPIO_H */
-- 
cgit v1.2.3


From 3ea6bc3de4f15fcae84fb31eeea4d420685a3da2 Mon Sep 17 00:00:00 2001
From: Markus Brunner <super.firetwister@gmail.com>
Date: Mon, 20 Aug 2007 08:59:33 +0900
Subject: sh: Add SH7720 CPU support.

This adds support for the SH7720 (SH3-DSP) CPU.

Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cpu-sh3/cache.h       |  4 +++-
 include/asm-sh/cpu-sh3/dma.h         | 13 +++++++++++++
 include/asm-sh/cpu-sh3/mmu_context.h |  9 +++++----
 include/asm-sh/cpu-sh3/timer.h       |  9 ++++++---
 include/asm-sh/cpu-sh3/ubc.h         |  3 ++-
 include/asm-sh/processor.h           |  2 +-
 6 files changed, 30 insertions(+), 10 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index ffe08d2813f..255016fc91f 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -26,7 +26,9 @@
 #define CCR_CACHE_ENABLE	CCR_CACHE_CE
 #define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720)
 #define CCR3	0xa40000b4
 #define CCR_CACHE_16KB  0x00010000
 #define CCR_CACHE_32KB	0x00020000
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 3a66dc45802..e56203086eb 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -1,7 +1,20 @@
 #ifndef __ASM_CPU_SH3_DMA_H
 #define __ASM_CPU_SH3_DMA_H
 
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#define SH_DMAC_BASE	0xa4010020
+
+#define DMTE0_IRQ	48
+#define DMTE1_IRQ	49
+#define DMTE2_IRQ	50
+#define DMTE3_IRQ	51
+#define DMTE4_IRQ	76
+#define DMTE5_IRQ	77
+
+#else
 #define SH_DMAC_BASE	0xa4000020
+#endif
 
 /* Definitions for the SuperH DMAC */
 #define TM_BURST	0x00000020
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index b20786d42d0..16c2d63b7e3 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -27,12 +27,13 @@
 #define TRA	0xffffffd0
 #define EXPEVT	0xffffffd4
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
     defined(CONFIG_CPU_SUBTYPE_SH7712) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7710)
+    defined(CONFIG_CPU_SUBTYPE_SH7720)
 #define INTEVT	0xa4000000	/* INTEVTE2(0xa4000000) */
 #else
 #define INTEVT	0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index b6c2020a2ad..3880ce047fe 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -23,11 +23,13 @@
  * ---------------------------------------------------------------------------
  */
 
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+     !defined(CONFIG_CPU_SUBTYPE_SH7727)
 #define TMU_TOCR	0xfffffe90	/* Byte access */
 #endif
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720)
 #define TMU_012_TSTR	0xa412fe92	/* Byte access */
 
 #define TMU0_TCOR	0xa412fe94	/* Long access */
@@ -56,7 +58,8 @@
 #define TMU2_TCOR	0xfffffeac	/* Long access */
 #define TMU2_TCNT	0xfffffeb0	/* Long access */
 #define TMU2_TCR	0xfffffeb4	/* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+    !defined(CONFIG_CPU_SUBTYPE_SH7727)
 #define TMU2_TCPR2	0xfffffeb8	/* Long access */
 #endif
 #endif
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 9d308cbe9b2..18467c57453 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,7 +11,8 @@
 #ifndef __ASM_CPU_SH3_UBC_H
 #define __ASM_CPU_SH3_UBC_H
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720)
 #define UBC_BARA		0xa4ffffb0
 #define UBC_BAMRA		0xa4ffffb4
 #define UBC_BBRA		0xa4ffffb8
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 26d52174f4b..56cb3c89f84 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -45,7 +45,7 @@ enum cpu_type {
 	CPU_SH7705, CPU_SH7706, CPU_SH7707,
 	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
 	CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
-	CPU_SH7729,
+	CPU_SH7720, CPU_SH7729,
 
 	/* SH-4 types */
 	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
-- 
cgit v1.2.3


From 6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Sun, 12 Aug 2007 15:22:02 +0900
Subject: sh: intc - add a clear register to struct intc_prio_reg

We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index a4086ea313c..6c759b2b892 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -53,7 +53,7 @@ struct intc_mask_reg {
 };
 
 struct intc_prio_reg {
-	unsigned long reg, reg_width, field_width;
+	unsigned long set_reg, clr_reg, reg_width, field_width;
 	intc_enum enum_ids[16];
 };
 
-- 
cgit v1.2.3


From 73505b445dbb8ad12df468404c4dd5cde9c40c65 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Sun, 12 Aug 2007 15:26:12 +0900
Subject: sh: intc - rework core code

This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 6c759b2b892..0e6a6030497 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -75,7 +75,7 @@ struct intc_desc {
 	unsigned int nr_prio_regs;
 	struct intc_sense_reg *sense_regs;
 	unsigned int nr_sense_regs;
-	struct irq_chip chip;
+	char *name;
 };
 
 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -86,7 +86,7 @@ struct intc_desc symbol = {						\
 	_INTC_ARRAY(priorities),					\
 	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
 	_INTC_ARRAY(sense_regs),					\
-	.chip.name = chipname,						\
+	chipname,							\
 }
 
 void __init register_intc_controller(struct intc_desc *desc);
-- 
cgit v1.2.3


From 2eeec85638cebcb6fbcb2abfe182a32252f3456d Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Sun, 12 Aug 2007 15:29:16 +0900
Subject: sh: intc - convert board specific r2d code

This patch converts the board specific interrupt code for r2d to make
use of intc. While at it we improve the Kconfig to avoid confusion.

- Two sets of interrupt tables exist - one for R2D-1 and one for R2D-PLUS.
- R2D-1 and R2D-PLUS use the same irq constants.
- R2D-1 has AX88796 support, R2D-PLUS does not hook up that IRQ.
- R2D-PLUS has KEY support, R2D-1 does not hook up that IRQ.
- The number and order of IRQ values are disconnected from register bits.
- Interrupt sources now start from IRQ 100.
- The machvec demux function converts from irlm IRQ 0-14 to IRQ 100++.

Tested on R2D-1 and R2D-PLUS boards.

Version 2 adds CONFIG_RTS7751R2D_1 and CONFIG_RTS7751R2D_PLUS together
with intc structured as __initdata.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/rts7751r2d.h | 65 +++++++++++++++++++++------------------------
 1 file changed, 30 insertions(+), 35 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/rts7751r2d.h b/include/asm-sh/rts7751r2d.h
index 5d7800aa31b..83b9c111f17 100644
--- a/include/asm-sh/rts7751r2d.h
+++ b/include/asm-sh/rts7751r2d.h
@@ -9,7 +9,7 @@
  * Renesas Technology Sales RTS7751R2D support
  */
 
-/* Box specific addresses.  */
+/* Board specific addresses.  */
 
 #define PA_BCR		0xa4000000	/* FPGA */
 #define PA_IRLMON	0xa4000002	/* Interrupt Status control */
@@ -20,19 +20,19 @@
 #define PA_RTCCE	0xa400000c	/* RTC(9701) Enable control */
 #define PA_PCICD	0xa400000e	/* PCI Extention detect control */
 #define PA_VOYAGERRTS	0xa4000020	/* VOYAGER Reset control */
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define PA_AXRST	0xa4000022	/* AX_LAN Reset control */
-#define PA_CFRST	0xa4000024	/* CF Reset control */
-#define	PA_ADMRTS	0xa4000026	/* SD Reset control */
-#define PA_EXTRST	0xa4000028	/* Extention Reset control */
-#define PA_CFCDINTCLR	0xa400002a	/* CF Insert Interrupt clear */
-#else
-#define PA_CFRST	0xa4000022	/* CF Reset control */
-#define	PA_ADMRTS	0xa4000024	/* SD Reset control */
-#define PA_EXTRST	0xa4000026	/* Extention Reset control */
-#define PA_CFCDINTCLR	0xa4000028	/* CF Insert Interrupt clear */
-#define	PA_KEYCTLCLR	0xa400002a	/* Key Interrupt clear */
-#endif
+
+#define PA_R2D1_AXRST		0xa4000022	/* AX_LAN Reset control */
+#define PA_R2D1_CFRST		0xa4000024	/* CF Reset control */
+#define PA_R2D1_ADMRTS		0xa4000026	/* SD Reset control */
+#define PA_R2D1_EXTRST		0xa4000028	/* Extention Reset control */
+#define PA_R2D1_CFCDINTCLR	0xa400002a	/* CF Insert Interrupt clear */
+
+#define PA_R2DPLUS_CFRST	0xa4000022	/* CF Reset control */
+#define PA_R2DPLUS_ADMRTS	0xa4000024	/* SD Reset control */
+#define PA_R2DPLUS_EXTRST	0xa4000026	/* Extention Reset control */
+#define PA_R2DPLUS_CFCDINTCLR	0xa4000028	/* CF Insert Interrupt clear */
+#define PA_R2DPLUS_KEYCTLCLR	0xa400002a	/* Key Interrupt clear */
+
 #define PA_POWOFF	0xa4000030	/* Board Power OFF control */
 #define PA_VERREG	0xa4000032	/* FPGA Version Register */
 #define PA_INPORT	0xa4000034	/* KEY Input Port control */
@@ -46,27 +46,22 @@
 
 #define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */
 
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define IRQ_PCIETH	0		/* PCI Ethernet IRQ */
-#define IRQ_CFCARD	1		/* CF Card IRQ */
-#define IRQ_CFINST	2		/* CF Card Insert IRQ */
-#define IRQ_PCMCIA	3		/* PCMCIA IRQ */
-#define IRQ_VOYAGER	4		/* VOYAGER IRQ */
-#define IRQ_ONETH	5		/* On board Ethernet IRQ */
-#else
-#define IRQ_KEYIN	0		/* Key Input IRQ */
-#define IRQ_PCIETH	1		/* PCI Ethernet IRQ */
-#define IRQ_CFCARD	2		/* CF Card IRQ */
-#define IRQ_CFINST	3		/* CF Card Insert IRQ */
-#define IRQ_PCMCIA	4		/* PCMCIA IRQ */
-#define IRQ_VOYAGER	5		/* VOYAGER IRQ */
-#endif
-#define IRQ_RTCALM	6		/* RTC Alarm IRQ */
-#define IRQ_RTCTIME	7		/* RTC Timer IRQ */
-#define IRQ_SDCARD	8		/* SD Card IRQ */
-#define IRQ_PCISLOT1	9		/* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2	10		/* PCI Slot #2 IRQ */
-#define	IRQ_EXTENTION	11		/* EXTn IRQ */
+#define R2D_FPGA_IRQ_BASE	100
+
+#define IRQ_VOYAGER		(R2D_FPGA_IRQ_BASE + 0)
+#define IRQ_EXT			(R2D_FPGA_IRQ_BASE + 1)
+#define IRQ_TP			(R2D_FPGA_IRQ_BASE + 2)
+#define IRQ_RTC_T		(R2D_FPGA_IRQ_BASE + 3)
+#define IRQ_RTC_A		(R2D_FPGA_IRQ_BASE + 4)
+#define IRQ_SDCARD		(R2D_FPGA_IRQ_BASE + 5)
+#define IRQ_CF_CD		(R2D_FPGA_IRQ_BASE + 6)
+#define IRQ_CF_IDE		(R2D_FPGA_IRQ_BASE + 7)
+#define IRQ_AX88796		(R2D_FPGA_IRQ_BASE + 8)
+#define IRQ_KEY			(R2D_FPGA_IRQ_BASE + 9)
+#define IRQ_PCI_INTA		(R2D_FPGA_IRQ_BASE + 10)
+#define IRQ_PCI_INTB		(R2D_FPGA_IRQ_BASE + 11)
+#define IRQ_PCI_INTC		(R2D_FPGA_IRQ_BASE + 12)
+#define IRQ_PCI_INTD		(R2D_FPGA_IRQ_BASE + 13)
 
 /* arch/sh/boards/renesas/rts7751r2d/irq.c */
 void init_rts7751r2d_IRQ(void);
-- 
cgit v1.2.3


From 5c37e025352b993d8726b0207ff2270b2f2bc7d6 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 17 Aug 2007 00:45:35 +0900
Subject: sh: intc - mark data structures as __initdata

With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 0e6a6030497..0c016e94993 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -42,10 +42,10 @@ struct intc_prio {
 
 struct intc_group {
 	intc_enum enum_id;
-	intc_enum *enum_ids;
+	intc_enum enum_ids[32];
 };
 
-#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
 
 struct intc_mask_reg {
 	unsigned long set_reg, clr_reg, reg_width;
@@ -81,7 +81,7 @@ struct intc_desc {
 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
 #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
 	priorities, mask_regs, prio_regs, sense_regs)			\
-struct intc_desc symbol = {						\
+struct intc_desc symbol __initdata = {					\
 	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
 	_INTC_ARRAY(priorities),					\
 	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
-- 
cgit v1.2.3


From 3d37d94e5aab669f5a492bb3cda67bbbbbca50b8 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 17 Aug 2007 00:50:44 +0900
Subject: sh: intc - primary priority masking fixes

This patch contains various intc fixes for problems reported by
Markus Brunner on the linuxsh-dev mailing list:

http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1

Apart from added comments, the fixes are:

- add intc_set_priority() function prototype to hw_irq.h
- fix off-by-one error in intc_set_priority()
- make sure _INTC_WIDTH() is set for primary priority masking

Big thanks to Markus for finding these problems. Version two fixes
a compile error and an inverted primary check.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 0c016e94993..f9c90670e14 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -90,6 +90,7 @@ struct intc_desc symbol __initdata = {					\
 }
 
 void __init register_intc_controller(struct intc_desc *desc);
+int intc_set_priority(unsigned int irq, unsigned int prio);
 
 void __init plat_irq_setup(void);
 
-- 
cgit v1.2.3


From 8786c952c1682a132e99b736beae4523e409b13d Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Mon, 20 Aug 2007 13:03:41 +0900
Subject: sh: heartbeat driver update.

Add some flags for the heartbeat driver, and kill off some duplication
in the bit positions for the boards that don't have special cases.

This also allows for variable access widths and inversion.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/heartbeat.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 include/asm-sh/heartbeat.h

(limited to 'include')

diff --git a/include/asm-sh/heartbeat.h b/include/asm-sh/heartbeat.h
new file mode 100644
index 00000000000..724a43ed245
--- /dev/null
+++ b/include/asm-sh/heartbeat.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_HEARTBEAT_H
+#define __ASM_SH_HEARTBEAT_H
+
+#include <linux/timer.h>
+
+#define HEARTBEAT_INVERTED	(1 << 0)
+
+struct heartbeat_data {
+	void __iomem *base;
+	unsigned char *bit_pos;
+	unsigned int nr_bits;
+	struct timer_list timer;
+	unsigned int regsize;
+	unsigned long flags;
+};
+
+#endif /* __ASM_SH_HEARTBEAT_H */
-- 
cgit v1.2.3


From 8a467a529f01c3471b195a0e8989c6177fe145ef Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 22 Aug 2007 10:34:31 +0900
Subject: sh: Overhaul spinlocks and rwlocks for SH-4A SMP.

This rips out some of the old spinlock and rwlock behaviour that the SH-2
parts were using and reworks them for LL/SC semantics on the SH-4A.

This is primarily only useful for SH-X3 multi-cores, but can also be used
for building CONFIG_SMP=y testing kernels on SH-4A UP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/spinlock.h       | 181 +++++++++++++++++++++++++++++++---------
 include/asm-sh/spinlock_types.h |  11 +--
 2 files changed, 146 insertions(+), 46 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h
index 92f6e2008b2..e793181d64d 100644
--- a/include/asm-sh/spinlock.h
+++ b/include/asm-sh/spinlock.h
@@ -2,6 +2,7 @@
  * include/asm-sh/spinlock.h
  *
  * Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2006, 2007 Akio Idehara
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -10,17 +11,22 @@
 #ifndef __ASM_SH_SPINLOCK_H
 #define __ASM_SH_SPINLOCK_H
 
-#include <asm/atomic.h>
-#include <asm/spinlock_types.h>
+/*
+ * The only locking implemented here uses SH-4A opcodes. For others,
+ * split this out as per atomic-*.h.
+ */
+#ifndef CONFIG_CPU_SH4A
+#error "Need movli.l/movco.l for spinlocks"
+#endif
 
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
 
-#define __raw_spin_is_locked(x)	((x)->lock != 0)
+#define __raw_spin_is_locked(x)		((x)->lock <= 0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 #define __raw_spin_unlock_wait(x) \
-	do { cpu_relax(); } while (__raw_spin_is_locked(x))
+	do { cpu_relax(); } while ((x)->lock)
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -30,12 +36,19 @@
  */
 static inline void __raw_spin_lock(raw_spinlock_t *lock)
 {
+	unsigned long tmp;
+	unsigned long oldval;
+
 	__asm__ __volatile__ (
-		"1:\n\t"
-		"tas.b @%0\n\t"
-		"bf/s 1b\n\t"
-		"nop\n\t"
-		: "=r" (lock->lock)
+		"1:						\n\t"
+		"movli.l	@%2, %0	! __raw_spin_lock	\n\t"
+		"mov		%0, %1				\n\t"
+		"mov		#0, %0				\n\t"
+		"movco.l	%0, @%2				\n\t"
+		"bf		1b				\n\t"
+		"cmp/pl		%1				\n\t"
+		"bf		1b				\n\t"
+		: "=&z" (tmp), "=&r" (oldval)
 		: "r" (&lock->lock)
 		: "t", "memory"
 	);
@@ -43,12 +56,36 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
 
 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
-	//assert_spin_locked(lock);
+	unsigned long tmp;
 
-	lock->lock = 0;
+	__asm__ __volatile__ (
+		"mov		#1, %0 ! __raw_spin_unlock	\n\t"
+		"mov.l		%0, @%1				\n\t"
+		: "=&z" (tmp)
+		: "r" (&lock->lock)
+		: "t", "memory"
+	);
 }
 
-#define __raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock))
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+	unsigned long tmp, oldval;
+
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%2, %0	! __raw_spin_trylock	\n\t"
+		"mov		%0, %1				\n\t"
+		"mov		#0, %0				\n\t"
+		"movco.l	%0, @%2				\n\t"
+		"bf		1b				\n\t"
+		"synco						\n\t"
+		: "=&z" (tmp), "=&r" (oldval)
+		: "r" (&lock->lock)
+		: "t", "memory"
+	);
+
+	return oldval;
+}
 
 /*
  * Read-write spinlocks, allowing multiple readers but only one writer.
@@ -59,58 +96,124 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  * read-locks.
  */
 
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(x)	((x)->lock > 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(x)	((x)->lock == RW_LOCK_BIAS)
+
 static inline void __raw_read_lock(raw_rwlock_t *rw)
 {
-	__raw_spin_lock(&rw->lock);
-
-	atomic_inc(&rw->counter);
+	unsigned long tmp;
 
-	__raw_spin_unlock(&rw->lock);
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%1, %0	! __raw_read_lock	\n\t"
+		"cmp/pl		%0				\n\t"
+		"bf		1b				\n\t"
+		"add		#-1, %0				\n\t"
+		"movco.l	%0, @%1				\n\t"
+		"bf		1b				\n\t"
+		: "=&z" (tmp)
+		: "r" (&rw->lock)
+		: "t", "memory"
+	);
 }
 
 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
-	__raw_spin_lock(&rw->lock);
-
-	atomic_dec(&rw->counter);
+	unsigned long tmp;
 
-	__raw_spin_unlock(&rw->lock);
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%1, %0	! __raw_read_unlock	\n\t"
+		"add		#1, %0				\n\t"
+		"movco.l	%0, @%1				\n\t"
+		"bf		1b				\n\t"
+		: "=&z" (tmp)
+		: "r" (&rw->lock)
+		: "t", "memory"
+	);
 }
 
 static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
-	__raw_spin_lock(&rw->lock);
-	atomic_set(&rw->counter, -1);
+	unsigned long tmp;
+
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%1, %0	! __raw_write_lock	\n\t"
+		"cmp/hs		%2, %0				\n\t"
+		"bf		1b				\n\t"
+		"sub		%2, %0				\n\t"
+		"movco.l	%0, @%1				\n\t"
+		"bf		1b				\n\t"
+		: "=&z" (tmp)
+		: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+		: "t", "memory"
+	);
 }
 
 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 {
-	atomic_set(&rw->counter, 0);
-	__raw_spin_unlock(&rw->lock);
+	__asm__ __volatile__ (
+		"mov.l		%1, @%0 ! __raw_write_unlock	\n\t"
+		:
+		: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+		: "t", "memory"
+	);
 }
 
-static inline int __raw_write_can_lock(raw_rwlock_t *rw)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
 {
-	return (atomic_read(&rw->counter) == RW_LOCK_BIAS);
-}
+	unsigned long tmp, oldval;
 
-static inline int __raw_read_trylock(raw_rwlock_t *lock)
-{
-	atomic_t *count = (atomic_t*)lock;
-	if (atomic_dec_return(count) >= 0)
-		return 1;
-	atomic_inc(count);
-	return 0;
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%2, %0	! __raw_read_trylock	\n\t"
+		"mov		%0, %1				\n\t"
+		"cmp/pl		%0				\n\t"
+		"bf		2f				\n\t"
+		"add		#-1, %0				\n\t"
+		"movco.l	%0, @%2				\n\t"
+		"bf		1b				\n\t"
+		"2:						\n\t"
+		"synco						\n\t"
+		: "=&z" (tmp), "=&r" (oldval)
+		: "r" (&rw->lock)
+		: "t", "memory"
+	);
+
+	return (oldval > 0);
 }
 
 static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
-	if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter))
-		return 1;
-	
-	atomic_add(RW_LOCK_BIAS, &rw->counter);
+	unsigned long tmp, oldval;
+
+	__asm__ __volatile__ (
+		"1:						\n\t"
+		"movli.l	@%2, %0	! __raw_write_trylock	\n\t"
+		"mov		%0, %1				\n\t"
+		"cmp/hs		%3, %0				\n\t"
+		"bf		2f				\n\t"
+		"sub		%3, %0				\n\t"
+		"2:						\n\t"
+		"movco.l	%0, @%2				\n\t"
+		"bf		1b				\n\t"
+		"synco						\n\t"
+		: "=&z" (tmp), "=&r" (oldval)
+		: "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+		: "t", "memory"
+	);
 
-	return 0;
+	return (oldval > (RW_LOCK_BIAS - 1));
 }
 
 #define _raw_spin_relax(lock)	cpu_relax()
diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h
index 5c58134f2c4..b4d244e7b60 100644
--- a/include/asm-sh/spinlock_types.h
+++ b/include/asm-sh/spinlock_types.h
@@ -6,19 +6,16 @@
 #endif
 
 typedef struct {
-	volatile unsigned long lock;
+	volatile unsigned int lock;
 } raw_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED	{ 1 }
-
-#include <asm/atomic.h>
+#define __RAW_SPIN_LOCK_UNLOCKED		{ 1 }
 
 typedef struct {
-	raw_spinlock_t lock;
-	atomic_t counter;
+	volatile unsigned int lock;
 } raw_rwlock_t;
 
 #define RW_LOCK_BIAS			0x01000000
-#define __RAW_RW_LOCK_UNLOCKED		{ { 0 }, { RW_LOCK_BIAS } }
+#define __RAW_RW_LOCK_UNLOCKED		{ RW_LOCK_BIAS }
 
 #endif
-- 
cgit v1.2.3


From 953c8ef250fc6c329d1607cf9cd7fac1d72d7579 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Mon, 10 Sep 2007 12:03:50 +0900
Subject: sh: intc - irl mode update for sh7780 and sh7785

This patch contains the following fixes and improvements:
- Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780.
- Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking.
- Good old IRQ_MODE_IRLnnnn should not register any intc controller.
- plat_irq_setup_pins() now selects IRL or IRQ mode.
- the holding function is now disabled using ICR0.

By default all external pin interrupts are disabled.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index f9c90670e14..96d97104050 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -95,6 +95,7 @@ int intc_set_priority(unsigned int irq, unsigned int prio);
 void __init plat_irq_setup(void);
 
 enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
+       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
        IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
 void __init plat_irq_setup_pins(int mode);
 
-- 
cgit v1.2.3


From 897cfcd878ccc9c2b0f1b3bb00a2368c43feafc0 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Mon, 10 Sep 2007 12:06:03 +0900
Subject: sh: intc - rework higlander irq code for r7780mp and r7785rp

This patch reworks the highlander irq code for r7780mp and r7785rp.
The same strategy as for the new R2D code is used here - the board
specific interrupts are now starting from HL_FPGA_IRQ_BASE. The code
for r7780rp is not touched due to lack of hardware.

Tested with CF, AX88796 on r7780mp and r7785rp. The touch switch
interrupt has also been tested on r7780mp.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/r7780rp.h | 33 ++++++++++++++-------------------
 1 file changed, 14 insertions(+), 19 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index 4083b594992..de37f933aa4 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -65,24 +65,6 @@
 #define PA_PMR          (PA_BCR+0x0900) /*  */
 
 #define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
-
-#define IRQ_PCISLOT1    65              /* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2    66              /* PCI Slot #2 IRQ */
-#define IRQ_PCISLOT3    67              /* PCI Slot #3 IRQ */
-#define IRQ_PCISLOT4    68              /* PCI Slot #4 IRQ */
-#define IRQ_TP          2               /* Touch Panel IRQ */
-#define IRQ_SCI1        3               /* SCI1 IRQ */
-#define IRQ_SCI0        4               /* SCI0 IRQ */
-#define IRQ_2SERIAL     5               /* Serial IRQ */
-#define IRQ_RTC         6               /* RTC A / B IRQ */
-#define IRQ_EXTENTION6  7               /* EXT6n IRQ */
-#define IRQ_EXTENTION5  8               /* EXT5n IRQ */
-#define IRQ_EXTENTION4  9               /* EXT4n IRQ */
-#define IRQ_EXTENTION2  10              /* EXT2n IRQ */
-#define IRQ_EXTENTION1  11              /* EXT1n IRQ */
-#define IRQ_ONETH       13              /* On board Ethernet IRQ */
-#define IRQ_PSW         14              /* Push Switch IRQ */
-
 #define IVDR_CK_ON	8		/* iVDR Clock ON */
 
 #elif defined(CONFIG_SH_R7780RP)
@@ -203,11 +185,24 @@
 #define PA_MMSR		(PA_BCR+0x0400)
 
 #define IVDR_CK_ON	4		/* iVDR Clock ON */
+#endif
 
+#define HL_FPGA_IRQ_BASE	200
+#define HL_NR_IRL		15
+
+#define IRQ_AX88796		(HL_FPGA_IRQ_BASE + 0)
+#define IRQ_CF			(HL_FPGA_IRQ_BASE + 1)
+#ifndef IRQ_PSW
+#define IRQ_PSW			(HL_FPGA_IRQ_BASE + 2)
 #endif
+#define IRQ_EXT1		(HL_FPGA_IRQ_BASE + 3)
+#define IRQ_EXT4		(HL_FPGA_IRQ_BASE + 4)
 
 void make_r7780rp_irq(unsigned int irq);
-void highlander_init_irq(void);
+
+unsigned char *highlander_init_irq_r7780mp(void);
+unsigned char *highlander_init_irq_r7780rp(void);
+unsigned char *highlander_init_irq_r7785rp(void);
 
 #define __IO_PREFIX	r7780rp
 #include <asm/io_generic.h>
-- 
cgit v1.2.3


From da6b003adc73011fd441a89c30d4f896667e24ba Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Mon, 10 Sep 2007 12:08:42 +0900
Subject: sh: add writesb(), readsb(), writesw() and readsw() to io.h

This patch adds inline versions of writesb(), readsb(), writesw() and
readsw() to include/asm-sh/io.h. Stolen from include/asm-avr32/io.h.

These functions are needed to compile certain device drivers such as
ax88796.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/io.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'include')

diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index e6a1877dcb2..1a336cdc75f 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -135,6 +135,32 @@ void __raw_readsl(unsigned long addr, void *data, int longlen);
 # define writel(v,a)	({ __raw_writel((v),(a)); mb(); })
 #endif
 
+#define __BUILD_MEMORY_STRING(bwlq, type)				\
+									\
+static inline void writes##bwlq(volatile void __iomem *mem,		\
+				const void *addr, unsigned int count)	\
+{									\
+	const volatile type *__addr = addr;				\
+									\
+	while (count--) {						\
+		__raw_write##bwlq(*__addr, mem);			\
+		__addr++;						\
+	}								\
+}									\
+									\
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
+			       unsigned int count)			\
+{									\
+	volatile type *__addr = addr;					\
+									\
+	while (count--) {						\
+		*__addr = __raw_read##bwlq(mem);			\
+		__addr++;						\
+	}								\
+}
+
+__BUILD_MEMORY_STRING(b, u8)
+__BUILD_MEMORY_STRING(w, u16)
 #define writesl __raw_writesl
 #define readsl  __raw_readsl
 
-- 
cgit v1.2.3


From f12468a6fd9edc43c7beb8be461ca6927a371540 Mon Sep 17 00:00:00 2001
From: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Date: Tue, 11 Sep 2007 12:37:30 +0900
Subject: sh: Fix OFFCHIP_IRQ_BASE compile error.

HP6xx uses OFFCHIP_IRQ_BASE to know the base irq number where non
cpu interrupts should start. This define was in irq.h before, but
since rework got lost. It really belongs inside hd64461.h since
the hp6xx wont work without it.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hd64461.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
index 4dd8592ca01..342ca55a266 100644
--- a/include/asm-sh/hd64461.h
+++ b/include/asm-sh/hd64461.h
@@ -226,6 +226,7 @@
 #define	HD64461_NIMR		(CONFIG_HD64461_IOBASE + 0x5002)
 
 #define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE
+#define	OFFCHIP_IRQ_BASE	64
 #define	HD64461_IRQ_NUM		16
 
 #define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)
-- 
cgit v1.2.3


From 4f247e84bdb81aab8880f556882a449782a1ea8b Mon Sep 17 00:00:00 2001
From: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Date: Tue, 11 Sep 2007 12:49:59 +0900
Subject: sh: dma: Fix up build for SH7709 support.

Trivial build fixes for SH7709.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cpu-sh3/dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index e56203086eb..54bfece328c 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -2,7 +2,7 @@
 #define __ASM_CPU_SH3_DMA_H
 
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define SH_DMAC_BASE	0xa4010020
 
 #define DMTE0_IRQ	48
-- 
cgit v1.2.3


From d581593388e39d77acd643b1d7427c5ecbb85a03 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Tue, 11 Sep 2007 17:55:36 +0900
Subject: sh: dma: Fix CONFIG_SYSFS=n build.

Trivial build fix for when sysfs is disabled.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/dma.h | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index 4c75b70b641..a65b02fd186 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -152,14 +152,9 @@ extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
 extern int dma_extend(unsigned int chan, unsigned long op, void *param);
 extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
 
-#ifdef CONFIG_SYSFS
 /* arch/sh/drivers/dma/dma-sysfs.c */
 extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
 extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
-#else
-#define dma_create_sysfs_file(channel, info)		do { } while (0)
-#define dma_remove_sysfs_file(channel, info)		do { } while (0)
-#endif
 
 #ifdef CONFIG_PCI
 extern int isa_dma_bridge_buggy;
-- 
cgit v1.2.3


From ded5431ff311d963888ac951131a04fe7633aa79 Mon Sep 17 00:00:00 2001
From: Markus Brunner <super.firetwister@gmail.com>
Date: Wed, 12 Sep 2007 11:54:58 +0900
Subject: sh: Magic Panel R2 board support.

This adds support for the SH7720 (SH3-DSP) based Magic Panel R2
board.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/magicpanelr2.h | 67 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 include/asm-sh/magicpanelr2.h

(limited to 'include')

diff --git a/include/asm-sh/magicpanelr2.h b/include/asm-sh/magicpanelr2.h
new file mode 100644
index 00000000000..c644a77ee35
--- /dev/null
+++ b/include/asm-sh/magicpanelr2.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/magicpanelr2.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  I/O addresses and bitmasks for Magic Panel Release 2 board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH_MAGICPANELR2_H
+#define __ASM_SH_MAGICPANELR2_H
+
+#include <asm/gpio.h>
+
+#define __IO_PREFIX mpr2
+#include <asm/io_generic.h>
+
+
+#define SETBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+
+
+#define PA_LED          PORT_PADR      /* LED */
+
+
+/* BSC */
+#define CMNCR           0xA4FD0000UL
+#define CS0BCR          0xA4FD0004UL
+#define CS2BCR          0xA4FD0008UL
+#define CS3BCR          0xA4FD000CUL
+#define CS4BCR          0xA4FD0010UL
+#define CS5ABCR         0xA4FD0014UL
+#define CS5BBCR         0xA4FD0018UL
+#define CS6ABCR         0xA4FD001CUL
+#define CS6BBCR         0xA4FD0020UL
+#define CS0WCR          0xA4FD0024UL
+#define CS2WCR          0xA4FD0028UL
+#define CS3WCR          0xA4FD002CUL
+#define CS4WCR          0xA4FD0030UL
+#define CS5AWCR         0xA4FD0034UL
+#define CS5BWCR         0xA4FD0038UL
+#define CS6AWCR         0xA4FD003CUL
+#define CS6BWCR         0xA4FD0040UL
+
+
+/* usb */
+
+#define PORT_UTRCTL		0xA405012CUL
+#define PORT_UCLKCR_W		0xA40A0008UL
+
+#define INTC_ICR0		0xA414FEE0UL
+#define INTC_ICR1		0xA4140010UL
+#define INTC_ICR2		0xA4140012UL
+
+/* MTD */
+
+#define MPR2_MTD_BOOTLOADER_SIZE	0x00060000UL
+#define MPR2_MTD_KERNEL_SIZE		0x00200000UL
+
+#endif  /* __ASM_SH_MAGICPANELR2_H */
-- 
cgit v1.2.3


From d04a0f79f502a87bb17b147afc4b3e39e75275c3 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Fri, 21 Sep 2007 11:55:03 +0900
Subject: sh: Fix up extended mode TLB for SH-X2+ cores.

The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
correspondingly, the PGD also has to be 64-bits, so fix that up.

The kernel and user permission bits really are decoupled in early
cuts of the silicon, which means that we also have to set corresponding
kernel permissions on user pages or we end up with user pages that the
kernel simply can't touch (!).

Finally, with those things corrected, really enable MMUCR.ME and
correct the PTEA value (this simply needs to be the upper 32-bits
of the PTE, with the size and protection bit encoding).

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cpu-sh4/mmu_context.h |  14 ++++-
 include/asm-sh/page.h                |   4 +-
 include/asm-sh/pgtable.h             | 112 +++++++++++++++++++----------------
 3 files changed, 75 insertions(+), 55 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
index ff4c5fbbfaf..979acddc0f8 100644
--- a/include/asm-sh/cpu-sh4/mmu_context.h
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -22,13 +22,21 @@
 #define MMU_UTLB_ADDRESS_ARRAY	0xF6000000
 #define MMU_PAGE_ASSOC_BIT	0x80
 
-#define MMU_NTLB_ENTRIES	64	/* for 7750 */
+#ifdef CONFIG_X2TLB
+#define MMUCR_ME		(1 << 7)
+#else
+#define MMUCR_ME		(0)
+#endif
+
 #ifdef CONFIG_SH_STORE_QUEUES
-#define MMU_CONTROL_INIT	0x05	/* SQMD=0, SV=0, TI=1, AT=1 */
+#define MMUCR_SQMD		(1 << 9)
 #else
-#define MMU_CONTROL_INIT	0x205	/* SQMD=1, SV=0, TI=1, AT=1 */
+#define MMUCR_SQMD		(0)
 #endif
 
+#define MMU_NTLB_ENTRIES	64
+#define MMU_CONTROL_INIT	(0x05|MMUCR_SQMD|MMUCR_ME)
+
 #define MMU_ITLB_DATA_ARRAY	0xF3000000
 #define MMU_UTLB_DATA_ARRAY	0xF7000000
 
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 48b718e7455..cb3d46c59ea 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -88,6 +88,7 @@ extern void __copy_user_page(void *to, void *from, void *orig_to);
 #ifdef CONFIG_X2TLB
 typedef struct { unsigned long pte_low, pte_high; } pte_t;
 typedef struct { unsigned long long pgprot; } pgprot_t;
+typedef struct { unsigned long long pgd; } pgd_t;
 #define pte_val(x) \
 	((x).pte_low | ((unsigned long long)(x).pte_high << 32))
 #define __pte(x) \
@@ -95,12 +96,11 @@ typedef struct { unsigned long long pgprot; } pgprot_t;
 #else
 typedef struct { unsigned long pte_low; } pte_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgd; } pgd_t;
 #define pte_val(x)	((x).pte_low)
 #define __pte(x) ((pte_t) { (x) } )
 #endif
 
-typedef struct { unsigned long pgd; } pgd_t;
-
 #define pgd_val(x)	((x).pgd)
 #define pgprot_val(x)	((x).pgprot)
 
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 54ad5037fe4..cf0dd2b648c 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -42,13 +42,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 
 /* PGD bits */
 #define PGDIR_SHIFT	(PTE_SHIFT + PTE_BITS)
-#define PGDIR_BITS	(32 - PGDIR_SHIFT)
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
 /* Entries per level */
 #define PTRS_PER_PTE	(PAGE_SIZE / (1 << PTE_MAGNITUDE))
-#define PTRS_PER_PGD	(PAGE_SIZE / 4)
+#define PTRS_PER_PGD	(PAGE_SIZE / sizeof(pgd_t))
 
 #define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS	0
@@ -100,17 +99,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #define _PAGE_HW_SHARED	0x002		/* SH-bit  : shared among processes */
 #define _PAGE_DIRTY	0x004		/* D-bit   : page changed */
 #define _PAGE_CACHABLE	0x008		/* C-bit   : cachable */
-#ifndef CONFIG_X2TLB
-# define _PAGE_SZ0	0x010		/* SZ0-bit : Size of page */
-# define _PAGE_RW	0x020		/* PR0-bit : write access allowed */
-# define _PAGE_USER	0x040		/* PR1-bit : user space access allowed*/
-# define _PAGE_SZ1	0x080		/* SZ1-bit : Size of page (on SH-4) */
-#endif
+#define _PAGE_SZ0	0x010		/* SZ0-bit : Size of page */
+#define _PAGE_RW	0x020		/* PR0-bit : write access allowed */
+#define _PAGE_USER	0x040		/* PR1-bit : user space access allowed*/
+#define _PAGE_SZ1	0x080		/* SZ1-bit : Size of page (on SH-4) */
 #define _PAGE_PRESENT	0x100		/* V-bit   : page is valid */
 #define _PAGE_PROTNONE	0x200		/* software: if not present  */
 #define _PAGE_ACCESSED	0x400		/* software: page referenced */
 #define _PAGE_FILE	_PAGE_WT	/* software: pagecache or swap? */
 
+#define _PAGE_SZ_MASK	(_PAGE_SZ0 | _PAGE_SZ1)
+#define _PAGE_PR_MASK	(_PAGE_RW | _PAGE_USER)
+
 /* Extended mode bits */
 #define _PAGE_EXT_ESZ0		0x0010	/* ESZ0-bit: Size of page */
 #define _PAGE_EXT_ESZ1		0x0020	/* ESZ1-bit: Size of page */
@@ -126,11 +126,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #define _PAGE_EXT_KERN_READ	0x2000	/* EPR5-bit: Kernel space readable */
 
 /* Wrapper for extended mode pgprot twiddling */
-#ifdef CONFIG_X2TLB
-# define _PAGE_EXT(x)		((unsigned long long)(x) << 32)
-#else
-# define _PAGE_EXT(x)		(0)
-#endif
+#define _PAGE_EXT(x)		((unsigned long long)(x) << 32)
 
 /* software: moves to PTEA.TC (Timing Control) */
 #define _PAGE_PCC_AREA5	0x00000000	/* use BSC registers for area5 */
@@ -146,10 +142,14 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #define _PAGE_PCC_ATR16	0x60000001	/* Attribute Memory space, 6 bit bus */
 
 /* Mask which drops unused bits from the PTEL value */
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3)
 #define _PAGE_CLEAR_FLAGS	(_PAGE_PROTNONE | _PAGE_ACCESSED| \
 				 _PAGE_FILE	| _PAGE_SZ1	| \
 				 _PAGE_HW_SHARED)
+#elif defined(CONFIG_X2TLB)
+/* Get rid of the legacy PR/SZ bits when using extended mode */
+#define _PAGE_CLEAR_FLAGS	(_PAGE_PROTNONE | _PAGE_ACCESSED | \
+				 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
 #else
 #define _PAGE_CLEAR_FLAGS	(_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
 #endif
@@ -212,27 +212,36 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 
 #define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 				 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
-				 _PAGE_EXT(_PAGE_EXT_USER_READ | \
+				 _PAGE_EXT(_PAGE_EXT_KERN_READ  | \
+					   _PAGE_EXT_KERN_WRITE | \
+					   _PAGE_EXT_USER_READ  | \
 					   _PAGE_EXT_USER_WRITE))
 
 #define PAGE_EXECREAD	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 				 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
-				 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
+				 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
+					   _PAGE_EXT_KERN_READ | \
+					   _PAGE_EXT_USER_EXEC | \
 					   _PAGE_EXT_USER_READ))
 
 #define PAGE_COPY	PAGE_EXECREAD
 
 #define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 				 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
-				 _PAGE_EXT(_PAGE_EXT_USER_READ))
+				 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+					   _PAGE_EXT_USER_READ))
 
 #define PAGE_WRITEONLY	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 				 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
-				 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
+				 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+					   _PAGE_EXT_USER_WRITE))
 
 #define PAGE_RWX	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 				 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
-				 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
+				 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+					   _PAGE_EXT_KERN_READ  | \
+					   _PAGE_EXT_KERN_EXEC  | \
+					   _PAGE_EXT_USER_WRITE | \
 					   _PAGE_EXT_USER_READ  | \
 					   _PAGE_EXT_USER_EXEC))
 
@@ -373,11 +382,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
 
 #define pte_pfn(x)		((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
-#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot)	__pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 
-#define pte_none(x)	(!pte_val(x))
-#define pte_present(x)	(pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
+#define pfn_pte(pfn, prot) \
+	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) \
+	__pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#define pte_none(x)		(!pte_val(x))
+#define pte_present(x)		((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
+
 #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 
 #define pmd_none(x)	(!pmd_val(x))
@@ -392,15 +405,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
-#define pte_not_present(pte)	(!(pte_val(pte) & _PAGE_PRESENT))
-#define pte_dirty(pte)		(pte_val(pte) & _PAGE_DIRTY)
-#define pte_young(pte)		(pte_val(pte) & _PAGE_ACCESSED)
-#define pte_file(pte)		(pte_val(pte) & _PAGE_FILE)
+#define pte_not_present(pte)	(!((pte).pte_low & _PAGE_PRESENT))
+#define pte_dirty(pte)		((pte).pte_low & _PAGE_DIRTY)
+#define pte_young(pte)		((pte).pte_low & _PAGE_ACCESSED)
+#define pte_file(pte)		((pte).pte_low & _PAGE_FILE)
 
 #ifdef CONFIG_X2TLB
 #define pte_write(pte)		((pte).pte_high & _PAGE_EXT_USER_WRITE)
 #else
-#define pte_write(pte)		(pte_val(pte) & _PAGE_RW)
+#define pte_write(pte)		((pte).pte_low & _PAGE_RW)
 #endif
 
 #define PTE_BIT_FUNC(h,fn,op) \
@@ -429,17 +442,10 @@ PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
 /*
  * Macro and implementation to make a page protection as uncachable.
  */
-#define pgprot_noncached pgprot_noncached
+#define pgprot_writecombine(prot) \
+	__pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
 
-static inline pgprot_t pgprot_noncached(pgprot_t _prot)
-{
-	unsigned long prot = pgprot_val(_prot);
-
-	prot &= ~_PAGE_CACHABLE;
-	return __pgprot(prot);
-}
-
-#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
+#define pgprot_noncached	 pgprot_writecombine
 
 /*
  * Conversion functions: convert a page and protection to a page entry,
@@ -451,28 +457,33 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
-			    pgprot_val(newprot)));
+	pte.pte_low &= _PAGE_CHG_MASK;
+	pte.pte_low |= pgprot_val(newprot);
+
+#ifdef CONFIG_X2TLB
+	pte.pte_high |= pgprot_val(newprot) >> 32;
+#endif
+
 	return pte;
 }
 
-#define pmd_page_vaddr(pmd)	pmd_val(pmd)
+#define pmd_page_vaddr(pmd)	((unsigned long)pmd_val(pmd))
 #define pmd_page(pmd)		(virt_to_page(pmd_val(pmd)))
 
 /* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_offset(mm, address)	((mm)->pgd+pgd_index(address))
 
 /* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+#define pgd_offset_k(address)	pgd_offset(&init_mm, address)
 
 /* Find an entry in the third-level page table.. */
-#define pte_index(address) \
-		((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_index(address)	((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset_kernel(dir, address) \
 	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
-#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
-#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
+#define pte_offset_map(dir, address)		pte_offset_kernel(dir, address)
+#define pte_offset_map_nested(dir, address)	pte_offset_kernel(dir, address)
+
 #define pte_unmap(pte)		do { } while (0)
 #define pte_unmap_nested(pte)	do { } while (0)
 
@@ -480,13 +491,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_ERROR(e) \
 	printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
 	       &(e), (e).pte_high, (e).pte_low)
+#define pgd_ERROR(e) \
+	printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
 #else
 #define pte_ERROR(e) \
 	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#endif
-
 #define pgd_ERROR(e) \
 	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+#endif
 
 struct vm_area_struct;
 extern void update_mmu_cache(struct vm_area_struct * vma,
-- 
cgit v1.2.3


From 17be2d2b1c333e1e4c378369ba90ab2dd11c589a Mon Sep 17 00:00:00 2001
From: Adrian McMenamin <adrian@mcmen.demon.co.uk>
Date: Fri, 21 Sep 2007 15:55:55 +0900
Subject: sh: Add maple bus support for the SEGA Dreamcast.

The Maple bus is SEGA's proprietary serial bus for peripherals
(keyboard, mouse, controller etc). The bus is capable of some
(limited) hotplugging and operates at up to 2 M/bits.

Drivers of one sort or another existed/exist for 2.4 and a rudimentary
port, which didn't support the 2.6 device driver model was also in
existence.

This driver - for the bus logic itself and for the keyboard (other
drivers will follow) are based on the code and concepts of those old
drivers but have lots of completely rewritten parts.

I have the maple bus code as a built in now as that seems the sane and
rational way to handle something like that - you either want the bus
or you don't.

Signed-off-by: Adrian McMenamin <adrian@mcmen.demon.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/dreamcast/maple.h | 37 +++++++++++++++++++
 include/linux/maple.h            | 80 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 117 insertions(+)
 create mode 100644 include/asm-sh/dreamcast/maple.h
 create mode 100644 include/linux/maple.h

(limited to 'include')

diff --git a/include/asm-sh/dreamcast/maple.h b/include/asm-sh/dreamcast/maple.h
new file mode 100644
index 00000000000..51f6a87f1f1
--- /dev/null
+++ b/include/asm-sh/dreamcast/maple.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_MAPLE_H
+#define __ASM_MAPLE_H
+
+#define MAPLE_PORTS 4
+#define MAPLE_PNP_INTERVAL HZ
+#define MAPLE_MAXPACKETS 8
+#define MAPLE_DMA_ORDER 14
+#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
+#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
+			  MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
+
+/* Maple Bus registers */
+#define MAPLE_BASE     0xa05f6c00
+#define MAPLE_DMAADDR  (MAPLE_BASE+0x04)
+#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
+#define MAPLE_ENABLE   (MAPLE_BASE+0x14)
+#define MAPLE_STATE    (MAPLE_BASE+0x18)
+#define MAPLE_SPEED    (MAPLE_BASE+0x80)
+#define MAPLE_RESET    (MAPLE_BASE+0x8c)
+
+#define MAPLE_MAGIC    0x6155404f
+#define MAPLE_2MBPS    0
+#define MAPLE_TIMEOUT(n) ((n)<<15)
+
+/* Function codes */
+#define MAPLE_FUNC_CONTROLLER 0x001
+#define MAPLE_FUNC_MEMCARD    0x002
+#define MAPLE_FUNC_LCD        0x004
+#define MAPLE_FUNC_CLOCK      0x008
+#define MAPLE_FUNC_MICROPHONE 0x010
+#define MAPLE_FUNC_ARGUN      0x020
+#define MAPLE_FUNC_KEYBOARD   0x040
+#define MAPLE_FUNC_LIGHTGUN   0x080
+#define MAPLE_FUNC_PURUPURU   0x100
+#define MAPLE_FUNC_MOUSE      0x200
+
+#endif /* __ASM_MAPLE_H */
diff --git a/include/linux/maple.h b/include/linux/maple.h
new file mode 100644
index 00000000000..bad9a7b319d
--- /dev/null
+++ b/include/linux/maple.h
@@ -0,0 +1,80 @@
+#ifndef __LINUX_MAPLE_H
+#define __LINUX_MAPLE_H
+
+#include <linux/device.h>
+
+extern struct bus_type maple_bus_type;
+
+/* Maple Bus command and response codes */
+enum maple_code {
+       MAPLE_RESPONSE_FILEERR = -5,
+       MAPLE_RESPONSE_AGAIN = -4,      /* request should be retransmitted */
+       MAPLE_RESPONSE_BADCMD = -3,
+       MAPLE_RESPONSE_BADFUNC = -2,
+       MAPLE_RESPONSE_NONE = -1,       /* unit didn't respond at all */
+       MAPLE_COMMAND_DEVINFO = 1,
+       MAPLE_COMMAND_ALLINFO = 2,
+       MAPLE_COMMAND_RESET = 3,
+       MAPLE_COMMAND_KILL = 4,
+       MAPLE_RESPONSE_DEVINFO = 5,
+       MAPLE_RESPONSE_ALLINFO = 6,
+       MAPLE_RESPONSE_OK = 7,
+       MAPLE_RESPONSE_DATATRF = 8,
+       MAPLE_COMMAND_GETCOND = 9,
+       MAPLE_COMMAND_GETMINFO = 10,
+       MAPLE_COMMAND_BREAD = 11,
+       MAPLE_COMMAND_BWRITE = 12,
+       MAPLE_COMMAND_SETCOND = 14
+};
+
+struct mapleq {
+       struct list_head list;
+       struct maple_device *dev;
+       void *sendbuf, *recvbuf, *recvbufdcsp;
+       unsigned char length;
+       enum maple_code command;
+};
+
+struct maple_devinfo {
+       unsigned long function;
+       unsigned long function_data[3];
+       unsigned char area_code;
+       unsigned char connector_directon;
+       char product_name[31];
+       char product_licence[61];
+       unsigned short standby_power;
+       unsigned short max_power;
+};
+
+struct maple_device {
+       struct maple_driver *driver;
+       struct mapleq *mq;
+       void *private_data;
+       void (*callback) (struct mapleq * mq);
+       unsigned long when, interval, function;
+       struct maple_devinfo devinfo;
+       unsigned char port, unit;
+       char product_name[32];
+       char product_licence[64];
+       int registered;
+       struct device dev;
+};
+
+struct maple_driver {
+       unsigned long function;
+       int (*connect) (struct maple_device * dev);
+       void (*disconnect) (struct maple_device * dev);
+       struct device_driver drv;
+};
+
+void maple_getcond_callback(struct maple_device *dev,
+                           void (*callback) (struct mapleq * mq),
+                           unsigned long interval,
+                           unsigned long function);
+int maple_driver_register(struct device_driver *drv);
+void maple_add_packet(struct mapleq *mq);
+
+#define to_maple_dev(n) container_of(n, struct maple_device, dev)
+#define to_maple_driver(n) container_of(n, struct maple_driver, drv)
+
+#endif /* __LINUX_MAPLE_H */
-- 
cgit v1.2.3


From 2d4a73d5b91528322631830784f4eb7897fb5e41 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Fri, 21 Sep 2007 18:01:40 +0900
Subject: sh: Kill off special boot_cpu_data.

This consolidates the cpu_data definitions and gets rid of the special
boot_cpu_data. It's made a wrapper to the boot CPU, in order to keep
the existing in-tree users happy.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/processor.h | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 56cb3c89f84..4f2922a1979 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -73,15 +73,10 @@ struct sh_cpuinfo {
 	unsigned long flags;
 } __attribute__ ((aligned(SMP_CACHE_BYTES)));
 
-extern struct sh_cpuinfo boot_cpu_data;
-
-#ifdef CONFIG_SMP
 extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
 #define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
 
 /*
  * User space process size: 2GB.
-- 
cgit v1.2.3


From f18d533e3cd476aedf41fe1e6e9dc3e0a2446bba Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Fri, 21 Sep 2007 18:16:42 +0900
Subject: sh: intc - initial SMP support.

This implements initial support for the SMP INTC (particularly
INTC2) controllers.

These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/hw_irq.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'include')

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 96d97104050..cb0b6c9f702 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -50,11 +50,17 @@ struct intc_group {
 struct intc_mask_reg {
 	unsigned long set_reg, clr_reg, reg_width;
 	intc_enum enum_ids[32];
+#ifdef CONFIG_SMP
+	unsigned long smp;
+#endif
 };
 
 struct intc_prio_reg {
 	unsigned long set_reg, clr_reg, reg_width, field_width;
 	intc_enum enum_ids[16];
+#ifdef CONFIG_SMP
+	unsigned long smp;
+#endif
 };
 
 struct intc_sense_reg {
@@ -62,6 +68,12 @@ struct intc_sense_reg {
 	intc_enum enum_ids[16];
 };
 
+#ifdef CONFIG_SMP
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#else
+#define INTC_SMP(stride, nr)
+#endif
+
 struct intc_desc {
 	struct intc_vect *vectors;
 	unsigned int nr_vectors;
-- 
cgit v1.2.3


From aba1030a7e529ec9fe47a8cfc06d12a39180fa71 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Fri, 21 Sep 2007 18:32:32 +0900
Subject: sh: Bring SMP support back from the dead.

There was a very preliminary bunch of SMP code scattered around for the
SH7604 microcontrollers from way back when, and it has mostly suffered
bitrot since then. With the tree already having been slowly getting
prepped for SMP, this plugs in most of the remaining platform-independent
bits.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/smp.h    | 34 +++++++++++++++++++++++-----------
 include/asm-sh/system.h |  1 +
 2 files changed, 24 insertions(+), 11 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index b99ca786c0c..9c8d34b07eb 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -1,12 +1,3 @@
-/*
- * include/asm-sh/smp.h
- *
- * Copyright (C) 2002, 2003  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive for
- * more details.
- */
 #ifndef __ASM_SH_SMP_H
 #define __ASM_SH_SMP_H
 
@@ -20,6 +11,15 @@
 #include <asm/current.h>
 
 #define raw_smp_processor_id()	(current_thread_info()->cpu)
+#define hard_smp_processor_id()	plat_smp_processor_id()
+
+/* Map from cpu id to sequential logical cpu number. */
+extern int __cpu_number_map[NR_CPUS];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
 
 /* I've no idea what the real meaning of this is */
 #define PROC_CHANGE_PENALTY	20
@@ -35,10 +35,22 @@ struct smp_fn_call_struct {
 
 extern struct smp_fn_call_struct smp_fn_call;
 
-#define SMP_MSG_RESCHEDULE	0x0001
+#define SMP_MSG_FUNCTION	0
+#define SMP_MSG_RESCHEDULE	1
+#define SMP_MSG_NR		2
 
-#endif /* CONFIG_SMP */
+void plat_smp_setup(void);
+void plat_prepare_cpus(unsigned int max_cpus);
+int plat_smp_processor_id(void);
+void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
+void plat_send_ipi(unsigned int cpu, unsigned int message);
+int plat_register_ipi_handler(unsigned int message,
+			      void (*handler)(void *), void *arg);
+
+#else
 
 #define hard_smp_processor_id()	(0)
 
+#endif /* CONFIG_SMP */
+
 #endif /* __ASM_SH_SMP_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 24504253720..9d849e6df26 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -266,6 +266,7 @@ void disable_hlt(void);
 void enable_hlt(void);
 
 void default_idle(void);
+void per_cpu_trap_init(void);
 
 asmlinkage void break_point_trap(void);
 asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
-- 
cgit v1.2.3


From 1f91bbb58413e0bce9726cd6d12bf4b95c343a7f Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Mon, 24 Sep 2007 18:11:27 +0900
Subject: sh: Define _ebss for uClinux MTD map driver.

The uClinux MTD device uses _ebss, add the symbol and corresponding
export.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/sections.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h
index 2a696b8ee4f..bd9cbc967c2 100644
--- a/include/asm-sh/sections.h
+++ b/include/asm-sh/sections.h
@@ -4,6 +4,7 @@
 #include <asm-generic/sections.h>
 
 extern long __machvec_start, __machvec_end;
+extern char _ebss[];
 
 #endif /* __ASM_SH_SECTIONS_H */
 
-- 
cgit v1.2.3


From 09a4df5f0c8b7c418821fe591bf0d0f13b206c61 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Thu, 27 Sep 2007 12:57:35 +0900
Subject: sh: processor.h needs smp.h

Trivial build fix for SH-2.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/processor.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 4f2922a1979..9f3ee775fe1 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -10,6 +10,7 @@
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
+#include <linux/smp.h>
 #include <asm/page.h>
 #include <asm/types.h>
 #include <asm/cache.h>
-- 
cgit v1.2.3


From cb7af21f7d370edb3a6a6d3e15cb17c8fd61591e Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Thu, 27 Sep 2007 18:18:39 +0900
Subject: sh: Use boot_cpu_data for CPU probe.

This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/processor.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 9f3ee775fe1..4f2922a1979 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -10,7 +10,6 @@
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
-#include <linux/smp.h>
 #include <asm/page.h>
 #include <asm/types.h>
 #include <asm/cache.h>
-- 
cgit v1.2.3


From a90f354709b372c8dcabe3cd6315a83da5927573 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 3 Oct 2007 17:13:34 +0900
Subject: sh: kgdb section mismatches and tidying.

The kgdb console setup was callable from a left-over deferred
initialization path, which in turn depends on __init symbols. Since
the deferred initialization was removed some time ago, kill off the
rest of those remnants and move kgdb_init() and friends to __init.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/kgdb.h | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h
index 74bd0953e5c..5334e86ccad 100644
--- a/include/asm-sh/kgdb.h
+++ b/include/asm-sh/kgdb.h
@@ -19,8 +19,6 @@
 #include <asm/ptrace.h>
 #include <asm/cacheflush.h>
 
-struct console;
-
 /* Same as pt_regs but has vbr in place of syscall_nr */
 struct kgdb_regs {
         unsigned long regs[16];
@@ -35,10 +33,7 @@ struct kgdb_regs {
 
 /* State info */
 extern char kgdb_in_gdb_mode;
-extern int kgdb_done_init;
-extern int kgdb_enabled;
 extern int kgdb_nofault;	/* Ignore bus errors (in gdb mem access) */
-extern int kgdb_halt;		/* Execute initial breakpoint at startup */
 extern char in_nmi;		/* Debounce flag to prevent NMI reentry*/
 
 /* SCI */
@@ -59,6 +54,7 @@ extern kgdb_debug_hook_t  *kgdb_debug_hook;
 extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
 
 /* Console */
+struct console;
 void kgdb_console_write(struct console *co, const char *s, unsigned count);
 extern int kgdb_console_setup(struct console *, char *);
 
@@ -69,11 +65,7 @@ extern void    longjmp(jmp_buf __jmpb, int __retval);
 extern int     setjmp(jmp_buf __jmpb);
 
 /* Forced breakpoint */
-#define breakpoint()					\
-do {							\
-	if (kgdb_enabled)				\
-		__asm__ __volatile__("trapa   #0x3c");	\
-} while (0)
+#define breakpoint()	__asm__ __volatile__("trapa   #0x3c")
 
 /* KGDB should be able to flush all kernel text space */
 #if defined(CONFIG_CPU_SH4)
-- 
cgit v1.2.3


From 01bd5e9ef2ead97059a1930de43942bdfc9e8755 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 3 Oct 2007 17:21:10 +0900
Subject: sh: Make kgdb i-cache flushing less inept.

kgdb had its own ranged I-cache flushing routine that attempted to
duplicate the flush_icache_range() functionality, but managed to do
an explicit D-cache writeback & invalidate twice on SH-4. This is
a no-op for SH-3, and the flush_icache_range() semantics already do
what kgdb was feebly attempting to do already, so just move over to
that and kill off the wrapper.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/kgdb.h | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'include')

diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h
index 5334e86ccad..4bc8cb187d1 100644
--- a/include/asm-sh/kgdb.h
+++ b/include/asm-sh/kgdb.h
@@ -17,7 +17,6 @@
 #define __KGDB_H
 
 #include <asm/ptrace.h>
-#include <asm/cacheflush.h>
 
 /* Same as pt_regs but has vbr in place of syscall_nr */
 struct kgdb_regs {
@@ -67,17 +66,6 @@ extern int     setjmp(jmp_buf __jmpb);
 /* Forced breakpoint */
 #define breakpoint()	__asm__ __volatile__("trapa   #0x3c")
 
-/* KGDB should be able to flush all kernel text space */
-#if defined(CONFIG_CPU_SH4)
-#define kgdb_flush_icache_range(start, end) \
-{									\
-	__flush_purge_region((void*)(start), (int)(end) - (int)(start));\
-	flush_icache_range((start), (end));				\
-}
-#else
-#define kgdb_flush_icache_range(start, end)	do { } while (0)
-#endif
-
 /* Taken from sh-stub.c of GDB 4.18 */
 static const char hexchars[] = "0123456789abcdef";
 
-- 
cgit v1.2.3


From 5d9df8eeacec943c9599f1cfd1069bc8cced3de6 Mon Sep 17 00:00:00 2001
From: Adrian McMenamin <adrian@mcmen.demon.co.uk>
Date: Mon, 8 Oct 2007 05:19:36 +0900
Subject: sh: Fix SH-4 DMAC CHCR masking.

This patch fixes the DMA cascade by masking the correct bits.

Tested and working with Dreamcast PVR2 DMA. With this patch applied
the existing mainline code in arch/sh/drivers/dma/dma-sh.c works,
whereas before I was patching that to get round this problem.

Signed-off-by: Adrian McMenamin <adrian@mcmen.demon.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 include/asm-sh/cpu-sh4/dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index 36e26a96476..aaf71b018c2 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -31,7 +31,7 @@
 #define TS_32		0x00000030
 #define TS_64		0x00000000
 
-#define CHCR_TS_MASK	0x30
+#define CHCR_TS_MASK	0x70
 #define CHCR_TS_SHIFT	4
 
 #define DMAOR_COD	0x00000008
-- 
cgit v1.2.3