From 962f480e0f9024ecdcfe2ba1d216c038ee328ced Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Wed, 19 Sep 2007 00:46:32 +0100 Subject: [MIPS] All MIPS32 processors support64-bit physical addresses. Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- include/asm-mips/pgtable-32.h | 4 ++-- include/asm-mips/pgtable-bits.h | 6 +++--- include/asm-mips/pgtable.h | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index ceefe027c76..4396e9ffd41 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp) pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t @@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __pgd_offset(address) pgd_index(address) #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 7494ba91112..d23f19a3240 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -32,7 +32,7 @@ * unpredictable things. The code (when it is written) to deal with * this problem will be in the update_mmu_cache() code for the r4k. */ -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define _PAGE_PRESENT (1<<6) /* implemented in software */ #define _PAGE_READ (1<<7) /* implemented in software */ @@ -122,7 +122,7 @@ #endif #endif -#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) @@ -139,7 +139,7 @@ #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW #endif -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) #else #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 17a7703a296..009b7b14231 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -79,7 +79,7 @@ extern void paging_init(void); #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) #define pmd_page_vaddr(pmd) pmd_val(pmd) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) @@ -182,7 +182,7 @@ extern pgd_t swapper_pg_dir[]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } @@ -309,7 +309,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte.pte_low &= _PAGE_CHG_MASK; -- cgit v1.2.3 From bec5052743ec8ae4c5669918cf9b130bf15709a2 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Wed, 19 Sep 2007 00:51:57 +0100 Subject: [MIPS] Tidy up cache attributes Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- include/asm-mips/pgtable-bits.h | 81 +++++++++++++++++++++-------------------- 1 file changed, 42 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index d23f19a3240..728fbe7b994 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -39,7 +39,7 @@ #define _PAGE_WRITE (1<<8) /* implemented in software */ #define _PAGE_ACCESSED (1<<9) /* implemented in software */ #define _PAGE_MODIFIED (1<<10) /* implemented in software */ -#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ +#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ #define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<0) @@ -47,15 +47,9 @@ #define _PAGE_SILENT_READ (1<<1) /* synonym */ #define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1<<2) +#define _CACHE_SHIFT 3 #define _CACHE_MASK (7<<3) -/* MIPS32 defines only values 2 and 3. The rest are implementation - * dependent. - */ -#define _CACHE_UNCACHED (2<<3) -#define _CACHE_CACHABLE_NONCOHERENT (3<<3) -#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */ - #else #define _PAGE_PRESENT (1<<0) /* implemented in software */ @@ -74,55 +68,66 @@ #define _PAGE_SILENT_WRITE (1<<10) #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) -#define _CACHE_CACHABLE_NONCOHERENT 0 #else + #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<6) #define _PAGE_VALID (1<<7) #define _PAGE_SILENT_READ (1<<7) /* synonym */ #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1<<8) +#define _CACHE_SHIFT 9 #define _CACHE_MASK (7<<9) -#ifdef CONFIG_CPU_SB1 +#endif +#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ + + +/* + * Cache attributes + */ +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +#define _CACHE_CACHABLE_NONCOHERENT 0 + +#elif defined(CONFIG_CPU_SB1) /* No penalty for being coherent on the SB1, so just use it for "noncoherent" spaces, too. Shouldn't hurt. */ -#define _CACHE_UNCACHED (2<<9) -#define _CACHE_CACHABLE_COW (5<<9) -#define _CACHE_CACHABLE_NONCOHERENT (5<<9) -#define _CACHE_UNCACHED_ACCELERATED (7<<9) +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) #elif defined(CONFIG_CPU_RM9000) -#define _CACHE_WT (0 << 9) -#define _CACHE_WTWA (1 << 9) -#define _CACHE_UC_B (2 << 9) -#define _CACHE_WB (3 << 9) -#define _CACHE_CWBEA (4 << 9) -#define _CACHE_CWB (5 << 9) -#define _CACHE_UCNB (6 << 9) -#define _CACHE_FPC (7 << 9) +#define _CACHE_WT (0<<_CACHE_SHIFT) +#define _CACHE_WTWA (1<<_CACHE_SHIFT) +#define _CACHE_UC_B (2<<_CACHE_SHIFT) +#define _CACHE_WB (3<<_CACHE_SHIFT) +#define _CACHE_CWBEA (4<<_CACHE_SHIFT) +#define _CACHE_CWB (5<<_CACHE_SHIFT) +#define _CACHE_UCNB (6<<_CACHE_SHIFT) +#define _CACHE_FPC (7<<_CACHE_SHIFT) -#define _CACHE_UNCACHED _CACHE_UC_B -#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB +#define _CACHE_UNCACHED _CACHE_UC_B +#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB #else -#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ -#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ #endif -#endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) @@ -135,14 +140,12 @@ #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT #elif defined(CONFIG_CPU_RM9000) #define PAGE_CACHABLE_DEFAULT _CACHE_CWB +#elif defined(CONFIG_SOC_AU1X00) +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT #else #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW #endif -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) -#else -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) -#endif +#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ -- cgit v1.2.3 From 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Wed, 19 Sep 2007 00:58:24 +0100 Subject: [MIPS] Allow setting of the cache attribute at run time. Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/io.h | 2 +- include/asm-mips/pgtable-bits.h | 12 ---------- include/asm-mips/pgtable.h | 51 +++++++++++++++++++++++------------------ 3 files changed, 30 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e62058b0d28..f18d2816cbe 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -273,7 +273,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * memory-like regions on I/O busses. */ #define ioremap_cachable(offset, size) \ - __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) + __ioremap_mode((offset), (size), _page_cachable_default) /* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 728fbe7b994..60e2f9338fc 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -134,18 +134,6 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif defined(CONFIG_DMA_NONCOHERENT) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#elif defined(CONFIG_CPU_RM9000) -#define PAGE_CACHABLE_DEFAULT _CACHE_CWB -#elif defined(CONFIG_SOC_AU1X00) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#else -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif - #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 009b7b14231..582f56f42f0 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -23,15 +23,15 @@ struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ - _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) + _PAGE_GLOBAL | _page_cachable_default) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -40,23 +40,30 @@ struct vm_area_struct; * read. Also, write permissions imply read permissions. This is the closest * we can get by reasonable means.. */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED + +/* + * Dummy values to fill the table in mmap.c + * The real values will be generated at runtime + */ +#define __P000 __pgprot(0) +#define __P001 __pgprot(0) +#define __P010 __pgprot(0) +#define __P011 __pgprot(0) +#define __P100 __pgprot(0) +#define __P101 __pgprot(0) +#define __P110 __pgprot(0) +#define __P111 __pgprot(0) + +#define __S000 __pgprot(0) +#define __S001 __pgprot(0) +#define __S010 __pgprot(0) +#define __S011 __pgprot(0) +#define __S100 __pgprot(0) +#define __S101 __pgprot(0) +#define __S110 __pgprot(0) +#define __S111 __pgprot(0) + +extern unsigned long _page_cachable_default; /* * ZERO_PAGE is a global shared page that is always zero; used -- cgit v1.2.3 From 308402445e005a039a72b315cd9b5ceeaea0063c Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 21 Sep 2007 14:50:08 +0100 Subject: [MIPS] Add CoreFPGA5 support; distinguish between SOCit/ROCit Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- include/asm-mips/mips-boards/generic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 1c39d339521..33407bee4e7 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -68,6 +68,7 @@ #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 #define MIPS_REVISION_CORID_CORE_FPGA4 11 +#define MIPS_REVISION_CORID_CORE_FPGA5 12 /**** Artificial corid defines ****/ /* -- cgit v1.2.3 From 39b8d5254246ac56342b72f812255c8f7a74dca9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 28 Apr 2008 17:14:26 +0100 Subject: [MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/cmp.h | 18 ++ include/asm-mips/cpu.h | 7 +- include/asm-mips/gcmpregs.h | 117 ++++++++ include/asm-mips/gic.h | 487 ++++++++++++++++++++++++++++++++ include/asm-mips/mips-boards/launch.h | 35 +++ include/asm-mips/mips-boards/malta.h | 23 ++ include/asm-mips/mips-boards/maltaint.h | 27 ++ include/asm-mips/mips-boards/maltasmp.h | 36 +++ include/asm-mips/mipsmtregs.h | 8 +- include/asm-mips/r4k-timer.h | 30 ++ include/asm-mips/smp-ops.h | 1 + include/asm-mips/smtc.h | 1 + include/asm-mips/smvp.h | 19 ++ 13 files changed, 802 insertions(+), 7 deletions(-) create mode 100644 include/asm-mips/cmp.h create mode 100644 include/asm-mips/gcmpregs.h create mode 100644 include/asm-mips/gic.h create mode 100644 include/asm-mips/mips-boards/launch.h create mode 100644 include/asm-mips/mips-boards/maltasmp.h create mode 100644 include/asm-mips/r4k-timer.h create mode 100644 include/asm-mips/smvp.h (limited to 'include') diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h new file mode 100644 index 00000000000..89a73fb93ae --- /dev/null +++ b/include/asm-mips/cmp.h @@ -0,0 +1,18 @@ +#ifndef _ASM_CMP_H +#define _ASM_CMP_H + +/* + * Definitions for CMP multitasking on MIPS cores + */ +struct task_struct; + +extern void cmp_smp_setup(void); +extern void cmp_smp_finish(void); +extern void cmp_boot_secondary(int cpu, struct task_struct *t); +extern void cmp_init_secondary(void); +extern void cmp_cpus_done(void); +extern void cmp_prepare_cpus(unsigned int max_cpus); + +/* This is platform specific */ +extern void cmp_send_ipi(int cpu, unsigned int action); +#endif /* _ASM_CMP_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index bf5bbc78a9f..6d04ea91225 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,7 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_1004K 0x9900 #define PRID_IMP_LOONGSON1 0x4200 #define PRID_IMP_LOONGSON2 0x6300 @@ -194,9 +195,9 @@ enum cpu_type_enum { /* * MIPS32 class processors */ - CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, - CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550, - CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, + CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, + CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h new file mode 100644 index 00000000000..d74a8a4ca86 --- /dev/null +++ b/include/asm-mips/gcmpregs.h @@ -0,0 +1,117 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * + * Multiprocessor Subsystem Register Definitions + * + */ +#ifndef _ASM_GCMPREGS_H +#define _ASM_GCMPREGS_H + + +/* Offsets to major blocks within GCMP from GCMP base */ +#define GCMP_GCB_OFS 0x0000 /* Global Control Block */ +#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ +#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ +#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ + +/* Offsets to individual GCMP registers from GCMP base */ +#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) + +#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) +#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) +#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) +#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) + +/* GCMP register access */ +#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) +#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) +#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) +#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) + +/* Mask generation */ +#define GCMPMSK(block, reg, bits) (MSK(bits)< +#include + +/* malta_smtc */ +#include +#include + +/* malta_cmp */ +#include + +/* malta_smvp */ +#include diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 5a2f8a3a6a1..c9420aa97e3 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -197,8 +197,8 @@ static inline void __raw_evpe(void) " .set pop \n"); } -/* Enable multiMT if previous suggested it should be. - EMT_ENABLE to force */ +/* Enable virtual processor execution if previous suggested it should be. + EVPE_ENABLE to force */ #define EVPE_ENABLE MVPCONTROL_EVP @@ -238,8 +238,8 @@ static inline void __raw_emt(void) " .set reorder"); } -/* enable multiVPE if previous suggested it should be. - EVPE_ENABLE to force */ +/* enable multi-threaded execution if previous suggested it should be. + EMT_ENABLE to force */ #define EMT_ENABLE VPECONTROL_TE diff --git a/include/asm-mips/r4k-timer.h b/include/asm-mips/r4k-timer.h new file mode 100644 index 00000000000..a37d12b3b61 --- /dev/null +++ b/include/asm-mips/r4k-timer.h @@ -0,0 +1,30 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_R4K_TYPES_H +#define __ASM_R4K_TYPES_H + +#include + +#ifdef CONFIG_SYNC_R4K + +extern void synchronise_count_master(void); +extern void synchronise_count_slave(void); + +#else + +static inline void synchronise_count_master(void) +{ +} + +static inline void synchronise_count_slave(void) +{ +} + +#endif + +#endif /* __ASM_R4K_TYPES_H */ diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h index b17fdfb5d81..43c207e72a6 100644 --- a/include/asm-mips/smp-ops.h +++ b/include/asm-mips/smp-ops.h @@ -51,6 +51,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops) #endif /* !CONFIG_SMP */ extern struct plat_smp_ops up_smp_ops; +extern struct plat_smp_ops cmp_smp_ops; extern struct plat_smp_ops vsmp_smp_ops; #endif /* __ASM_SMP_OPS_H */ diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index ff3e8936b49..3639b28f80d 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h @@ -44,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot); extern void mipsmt_prepare_cpus(void); extern void smtc_smp_finish(void); extern void smtc_boot_secondary(int cpu, struct task_struct *t); +extern void smtc_cpus_done(void); /* * Sharing the TLB between multiple VPEs means that the diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h new file mode 100644 index 00000000000..0d0e80a39e8 --- /dev/null +++ b/include/asm-mips/smvp.h @@ -0,0 +1,19 @@ +#ifndef _ASM_SMVP_H +#define _ASM_SMVP_H + +/* + * Definitions for SMVP multitasking on MIPS MT cores + */ +struct task_struct; + +extern void smvp_smp_setup(void); +extern void smvp_smp_finish(void); +extern void smvp_boot_secondary(int cpu, struct task_struct *t); +extern void smvp_init_secondary(void); +extern void smvp_smp_finish(void); +extern void smvp_cpus_done(void); +extern void smvp_prepare_cpus(unsigned int max_cpus); + +/* This is platform specific */ +extern void smvp_send_ipi(int cpu, unsigned int action); +#endif /* _ASM_SMVP_H */ -- cgit v1.2.3 From a92b05880d261e9017ef8e7d5b6b01e0e5aa991d Mon Sep 17 00:00:00 2001 From: Daniel Laird Date: Thu, 6 Mar 2008 09:07:18 +0000 Subject: [MIPS] Move arch/mips/philips to arch/mips/nxp Signed-off-by: daniel.j.laird Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 6d04ea91225..1c35cac6f35 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -29,7 +29,7 @@ #define PRID_COMP_ALCHEMY 0x030000 #define PRID_COMP_SIBYTE 0x040000 #define PRID_COMP_SANDCRAFT 0x050000 -#define PRID_COMP_PHILIPS 0x060000 +#define PRID_COMP_NXP 0x060000 #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 -- cgit v1.2.3 From 0167509574ef1cdb516906db5e8b6ad5ca64ab61 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 24 Mar 2008 23:15:50 +0300 Subject: [MIPS] Alchemy: don't unmask timer IRQ early Defer the unmasking of the count/compare interrupt (IRQ5) till the clockevent driver initialization: - only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the ALLINTS macro -- this change is blessed by AMD as I saw it in their own patch; :-) - do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's no 32 KHz crystal. Update the copyrights (taking into account my prior changes), also removing Pete Popov's old email... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 5bb57bf2b9d..a88637a93e0 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -3,9 +3,8 @@ * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ -#ifdef CONFIG_PM -/* no CP0 timer irq */ -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - /* * SDRAM Register Offsets */ -- cgit v1.2.3 From 8aa62adafada6e3f29e12dacf1d6f491d2ba5f7f Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 5 Apr 2008 00:55:24 +0900 Subject: [MIPS] make fallback gpio.h gpiolib-friendly If gpiolib was selected, asm-generic/gpio.h provides some prototypes for gpio API and implementation helpers. With this patch, platform code can implement its GPIO API using gpiolib without custom gpio.h file. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/mach-generic/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h index 6eaf5efedf3..e6b376bd9d0 100644 --- a/include/asm-mips/mach-generic/gpio.h +++ b/include/asm-mips/mach-generic/gpio.h @@ -1,12 +1,18 @@ #ifndef __ASM_MACH_GENERIC_GPIO_H #define __ASM_MACH_GENERIC_GPIO_H +#ifdef CONFIG_HAVE_GPIO_LIB +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#else int gpio_request(unsigned gpio, const char *label); void gpio_free(unsigned gpio); int gpio_direction_input(unsigned gpio); int gpio_direction_output(unsigned gpio, int value); int gpio_get_value(unsigned gpio); void gpio_set_value(unsigned gpio, int value); +#endif int gpio_to_irq(unsigned gpio); int irq_to_gpio(unsigned irq); -- cgit v1.2.3 From a9aec7fe74cd912cad74ca621ed91cb1c37566ae Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 5 Apr 2008 00:55:41 +0900 Subject: [MIPS] generic txx9 gpio support This is a board-independent TXx9 gpio API implementation using gpiolib. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/txx9pio.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/asm-mips/txx9pio.h (limited to 'include') diff --git a/include/asm-mips/txx9pio.h b/include/asm-mips/txx9pio.h new file mode 100644 index 00000000000..3d6fa9f8d51 --- /dev/null +++ b/include/asm-mips/txx9pio.h @@ -0,0 +1,29 @@ +/* + * include/asm-mips/txx9pio.h + * TX39/TX49 PIO controller definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9PIO_H +#define __ASM_TXX9PIO_H + +#include + +struct txx9_pio_reg { + __u32 dout; + __u32 din; + __u32 dir; + __u32 od; + __u32 flag[2]; + __u32 pol; + __u32 intc; + __u32 maskcpu; + __u32 maskext; +}; + +int txx9_gpio_init(unsigned long baseaddr, + unsigned int base, unsigned int num); + +#endif /* __ASM_TXX9PIO_H */ -- cgit v1.2.3 From 4cad154b30e7471628cb1943081c72b6368b079a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 5 Apr 2008 00:56:09 +0900 Subject: [MIPS] rbhma4500: use generic txx9 gpio Use generic txx9 gpio (and gpiolib) for RBHMA4500 board. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/tx4938/tx4938.h | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'include') diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index f7c448b9057..a05f031cfdf 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -261,18 +261,6 @@ struct tx4938_sio_reg { volatile unsigned long rfifo; }; -struct tx4938_pio_reg { - volatile unsigned long dout; - volatile unsigned long din; - volatile unsigned long dir; - volatile unsigned long od; - volatile unsigned long flag[2]; - volatile unsigned long pol; - volatile unsigned long intc; - volatile unsigned long maskcpu; - volatile unsigned long maskext; -}; - struct tx4938_ndfmc_reg { endian_def_l2(unused0, dtr); endian_def_l2(unused1, mcr); @@ -642,7 +630,7 @@ struct tx4938_ccfg_reg { #define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) #define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) #define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) -#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) +#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) #define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) #define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) #define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) -- cgit v1.2.3 From 1bd0962e3d5bc66ee0ee207a61485c6a436cfac2 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 5 Apr 2008 00:56:27 +0900 Subject: [MIPS] jmr3927: use generic txx9 gpio Use generic txx9 gpio (and gpiolib) for JMR3927 board. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/jmr3927/jmr3927.h | 4 ++-- include/asm-mips/jmr3927/tx3927.h | 2 +- include/asm-mips/jmr3927/txx927.h | 12 ------------ 3 files changed, 3 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h index 81602c8047e..a162268f17d 100644 --- a/include/asm-mips/jmr3927/jmr3927.h +++ b/include/asm-mips/jmr3927/jmr3927.h @@ -99,8 +99,8 @@ #define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) /* DIPSW4 macro */ -#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0) -#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) +#define jmr3927_dipsw1() (gpio_get_value(11) == 0) +#define jmr3927_dipsw2() (gpio_get_value(10) == 0) #define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) #define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 338f99882a3..fb580333c10 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -314,6 +314,6 @@ struct tx3927_ccfg_reg { #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) #define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) +#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) #endif /* __ASM_TX3927_H */ diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h index 0474fe8dac3..25dcf2feb09 100644 --- a/include/asm-mips/jmr3927/txx927.h +++ b/include/asm-mips/jmr3927/txx927.h @@ -22,18 +22,6 @@ struct txx927_sio_reg { volatile unsigned long rfifo; }; -struct txx927_pio_reg { - volatile unsigned long dout; - volatile unsigned long din; - volatile unsigned long dir; - volatile unsigned long od; - volatile unsigned long flag[2]; - volatile unsigned long pol; - volatile unsigned long intc; - volatile unsigned long maskcpu; - volatile unsigned long maskext; -}; - /* * SIO */ -- cgit v1.2.3 From 66140c8e9f0d978bd26c58f236d0d86aa666d8fc Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 14 Apr 2008 21:49:07 +0900 Subject: [MIPS] rbtx4938: misc cleanups * Do not use non-standard I/O accessors, such as reg_rd08, etc. * Kill unnecessary wbflush() * Kill tx4938_mips.h * Kill unnecessary includes Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/tx4938/rbtx4938.h | 58 ++++++++++++----------------------- include/asm-mips/tx4938/tx4938.h | 24 --------------- include/asm-mips/tx4938/tx4938_mips.h | 54 -------------------------------- 3 files changed, 20 insertions(+), 116 deletions(-) delete mode 100644 include/asm-mips/tx4938/tx4938_mips.h (limited to 'include') diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index b180488dcdc..dfed7beb533 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -67,44 +67,26 @@ #define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) #define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) -#define rbtx4938_fpga_rev_ptr \ - ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_ptr \ - ((volatile unsigned char *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_ptr \ - ((volatile unsigned char *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_ptr \ - ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_ptr \ - ((volatile unsigned char *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_ptr \ - ((volatile unsigned char *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_ptr \ - ((volatile unsigned char *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_ptr \ - ((volatile unsigned char *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_ptr \ - ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_ptr \ - ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_ptr \ - ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_ptr \ - ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_ptr \ - ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_ptr \ - ((volatile unsigned char *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_ptr \ - ((volatile unsigned char *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_ptr \ - ((volatile unsigned char *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_ptr \ - ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_ptr \ - ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_ptr \ - ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) +#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_addr \ + ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) /* * IRQ mappings diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index a05f031cfdf..e8807f5c61e 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -13,8 +13,6 @@ #ifndef __ASM_TX_BOARDS_TX4938_H #define __ASM_TX_BOARDS_TX4938_H -#include - #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) @@ -54,28 +52,6 @@ #define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) #define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) -#ifndef _LANGUAGE_ASSEMBLY -#include - -#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) )) - -#define TX4938_RD08( reg ) (*(vu08*)(reg)) -#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val)) - -#define TX4938_RD16( reg ) (*(vu16*)(reg)) -#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val)) - -#define TX4938_RD32( reg ) (*(vu32*)(reg)) -#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val)) - -#define TX4938_RD64( reg ) (*(vu64*)(reg)) -#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val)) - -#define TX4938_RD( reg ) TX4938_RD32( reg ) -#define TX4938_WR( reg, val ) TX4938_WR32( reg, val ) - -#endif /* !__ASSEMBLY__ */ - #ifdef __ASSEMBLY__ #define _CONST64(c) c #else diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h deleted file mode 100644 index f346ff58b94..00000000000 --- a/include/asm-mips/tx4938/tx4938_mips.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/tx4938_mips.h - * Generic bitmask definitions - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#ifndef TX4938_TX4938_MIPS_H -#define TX4938_TX4938_MIPS_H -#ifndef __ASSEMBLY__ - -#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) -#define reg_rd16(r) ((u16)(*((vu16*)(r)))) -#define reg_rd32(r) ((u32)(*((vu32*)(r)))) -#define reg_rd64(r) ((u64)(*((vu64*)(r)))) - -#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v))) - -typedef volatile __signed char vs8; -typedef volatile unsigned char vu8; - -typedef volatile __signed short vs16; -typedef volatile unsigned short vu16; - -typedef volatile __signed int vs32; -typedef volatile unsigned int vu32; - -typedef s8 s08; -typedef vs8 vs08; - -typedef u8 u08; -typedef vu8 vu08; - -#if (_MIPS_SZLONG == 64) - -typedef volatile __signed__ long vs64; -typedef volatile unsigned long vu64; - -#else - -typedef volatile __signed__ long long vs64; -typedef volatile unsigned long long vu64; - -#endif -#endif -#endif -- cgit v1.2.3 From 6ed436932d1417534aa1a738fd9585795f954304 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 22 Apr 2008 23:28:57 +0400 Subject: [MIPS] Alchemy: kill unused PCI_IRQ_TABLE_LOOKUP macro Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index a88637a93e0..a05555165d0 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1685,20 +1685,6 @@ enum soc_au1200_ints { #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff - /* - * Borrowed from the PPC arch: - * The following macro is used to lookup irqs in a standard table - * format for those PPC systems that do not already have PCI - * interrupts properly routed. - */ - /* FIXME - double check this from asm-ppc/pci-bridge.h */ -#define PCI_IRQ_TABLE_LOOKUP \ - ({ long _ctl_ = -1; \ - if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ - _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ - _ctl_; }) - - #else /* Au1000 and Au1100 and Au1200 */ /* don't allow any legacy ports probing */ -- cgit v1.2.3 From 4247417d8457b326ede001cb74af8570b5aa302b Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Thu, 24 Apr 2008 09:48:40 +0900 Subject: [MIPS] add DECstation I/O ASIC clocksource Add DECstation I/O ASIC clocksource Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- include/asm-mips/dec/ioasic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h index 486a5b0a130..98badd6bf22 100644 --- a/include/asm-mips/dec/ioasic.h +++ b/include/asm-mips/dec/ioasic.h @@ -33,4 +33,6 @@ static inline u32 ioasic_read(unsigned int reg) extern void init_ioasic_irqs(int base); +extern void dec_ioasic_clocksource_init(void); + #endif /* __ASM_DEC_IOASIC_H */ -- cgit v1.2.3 From 6457d9fc3bb87c72db03cfb34cd414c8fb9b8edf Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 25 Apr 2008 12:11:44 +0900 Subject: [MIPS] DS1287: Add clockevent driver Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- include/asm-mips/ds1287.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 include/asm-mips/ds1287.h (limited to 'include') diff --git a/include/asm-mips/ds1287.h b/include/asm-mips/ds1287.h new file mode 100644 index 00000000000..ba1702e8693 --- /dev/null +++ b/include/asm-mips/ds1287.h @@ -0,0 +1,27 @@ +/* + * DS1287 timer functions. + * + * Copyright (C) 2008 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_DS1287_H +#define __ASM_DS1287_H + +extern int ds1287_timer_state(void); +extern void ds1287_set_base_clock(unsigned int clock); +extern int ds1287_clockevent_init(int irq); + +#endif -- cgit v1.2.3 From 411ba7fcba54b30ba4ce2c492ea8d20f1d0db996 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 26 Apr 2008 01:55:30 +0900 Subject: [MIPS] Fix some sparse warnings on traps.c and irq-msc01.c * Declare board_bind_eic_interrupt, board_watchpoint_handler in traps.h * Make msc_bind_eic_interrupt static and fix its argument types. * Make msc_levelirq_type, msc_edgeirq_type static. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/traps.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index d02e019b012..e5dbde625ec 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -23,5 +23,7 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); +extern void (*board_bind_eic_interrupt)(int irq, int regset); +extern void (*board_watchpoint_handler)(struct pt_regs *regs); #endif /* _ASM_TRAPS_H */ -- cgit v1.2.3 From a4a8f70d2db2998cf28532287ee89776d4d8a2ca Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Wed, 23 Apr 2008 18:55:59 +0300 Subject: [MIPS] IP27: Fix build bug due to missing include asm-mips/mach-ip27/topology.h must #include This fixes the following compile error: ... CC kernel/sched.o /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c: In function 'find_next_best_node': /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7015: error: implicit declaration of function 'node_to_cpumask_ptr' /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7015: error: '__tmp__' undeclared (first use in this function) /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7015: error: (Each undeclared identifier is reported only once /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7015: error: for each function it appears in.) /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c: In function 'sched_domain_node_span': /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7047: error: 'nodemask' undeclared (first use in this function) /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7048: warning: ISO C90 forbids mixed declarations and code /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7059: error: implicit declaration of function 'node_to_cpumask_ptr_next' /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c: In function '__build_sched_domains': /home/bunk/linux/kernel-2.6/git/linux-2.6/kernel/sched.c:7605: error: 'pnodemask' undeclared (first use in this function) make[2]: *** [kernel/sched.o] Error 1 <-- snip --> Signed-off-by: Adrian Bunk Signed-off-by: Ralf Baechle --- include/asm-mips/mach-ip27/topology.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h index 372291f53fb..7785bec732f 100644 --- a/include/asm-mips/mach-ip27/topology.h +++ b/include/asm-mips/mach-ip27/topology.h @@ -54,4 +54,6 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; .nr_balance_failed = 0, \ } +#include + #endif /* _ASM_MACH_TOPOLOGY_H */ -- cgit v1.2.3 From fcbd3b4b92efe29b59df16b910138cf43683be88 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 28 Apr 2008 19:54:38 +0400 Subject: [MIPS] Pb1200/DBAu1200: move platform code to its proper place Since both the IDE interface and SMC 91C111 Ethernet chip are on-board devices, not SOC devices, move the platform device registration form the common to the board specific code. While at it, remove semicolon (which didn't break compilation only by chance) from the AU1XXX_ATA_DDMA_REQ macro and do some renaming: - change 'au1200_ide0_' variable name prefix to the mere 'ide_'; - change 'smc91x_' variable name prefix to 'smc91c111_' since that's the name of the chip used on the boards; - drop 'AU1XXX_' prefix from the names of macros describing IDE and Ethernet on-board devices; - change 'SMC91111_' to 'SMC91C111_', change 'IRQ' to 'INT' in the names of the macros describing the Ethernet chip for consistency with the IDE macros; - change 'ATA_' to 'IDE_' and 'OFFSET' to 'SHIFT' (since this value is indeed a shift count) in the names of the macros describing the IDE interface. Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-db1x00/db1200.h | 18 +++++++++--------- include/asm-mips/mach-pb1x00/pb1200.h | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h index d2e28e64932..eedd048a726 100644 --- a/include/asm-mips/mach-db1x00/db1200.h +++ b/include/asm-mips/mach-db1x00/db1200.h @@ -169,15 +169,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 -#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) -#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT - -#define AU1XXX_ATA_PHYS_ADDR (0x18800000) -#define AU1XXX_ATA_REG_OFFSET (5) -#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET) -#define AU1XXX_ATA_INT DB1200_IDE_INT -#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; -#define AU1XXX_ATA_RQSIZE 128 +#define SMC91C111_PHYS_ADDR 0x19000300 +#define SMC91C111_INT DB1200_ETH_INT + +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) +#define IDE_INT DB1200_IDE_INT +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x20000000 diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h index edaa489b58f..e2c6bcac3b4 100644 --- a/include/asm-mips/mach-pb1x00/pb1200.h +++ b/include/asm-mips/mach-pb1x00/pb1200.h @@ -182,15 +182,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define SET_VCC_VPP(VCC, VPP, SLOT)\ ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) -#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300) -#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT - -#define AU1XXX_ATA_PHYS_ADDR (0x0C800000) -#define AU1XXX_ATA_REG_OFFSET (5) -#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET) -#define AU1XXX_ATA_INT PB1200_IDE_INT -#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; -#define AU1XXX_ATA_RQSIZE 128 +#define SMC91C111_PHYS_ADDR 0x0D000300 +#define SMC91C111_INT PB1200_ETH_INT + +#define IDE_PHYS_ADDR 0x0C800000 +#define IDE_REG_SHIFT 5 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) +#define IDE_INT PB1200_IDE_INT +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 #define NAND_PHYS_ADDR 0x1C000000 -- cgit v1.2.3