From 05faa7b758e4f23b66c5a776a338f2348cbbc4af Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 11 Jan 2006 18:23:00 +0000 Subject: [MIPS] Fix C version of ssnop to use the right opcode. Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 2fc90632f88..6111a0ce58c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -100,7 +100,7 @@ __asm__( " .macro _ssnop \n\t" - " sll $0, $2, 1 \n\t" + " sll $0, $0, 1 \n\t" " .endm \n\t" " \n\t" " .macro _ehb \n\t" -- cgit v1.2.3 From fcdb27ad1d5c66611d3df6400a9b559186f266fe Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 18 Jan 2006 17:37:07 +0000 Subject: [MIPS] Rename _machine_power_off to pm_power_off so the kernel builds again. Signed-off-by: Ralf Baechle --- include/asm-mips/reboot.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h index 2f10ebcbe14..e48c0bfab25 100644 --- a/include/asm-mips/reboot.h +++ b/include/asm-mips/reboot.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef _ASM_REBOOT_H @@ -11,6 +11,5 @@ extern void (*_machine_restart)(char *command); extern void (*_machine_halt)(void); -extern void (*_machine_power_off)(void); #endif /* _ASM_REBOOT_H */ -- cgit v1.2.3 From 11ed6d5bb01c5f347fd5c47e0005f06687c66f1f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 18 Jan 2006 23:26:43 +0000 Subject: [MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt. Signed-off-by: Ralf Baechle --- include/asm-mips/cobalt/cobalt.h | 116 ---------------------------- include/asm-mips/cobalt/mach-gt64120.h | 1 - include/asm-mips/mach-cobalt/cobalt.h | 116 ++++++++++++++++++++++++++++ include/asm-mips/mach-cobalt/mach-gt64120.h | 1 + 4 files changed, 117 insertions(+), 117 deletions(-) delete mode 100644 include/asm-mips/cobalt/cobalt.h delete mode 100644 include/asm-mips/cobalt/mach-gt64120.h create mode 100644 include/asm-mips/mach-cobalt/cobalt.h create mode 100644 include/asm-mips/mach-cobalt/mach-gt64120.h (limited to 'include') diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h deleted file mode 100644 index 78e1df2095f..00000000000 --- a/include/asm-mips/cobalt/cobalt.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Lowlevel hardware stuff for the MIPS based Cobalt microservers. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 Cobalt Microserver - * Copyright (C) 1997, 2003 Ralf Baechle - * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) - */ -#ifndef __ASM_COBALT_H -#define __ASM_COBALT_H - -/* - * i8259 legacy interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ -#define COBALT_QUBE_SLOT_IRQ 9 - -/* - * CPU IRQs are 16 ... 23 - */ -#define COBALT_CPU_IRQ 16 - -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ - -/* - * PCI configuration space manifest constants. These are wired into - * the board layout according to the PCI spec to enable the software - * to probe the hardware configuration space in a well defined manner. - * - * The PCI_DEVSHFT() macro transforms these values into numbers - * suitable for passing as the dev parameter to the various - * pcibios_read/write_config routines. - */ -#define COBALT_PCICONF_CPU 0x06 -#define COBALT_PCICONF_ETH0 0x07 -#define COBALT_PCICONF_RAQSCSI 0x08 -#define COBALT_PCICONF_VIA 0x09 -#define COBALT_PCICONF_PCISLOT 0x0A -#define COBALT_PCICONF_ETH1 0x0C - - -/* - * The Cobalt board id information. The boards have an ID number wired - * into the VIA that is available in the high nibble of register 94. - * This register is available in the VIA configuration space through the - * interface routines qube_pcibios_read/write_config. See cobalt/pci.c - */ -#define VIA_COBALT_BRD_ID_REG 0x94 -#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) -#define COBALT_BRD_ID_QUBE1 0x3 -#define COBALT_BRD_ID_RAQ1 0x4 -#define COBALT_BRD_ID_QUBE2 0x5 -#define COBALT_BRD_ID_RAQ2 0x6 - -/* - * Galileo chipset access macros for the Cobalt. The base address for - * the GT64111 chip is 0x14000000 - * - * Most of this really should go into a separate GT64111 header file. - */ -#define GT64111_IO_BASE 0x10000000UL -#define GT64111_IO_END 0x11ffffffUL -#define GT64111_MEM_BASE 0x12000000UL -#define GT64111_MEM_END 0x13ffffffUL -#define GT64111_BASE 0x14000000UL -#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs)) - -#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) -#define GALILEO_OUTL(val, port) \ -do { \ - *(volatile unsigned int *) GALILEO_REG(port) = (val); \ -} while (0) - -#define GALILEO_INTR_T0EXP (1 << 8) -#define GALILEO_INTR_RETRY_CTR (1 << 20) - -#define GALILEO_ENTC0 0x01 -#define GALILEO_SELTC0 0x02 - -#define PCI_CFG_SET(devfn,where) \ - GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ - (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) - -#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) -# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ -# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ -# define COBALT_LED_WEB (1 << 2) /* RaQ */ -# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ -# define COBALT_LED_RESET 0x0f - -#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) -# define COBALT_KEY_CLEAR (1 << 1) -# define COBALT_KEY_LEFT (1 << 2) -# define COBALT_KEY_UP (1 << 3) -# define COBALT_KEY_DOWN (1 << 4) -# define COBALT_KEY_RIGHT (1 << 5) -# define COBALT_KEY_ENTER (1 << 6) -# define COBALT_KEY_SELECT (1 << 7) -# define COBALT_KEY_MASK 0xfe - -#endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/cobalt/mach-gt64120.h deleted file mode 100644 index 587fc4378f4..00000000000 --- a/include/asm-mips/cobalt/mach-gt64120.h +++ /dev/null @@ -1 +0,0 @@ -/* there's something here ... in the dark */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h new file mode 100644 index 00000000000..78e1df2095f --- /dev/null +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -0,0 +1,116 @@ +/* + * Lowlevel hardware stuff for the MIPS based Cobalt microservers. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Cobalt Microserver + * Copyright (C) 1997, 2003 Ralf Baechle + * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) + */ +#ifndef __ASM_COBALT_H +#define __ASM_COBALT_H + +/* + * i8259 legacy interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI + * 14 - IDE0 + * 15 - IDE1 + */ +#define COBALT_QUBE_SLOT_IRQ 9 + +/* + * CPU IRQs are 16 ... 23 + */ +#define COBALT_CPU_IRQ 16 + +#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) +#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ +#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) +#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) +#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) +#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ + +/* + * PCI configuration space manifest constants. These are wired into + * the board layout according to the PCI spec to enable the software + * to probe the hardware configuration space in a well defined manner. + * + * The PCI_DEVSHFT() macro transforms these values into numbers + * suitable for passing as the dev parameter to the various + * pcibios_read/write_config routines. + */ +#define COBALT_PCICONF_CPU 0x06 +#define COBALT_PCICONF_ETH0 0x07 +#define COBALT_PCICONF_RAQSCSI 0x08 +#define COBALT_PCICONF_VIA 0x09 +#define COBALT_PCICONF_PCISLOT 0x0A +#define COBALT_PCICONF_ETH1 0x0C + + +/* + * The Cobalt board id information. The boards have an ID number wired + * into the VIA that is available in the high nibble of register 94. + * This register is available in the VIA configuration space through the + * interface routines qube_pcibios_read/write_config. See cobalt/pci.c + */ +#define VIA_COBALT_BRD_ID_REG 0x94 +#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) +#define COBALT_BRD_ID_QUBE1 0x3 +#define COBALT_BRD_ID_RAQ1 0x4 +#define COBALT_BRD_ID_QUBE2 0x5 +#define COBALT_BRD_ID_RAQ2 0x6 + +/* + * Galileo chipset access macros for the Cobalt. The base address for + * the GT64111 chip is 0x14000000 + * + * Most of this really should go into a separate GT64111 header file. + */ +#define GT64111_IO_BASE 0x10000000UL +#define GT64111_IO_END 0x11ffffffUL +#define GT64111_MEM_BASE 0x12000000UL +#define GT64111_MEM_END 0x13ffffffUL +#define GT64111_BASE 0x14000000UL +#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs)) + +#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) +#define GALILEO_OUTL(val, port) \ +do { \ + *(volatile unsigned int *) GALILEO_REG(port) = (val); \ +} while (0) + +#define GALILEO_INTR_T0EXP (1 << 8) +#define GALILEO_INTR_RETRY_CTR (1 << 20) + +#define GALILEO_ENTC0 0x01 +#define GALILEO_SELTC0 0x02 + +#define PCI_CFG_SET(devfn,where) \ + GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ + (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) + +#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) +# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ +# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ +# define COBALT_LED_WEB (1 << 2) /* RaQ */ +# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ +# define COBALT_LED_RESET 0x0f + +#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) +# define COBALT_KEY_CLEAR (1 << 1) +# define COBALT_KEY_LEFT (1 << 2) +# define COBALT_KEY_UP (1 << 3) +# define COBALT_KEY_DOWN (1 << 4) +# define COBALT_KEY_RIGHT (1 << 5) +# define COBALT_KEY_ENTER (1 << 6) +# define COBALT_KEY_SELECT (1 << 7) +# define COBALT_KEY_MASK 0xfe + +#endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h new file mode 100644 index 00000000000..587fc4378f4 --- /dev/null +++ b/include/asm-mips/mach-cobalt/mach-gt64120.h @@ -0,0 +1 @@ +/* there's something here ... in the dark */ -- cgit v1.2.3 From c011db451bcce468a6f999949fbdbc2fec1167d2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 19 Jan 2006 00:49:32 +0000 Subject: [MIPS] CPU definitions for Cobalt. Signed-off-by: Ralf Baechle --- .../asm-mips/mach-cobalt/cpu-feature-overrides.h | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 include/asm-mips/mach-cobalt/cpu-feature-overrides.h (limited to 'include') diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h new file mode 100644 index 00000000000..ace8c5ef970 --- /dev/null +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H +#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H + +#include + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 +#define cpu_has_watch 0 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_subset_pcaches 0 +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 0 + +#ifdef CONFIG_64BIT +#define cpu_has_llsc 0 +#else +#define cpu_has_llsc 1 +#endif + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_icache_snoops_remote_store 0 +#define cpu_has_dsp 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ -- cgit v1.2.3 From dd2f18fe5af54ea8928f175d3bff9401a0fb6b83 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 19 Jan 2006 14:55:42 +0000 Subject: [MIPS] Nevada support for SGI O2. Signed-off-by: Ralf Baechle --- include/asm-mips/mach-ip32/cpu-feature-overrides.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index b80c30725cf..36070b5654a 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -18,7 +18,7 @@ * so, for 64bit IP32 kernel we just don't use ll/sc. * This does not affect luserland. */ -#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT) +#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT) #define cpu_has_llsc 0 #else #define cpu_has_llsc 1 -- cgit v1.2.3 From 4feb8f8f4589d1cb1594e344c9672ec40f627ab4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 23 Jan 2006 16:15:30 +0000 Subject: [MIPS] Bullet proof uaccess.h against 4.0.1 miss-compilation. Signed-off-by: Ralf Baechle --- include/asm-mips/uaccess.h | 71 +++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 41bb96bb212..91d813a3782 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -202,49 +202,49 @@ struct __large_struct { unsigned long buf[100]; }; * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ -#ifdef __mips64 -#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr) -#else -#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr) +#ifdef CONFIG_32BIT +#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr) +#endif +#ifdef CONFIG_64BIT +#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr) #endif -#define __get_user_nocheck(x,ptr,size) \ -({ \ - __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \ - long __gu_err = 0; \ - \ +extern void __get_user_unknown(void); + +#define __get_user_common(val, size, ptr) \ +do { \ switch (size) { \ - case 1: __get_user_asm("lb", ptr); break; \ - case 2: __get_user_asm("lh", ptr); break; \ - case 4: __get_user_asm("lw", ptr); break; \ - case 8: __GET_USER_DW(ptr); break; \ + case 1: __get_user_asm(val, "lb", ptr); break; \ + case 2: __get_user_asm(val, "lh", ptr); break; \ + case 4: __get_user_asm(val, "lw", ptr); break; \ + case 8: __GET_USER_DW(val, ptr); break; \ default: __get_user_unknown(); break; \ } \ - (x) = (__typeof__(*(ptr))) __gu_val; \ +} while (0) + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err; \ + \ + __get_user_common((x), size, ptr); \ __gu_err; \ }) #define __get_user_check(x,ptr,size) \ ({ \ - const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \ - __typeof__(*(ptr)) __gu_val = 0; \ long __gu_err = -EFAULT; \ + const void __user * __gu_ptr = (ptr); \ + \ + if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ + __get_user_common((x), size, __gu_ptr); \ \ - if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \ - switch (size) { \ - case 1: __get_user_asm("lb", __gu_addr); break; \ - case 2: __get_user_asm("lh", __gu_addr); break; \ - case 4: __get_user_asm("lw", __gu_addr); break; \ - case 8: __GET_USER_DW(__gu_addr); break; \ - default: __get_user_unknown(); break; \ - } \ - } \ - (x) = (__typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) -#define __get_user_asm(insn, addr) \ +#define __get_user_asm(val, insn, addr) \ { \ + long __gu_tmp; \ + \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ @@ -255,14 +255,16 @@ struct __large_struct { unsigned long buf[100]; }; " .section __ex_table,\"a\" \n" \ " "__UA_ADDR "\t1b, 3b \n" \ " .previous \n" \ - : "=r" (__gu_err), "=r" (__gu_val) \ + : "=r" (__gu_err), "=r" (__gu_tmp) \ : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ + \ + (val) = (__typeof__(val)) __gu_tmp; \ } /* * Get a long long 64 using 32 bit registers. */ -#define __get_user_asm_ll32(addr) \ +#define __get_user_asm_ll32(val, addr) \ { \ __asm__ __volatile__( \ "1: lw %1, (%3) \n" \ @@ -278,21 +280,20 @@ struct __large_struct { unsigned long buf[100]; }; " " __UA_ADDR " 1b, 4b \n" \ " " __UA_ADDR " 2b, 4b \n" \ " .previous \n" \ - : "=r" (__gu_err), "=&r" (__gu_val) \ + : "=r" (__gu_err), "=&r" (val) \ : "0" (0), "r" (addr), "i" (-EFAULT)); \ } -extern void __get_user_unknown(void); - /* * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ -#ifdef __mips64 -#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) -#else +#ifdef CONFIG_32BIT #define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) #endif +#ifdef CONFIG_64BIT +#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) +#endif #define __put_user_nocheck(x,ptr,size) \ ({ \ -- cgit v1.2.3 From 6fe2a5681fff0cbeaf9a2d3778661be62a7f2f06 Mon Sep 17 00:00:00 2001 From: Sergei Shtylylov Date: Wed, 25 Jan 2006 21:24:57 +0300 Subject: [MIPS] TX49x7: Fix timer register #define's Fix the #define's for TX4927/37 timer reg's to match the datasheets (those Signed-off-by: Konstantin Baydarov Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/tx4927/tx4927.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 3bb7f0087d6..de85bd2245f 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -2,7 +2,7 @@ * Author: MontaVista Software, Inc. * source@mvista.com * - * Copyright 2001-2002 MontaVista Software Inc. + * Copyright 2001-2006 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -30,10 +30,10 @@ #include /* - This register naming came from the intergrate cpu/controoler name TX4927 + This register naming came from the integrated CPU/controller name TX4927 followed by the device name from table 4.2.2 on page 4-3 and then followed by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". + used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". */ #define TX4927_SIO_0_BASE @@ -251,8 +251,8 @@ /* TX4927 Timer 0 (32-bit registers) */ #define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf004 -#define TX4927_TMR0_TMTISR0 0xf008 +#define TX4927_TMR0_TMTCR0 0xf000 +#define TX4927_TMR0_TMTISR0 0xf004 #define TX4927_TMR0_TMCPRA0 0xf008 #define TX4927_TMR0_TMCPRB0 0xf00c #define TX4927_TMR0_TMITMR0 0xf010 @@ -264,8 +264,8 @@ /* TX4927 Timer 1 (32-bit registers) */ #define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf104 -#define TX4927_TMR1_TMTISR1 0xf108 +#define TX4927_TMR1_TMTCR1 0xf100 +#define TX4927_TMR1_TMTISR1 0xf104 #define TX4927_TMR1_TMCPRA1 0xf108 #define TX4927_TMR1_TMCPRB1 0xf10c #define TX4927_TMR1_TMITMR1 0xf110 @@ -277,13 +277,12 @@ /* TX4927 Timer 2 (32-bit registers) */ #define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf104 -#define TX4927_TMR2_TMTISR2 0xf208 +#define TX4927_TMR2_TMTCR2 0xf200 +#define TX4927_TMR2_TMTISR2 0xf204 #define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMCPRB2 0xf20c #define TX4927_TMR2_TMITMR2 0xf210 #define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMPGMR2 0xf230 +#define TX4927_TMR2_TMWTMR2 0xf240 #define TX4927_TMR2_TMTRR2 0xf2f0 #define TX4927_TMR2_LIMIT 0xf2ff -- cgit v1.2.3 From 492fd5f2fdbc1bb7e1d517fd5e9b0cd9f3d0b623 Mon Sep 17 00:00:00 2001 From: Sergei Shtylylov Date: Thu, 26 Jan 2006 04:36:25 +0300 Subject: [MIPS] Au1200: Make KGDB compile AMD Au1200 SOC just doesn't have UART3, so KGDB won't even compile for it as is, here's the fix to make KGDB use UART1. Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 8e1d7ed7d8e..4686e17c206 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1198,7 +1198,11 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* UARTS 0-3 */ #define UART_BASE UART0_ADDR +#ifdef CONFIG_SOC_AU1200 +#define UART_DEBUG_BASE UART1_ADDR +#else #define UART_DEBUG_BASE UART3_ADDR +#endif #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ -- cgit v1.2.3 From 76f072a46f179be371aa10a84c85db06a387713b Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 29 Jan 2006 02:30:55 +0900 Subject: [MIPS] Build blast_cache routines from template Build blast_xxx, blast_xxx_page, blast_xxx_page_indexed from template. Easier to maintaina and saves 300 lines. Generated code should be unchanged. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/r4kcache.h | 400 ++++++-------------------------------------- 1 file changed, 50 insertions(+), 350 deletions(-) (limited to 'include') diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index a5ea9d828ae..cc53196efa4 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -166,123 +166,6 @@ static inline void invalidate_tcache_page(unsigned long addr) : "r" (base), \ "i" (op)); -static inline void blast_dcache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Writeback_Inv_D); - start += 0x200; - } while (start < end); -} - -static inline void blast_dcache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Invalidate_I); - start += 0x200; - } while (start < end); -} - -static inline void blast_icache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x200; - } while (start < end); -} - -static inline void blast_scache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -309,123 +192,6 @@ static inline void blast_scache16_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_dcache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Writeback_Inv_D); - start += 0x400; - } while (start < end); -} - -static inline void blast_dcache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Invalidate_I); - start += 0x400; - } while (start < end); -} - -static inline void blast_icache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x400; - } while (start < end); -} - -static inline void blast_scache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -452,84 +218,6 @@ static inline void blast_scache32_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_icache64(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache64_unroll32(start,Hit_Invalidate_I); - start += 0x800; - } while (start < end); -} - -static inline void blast_icache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache64(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache64_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x800; - } while (start < end); -} - -static inline void blast_scache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -556,43 +244,55 @@ static inline void blast_scache64_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_scache128(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache128_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache128_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x1000; - } while (start < end); -} - -static inline void blast_scache128_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} +/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ +static inline void blast_##pfx##cache##lsize(void) \ +{ \ + unsigned long start = INDEX_BASE; \ + unsigned long end = start + current_cpu_data.desc.waysize; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws,indexop); \ +} \ + \ +static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + do { \ + cache##lsize##_unroll32(start,hitop); \ + start += lsize * 32; \ + } while (start < end); \ +} \ + \ +static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = start + PAGE_SIZE; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws,indexop); \ +} + +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) #endif /* _ASM_R4KCACHE_H */ -- cgit v1.2.3 From 2e66fe24d6faa287088ff18051dd423a32b60502 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 30 Jan 2006 16:48:26 +0000 Subject: [MIPS] local_irq_restore wasn't safe to be used in other macros mode. It always left the assembler in reorder mode possibly causing disaster. Signed-off-by: Ralf Baechle --- include/asm-mips/interrupt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index abdf54ee64c..0da5818a2d6 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h @@ -114,6 +114,7 @@ __asm__ __volatile__( \ __asm__ ( " .macro local_irq_restore flags \n" + " .set push \n" " .set noreorder \n" " .set noat \n" #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) @@ -141,8 +142,7 @@ __asm__ ( " mtc0 \\flags, $12 \n" #endif " irq_disable_hazard \n" - " .set at \n" - " .set reorder \n" + " .set pop \n" " .endm \n"); #define local_irq_restore(flags) \ -- cgit v1.2.3 From 2caf190002770b53fdb263ed744802a1b5e81649 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 30 Jan 2006 17:14:41 +0000 Subject: [MIPS] Cleanup fls implementation. fls was the only called of flz, so fold flz into fls, same for the __ilog2 call. Delete the now unused flz function. Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 58 ++++++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 3b0c8aaf6e8..8e802059fe6 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -644,20 +644,26 @@ static inline unsigned long ffz(unsigned long word) } /* - * flz - find last zero in word. + * fls - find last bit set. * @word: The word to search * - * Returns 0..SZLONG-1 - * Undefined if no zero exists, so code should check against ~0UL first. + * Returns 1..SZLONG + * Returns 0 if no bit exists */ -static inline unsigned long flz(unsigned long word) +static inline unsigned long fls(unsigned long word) { -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return __ilog2(~word); -#else #ifdef CONFIG_32BIT - int r = 31, s; - word = ~word; +#ifdef CONFIG_CPU_MIPS32 + __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); + + return 32 - word; +#else + { + int r = 32, s; + + if (word == 0) + return 0; + s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; @@ -665,10 +671,23 @@ static inline unsigned long flz(unsigned long word) s = 1; if ((word & 0x80000000)) s = 0; r -= s; return r; + } #endif +#endif /* CONFIG_32BIT */ + #ifdef CONFIG_64BIT - int r = 63, s; - word = ~word; +#ifdef CONFIG_CPU_MIPS64 + + __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + + return 64 - word; +#else + { + int r = 64, s; + + if (word == 0) + return 0; + s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; @@ -677,24 +696,11 @@ static inline unsigned long flz(unsigned long word) s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; return r; + } #endif -#endif +#endif /* CONFIG_64BIT */ } -/* - * fls - find last bit set. - * @word: The word to search - * - * Returns 1..SZLONG - * Returns 0 if no bit exists - */ -static inline unsigned long fls(unsigned long word) -{ - if (word == 0) - return 0; - - return flz(~word) + 1; -} #define fls64(x) generic_fls64(x) /* -- cgit v1.2.3 From d4264f183967db9c2dae4275abb98eb1f79facb2 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 29 Jan 2006 02:27:51 +0900 Subject: [MIPS] Remove wrong __user tags. This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/cacheflush.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index a18ba2edc0b..aeae9fabf4a 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -49,8 +49,7 @@ static inline void flush_dcache_page(struct page *page) extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); -extern void (*flush_icache_range)(unsigned long __user start, - unsigned long __user end); +extern void (*flush_icache_range)(unsigned long start, unsigned long end); #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() -- cgit v1.2.3 From 7e5b24ac759176e55c8a535fff6533366168cbe9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 31 Jan 2006 17:07:53 +0000 Subject: [MIPS] Remove buggy inline version of memscan. Signed-off-by: Ralf Baechle --- include/asm-mips/string.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'include') diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 5a06f6d1389..907da600fdd 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -141,26 +141,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #define __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -#ifdef CONFIG_32BIT -#define __HAVE_ARCH_MEMSCAN -static __inline__ void *memscan(void *__addr, int __c, size_t __size) -{ - char *__end = (char *)__addr + __size; - unsigned char __uc = (unsigned char) __c; - - __asm__(".set\tpush\n\t" - ".set\tnoat\n\t" - ".set\treorder\n\t" - "1:\tbeq\t%0,%1,2f\n\t" - "addiu\t%0,1\n\t" - "lbu\t$1,-1(%0)\n\t" - "bne\t$1,%z4,1b\n" - "2:\t.set\tpop" - : "=r" (__addr), "=r" (__end) - : "0" (__addr), "1" (__end), "Jr" (__uc)); - - return __addr; -} -#endif /* CONFIG_32BIT */ - #endif /* _ASM_STRING_H */ -- cgit v1.2.3 From 1e32ceeca25ea30cabce137fac7e2f58fe8847db Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 1 Feb 2006 15:29:21 +0000 Subject: [MIPS] MIPS R2 optimized endianess swapping. From Franck Bui-Huu with modifications by me. Signed-off-by: Ralf Baechle --- include/asm-mips/byteorder.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index d1fe9e5c62e..584f8128fff 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -8,10 +8,39 @@ #ifndef _ASM_BYTEORDER_H #define _ASM_BYTEORDER_H +#include +#include #include #ifdef __GNUC__ +#ifdef CONFIG_CPU_MIPSR2 + +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__( + " wsbh %0, %1 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab16(x) ___arch__swab16(x) + +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__( + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab32(x) ___arch__swab32(x) + +#endif /* CONFIG_CPU_MIPSR2 */ + #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ -- cgit v1.2.3 From c226f2601f55010936f0f3c77ae167a02339f566 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 3 Feb 2006 01:34:01 +0900 Subject: [MIPS] TX49 MFC0 bug workaround If mfc0 $12 follows store and the mfc0 is last instruction of a page and fetching the next instruction causes TLB miss, the result of the mfc0 might wrongly contain EXL bit. ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 Workaround: mask EXL bit of the result or place a nop before mfc0. It doesn't harm to always clear those bits, so we change the code to do so. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/interrupt.h | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index 0da5818a2d6..774348734fa 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h @@ -47,6 +47,17 @@ static inline void local_irq_enable(void) * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs * no nops at all. */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ __asm__ ( " .macro local_irq_disable\n" " .set push \n" @@ -55,8 +66,8 @@ __asm__ ( " di \n" #else " mfc0 $1,$12 \n" - " ori $1,1 \n" - " xori $1,1 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" " .set noreorder \n" " mtc0 $1,$12 \n" #endif @@ -96,8 +107,8 @@ __asm__ ( " andi \\result, 1 \n" #else " mfc0 \\result, $12 \n" - " ori $1, \\result, 1 \n" - " xori $1, 1 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" " .set noreorder \n" " mtc0 $1, $12 \n" #endif @@ -136,8 +147,8 @@ __asm__ ( #else " mfc0 $1, $12 \n" " andi \\flags, 1 \n" - " ori $1, 1 \n" - " xori $1, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" " or \\flags, $1 \n" " mtc0 \\flags, $12 \n" #endif -- cgit v1.2.3 From f09678af51caf93cbbb253b298be995e1145a577 Mon Sep 17 00:00:00 2001 From: Sergei Shtylylov Date: Sat, 4 Feb 2006 15:11:14 +0300 Subject: [MIPS] TX49x7: Fix reporting of the CPU name and PCI clock I've noticed that PCI clock was incorrectly reported as 66 MHz while being mere 33 MHz on RBTX4937 board -- this was due to the different encoding of the PCI divisor field in CCFG register between TX4927 and TX4937 chips... Also, RBTX49x7 was printed out as a CPU name (e.g., "CPU is RBTX4937"); and some debug printk() were duplicating each other... Signed-off-by: Konstantin Baydarov Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/tx4927/tx4927_pci.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 165f6b8b217..66c064690f4 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -253,6 +253,16 @@ struct tx4927_pcic_reg { #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + /* PCFG : Pin Configuration */ #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -- cgit v1.2.3