/*
 * MPC8544 DS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/ {
	model = "MPC8544DS";
	compatible = "MPC8544DS", "MPC85xxDS";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#cpus = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8544@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;	// 32 bytes
			i-cache-line-size = <20>;	// 32 bytes
			d-cache-size = <8000>;		// L1, 32K
			i-cache-size = <8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			32-bit;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 00000000>;	// Filled by U-Boot
	};

	soc8544@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		ranges = <0 e0000000 00100000>;
		reg = <e0000000 00100000>;	// CCSRBAR 1M
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,8544-memory-controller";
			reg = <2000 1000>;
			interrupt-parent = <&mpic>;
			interrupts = <2 2>;
		};

		l2-cache-controller@20000 {
			compatible = "fsl,8544-l2-cache-controller";
			reg = <20000 1000>;
			cache-line-size = <20>;	// 32 bytes
			cache-size = <40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <0 2>;
		};

		i2c@3000 {
			device_type = "i2c";
			compatible = "fsl-i2c";
			reg = <3000 100>;
			interrupts = <1b 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "mdio";
			compatible = "gianfar";
			reg = <24520 20>;
			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <3a 1>;
				reg = <0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <3a 1>;
				reg = <1>;
				device_type = "ethernet-phy";
			};
		};

		ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <24000 1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <d 2 e 2 12 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <26000 1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <f 2 10 2 11 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

		serial@4500 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <4500 100>;
			clock-frequency = <0>;
			interrupts = <1a 2>;
			interrupt-parent = <&mpic>;
		};

		serial@4600 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <4600 100>;
			clock-frequency = <0>;
			interrupts = <1a 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <40000 40000>;
			built-in;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};
	};
};