# Put here option for CPU selection and depending optimization if !X86_ELAN choice prompt "Processor family" default M686 if X86_32 default GENERIC_CPU if X86_64 config M386 bool "386" depends on X86_32 && !UML ---help--- This is the processor type of your CPU. This information is used for optimizing purposes. In order to compile a kernel that can run on all x86 CPU types (albeit not optimally fast), you can specify "386" here. The kernel will not necessarily run on earlier architectures than the one you have chosen, e.g. a Pentium optimized kernel will run on a PPro, but not necessarily on a i486. Here are the settings recommended for greatest speed: - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386 class machine. - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. - "586" for generic Pentium CPUs lacking the TSC (time stamp counter) register. - "Pentium-Classic" for the Intel Pentium. - "Pentium-MMX" for the Intel Pentium MMX. - "Pentium-Pro" for the Intel Pentium Pro. - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). - "Crusoe" for the Transmeta Crusoe series. - "Efficeon" for the Transmeta Efficeon series. - "Winchip-C6" for original IDT Winchip. - "Winchip-2" for IDT Winchip 2. - "Winchip-2A" for IDT Winchips with 3dNow! capabilities. - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). - "Geode GX/LX" For AMD Geode GX and LX processors. - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). - "VIA C7" for VIA C7. If you don't know what to do, choose "386". config M486 bool "486" depends on X86_32 help Select this for a 486 series processor, either Intel or one of the compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX, DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. config M586 bool "586/K5/5x86/6x86/6x86MX" depends on X86_32 help Select this for an 586 or 686 series processor such as the AMD K5, the Cyrix 5x86, 6x86 and 6x86MX. This choice does not assume the RDTSC (Read Time Stamp Counter) instruction. config M586TSC bool "Pentium-Classic" depends on X86_32 help Select this for a Pentium Classic processor with the RDTSC (Read Time Stamp Counter) instruction for benchmarking. config M586MMX bool "Pentium-MMX" depends on X86_32 help Select this for a Pentium with the MMX graphics/multimedia extended instructions. config M686 bool "Pentium-Pro" depends on X86_32 help Select this for Intel Pentium Pro chips. This enables the use of Pentium Pro extended instructions, and disables the init-time guard against the f00f bug found in earlier Pentiums. config MPENTIUMII bool "Pentium-II/Celeron(pre-Coppermine)" depends on X86_32 help Select this for Intel chips based on the Pentium-II and pre-Coppermine Celeron core. This option enables an unaligned copy optimization, compiles the kernel with optimization flags tailored for the chip, and applies any applicable Pentium Pro optimizations. config MPENTIUMIII bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" depends on X86_32 help Select this for Intel chips based on the Pentium-III and Celeron-Coppermine core. This option enables use of some extended prefetch instructions in addition to the Pentium II extensions. config MPENTIUMM bool "Pentium M" depends on X86_32 help Select this for Intel Pentium M (not Pentium-4 M) notebook chips. config MPENTIUM4 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" depends on X86_32 help Select this for Intel Pentium 4 chips. This includes the Pentium 4, Pentium D, P4-based Celeron and Xeon, and Pentium-4 M (not Pentium M) chips. This option enables compile flags optimized for the chip, uses the correct cache line size, and applies any applicable optimizations. CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) Select this for: Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: -Willamette -Northwood -Mobile Pentium 4 -Mobile Pentium 4 M -Extreme Edition (Gallatin) -Prescott -Prescott 2M -Cedar Mill -Presler -Smithfiled Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: -Foster -Prestonia -Gallatin -Nocona -Irwindale -Cranford -Potomac -Paxville -Dempsey config MK6 bool "K6/K6-II/K6-III" depends on X86_32 help Select this for an AMD K6-family processor. Enables use of some extended instructions, and passes appropriate optimization flags to GCC. config MK7 bool "Athlon/Duron/K7" depends on X86_32 help Select this for an AMD Athlon K7-family processor. Enables use of some extended instructions, and passes appropriate optimization flags to GCC. config MK8 bool "Opteron/Athlon64/Hammer/K8" help Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables use of some extended instructions, and passes appropriate optimization flags to GCC. config MCRUSOE bool "Crusoe" depends on X86_32 help Select this for a Transmeta Crusoe processor. Treats the processor like a 586 with TSC, and sets some GCC optimization flags (like a Pentium Pro with no alignment requirements). config MEFFICEON bool "Efficeon" depends on X86_32 help Select this for a Transmeta Efficeon processor. config MWINCHIPC6 bool "Winchip-C6" depends on X86_32 help Select this for an IDT Winchip C6 chip. Linux and GCC treat this chip as a 586TSC with some extended instructions and alignment requirements. config MWINCHIP2 bool "Winchip-2" depends on X86_32 help Select this for an IDT Winchip-2. Linux and GCC treat this chip as a 586TSC with some extended instructions and alignment requirements. config MWINCHIP3D bool "Winchip-2A/Winchip-3" depends on X86_32 help Select this for an IDT Winchip-2A or 3. Linux and GCC treat this chip as a 586TSC with some extended instructions and alignment requirements. Also enable out of order memory stores for this CPU, which can increase performance of some operations. config MGEODEGX1 bool "GeodeGX1" depends on X86_32 help Select this for a Geode GX1 (Cyrix MediaGX) chip. config MGEODE_LX bool "Geode GX/LX" depends on X86_32 help Select this for AMD Geode GX and LX processors. config MCYRIXIII bool "CyrixIII/VIA-C3" depends on X86_32 help Select this for a Cyrix III or C3 chip. Presently Linux and GCC treat this chip as a generic 586. Whilst the CPU is 686 class, it lacks the cmov extension which gcc assumes is present when generating 686 code. Note that Nehemiah (Model 9) and above will not boot with this kernel due to them lacking the 3DNow! instructions used in earlier incarnations of the CPU. config MVIAC3_2 bool "VIA C3-2 (Nehemiah)" depends on X86_32 help Select this for a VIA C3 "Nehemiah". Selecting this enables usage of SSE and tells gcc to treat the CPU as a 686. Note, this kernel will not boot on older (pre model 9) C3s. config MVIAC7 bool "VIA C7" depends on X86_32 help Select this for a VIA C7. Selecting this uses the correct cache shift and tells gcc to treat the CPU as a 686. config MPSC bool "Intel P4 / older Netburst based Xeon" depends on X86_64 help Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey Xeon CPUs with Intel 64bit which is compatible with x86-64. Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the Netburst core and shouldn't use this option. You can distinguish them using the cpu family field in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. config MCORE2 bool "Core 2/newer Xeon" help Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx) CPUs. You can distinguish newer from older Xeons by the CPU family in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo) config GENERIC_CPU bool "Generic-x86-64" depends on X86_64 help Generic x86-64 CPU. Run equally well on all x86-64 CPUs. endchoice config X86_GENERIC bool "Generic x86 support" depends on X86_32 help Instead of just including optimizations for the selected x86 variant (e.g. PII, Crusoe or Athlon), include some more generic optimizations as well. This will make the kernel perform better on x86 CPUs other than that selected. This is really intended for distributors who need more generic optimizations. endif config X86_CPU def_bool y select GENERIC_FIND_FIRST_BIT select GENERIC_FIND_NEXT_BIT # # Define implied options from the CPU selection here config X86_L1_CACHE_BYTES int default "128" if GENERIC_CPU || MPSC default "64" if MK8 || MCORE2 depends on X86_64 config X86_INTERNODE_CACHE_BYTES int default "4096" if X86_VSMP default X86_L1_CACHE_BYTES if !X86_VSMP depends on X86_64 config X86_CMPXCHG def_bool X86_64 || (X86_32 && !M386) config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC default "4" if X86_ELAN || M486 || M386 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 config X86_XADD def_bool y depends on X86_32 && !M386 config X86_PPRO_FENCE bool "PentiumPro memory ordering errata workaround" depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 help Old PentiumPro multiprocessor systems had errata that could cause memory operations to violate the x86 ordering standard in rare cases. Enabling this option will attempt to work around some (but not all) occurances of this problem, at the cost of much heavier spinlock and memory barrier operations. If unsure, say n here. Even distro kernels should think twice before enabling this: there are few systems, and an unlikely bug. config X86_F00F_BUG def_bool y depends on M586MMX || M586TSC || M586 || M486 || M386 config X86_WP_WORKS_OK def_bool y depends on !M386 config X86_INVLPG def_bool y depends on X86_32 && !M386 config X86_BSWAP def_bool y depends on X86_32 && !M386 config X86_POPAD_OK def_bool y depends on X86_32 && !M386 config X86_ALIGNMENT_16 def_bool y depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 config X86_INTEL_USERCOPY def_bool y depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 config X86_USE_PPRO_CHECKSUM def_bool y depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2 config X86_USE_3DNOW def_bool y depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML config X86_OOSTORE def_bool y depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR # # P6_NOPs are a relatively minor optimization that require a family >= # 6 processor, except that it is broken on certain VIA chips. # Furthermore, AMD chips prefer a totally different sequence of NOPs # (which work on all CPUs). As a result, disallow these if we're # compiling X86_GENERIC but not X86_64 (these NOPs do work on all # x86-64 capable chips); the list of processors in the right-hand clause # are the cores that benefit from this optimization. # config X86_P6_NOP def_bool y depends on (X86_64 || !X86_GENERIC) && (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || MPENTIUM4 || MPSC) config X86_TSC def_bool y depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64 config X86_CMPXCHG64 def_bool y depends on X86_PAE || X86_64 # this should be set for all -march=.. options where the compiler # generates cmov. config X86_CMOV def_bool y depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || X86_64) config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 default "6" if X86_32 && X86_P6_NOP default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK) default "3" config X86_DEBUGCTLMSR def_bool y depends on !(MK6 || MWINCHIPC6 || MWINCHIP2 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) menuconfig PROCESSOR_SELECT default y bool "Supported processor vendors" if EMBEDDED help This lets you choose what x86 vendor support code your kernel will include. config CPU_SUP_INTEL_32 default y bool "Support Intel processors" if PROCESSOR_SELECT depends on !64BIT help This enables extended support for Intel processors config CPU_SUP_INTEL_64 default y bool "Support Intel processors" if PROCESSOR_SELECT depends on 64BIT help This enables extended support for Intel processors config CPU_SUP_CYRIX_32 default y bool "Support Cyrix processors" if PROCESSOR_SELECT depends on !64BIT help This enables extended support for Cyrix processors config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT help This enables extended support for AMD processors config CPU_SUP_CENTAUR_32 default y bool "Support Centaur processors" if PROCESSOR_SELECT depends on !64BIT help This enables extended support for Centaur processors config CPU_SUP_CENTAUR_64 default y bool "Support Centaur processors" if PROCESSOR_SELECT depends on 64BIT help This enables extended support for Centaur processors config CPU_SUP_TRANSMETA_32 default y bool "Support Transmeta processors" if PROCESSOR_SELECT depends on !64BIT help This enables extended support for Transmeta processors config CPU_SUP_UMC_32 default y bool "Support UMC processors" if PROCESSOR_SELECT depends on !64BIT help This enables extended support for UMC processors config X86_DS bool "Debug Store support" default y help Add support for Debug Store. This allows the kernel to provide a memory buffer to the hardware to store various profiling and tracing events. config X86_PTRACE_BTS bool "ptrace interface to Branch Trace Store" default y depends on (X86_DS && X86_DEBUGCTLMSR) help Add a ptrace interface to allow collecting an execution trace of the traced task. This collects control flow changes in a (cyclic) buffer and allows debuggers to fill in the gaps and show an execution trace of the debuggee.