From b1a9a769711d83af8ab4c7ba4eec52a05a351533 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 30 Nov 2006 08:35:42 +1100 Subject: Wrap access to objects in RAMIN. This will make it easier to support extra RAMIN in vram at a later point. --- shared-core/nouveau_drv.h | 4 +++ shared-core/nouveau_fifo.c | 11 ++++--- shared-core/nouveau_object.c | 74 ++++++++++++++++++++++++-------------------- shared-core/nouveau_state.c | 6 +++- 4 files changed, 56 insertions(+), 39 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 03c7bd12..93887839 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -169,6 +169,7 @@ extern struct nouveau_object *nouveau_dma_object_create(drm_device_t *dev, uint32_t offset, uint32_t size, int access, uint32_t target); extern int nouveau_ioctl_object_init(DRM_IOCTL_ARGS); extern int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS); +extern uint32_t nouveau_chip_instance_get(drm_device_t *dev, uint32_t instance); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); @@ -187,5 +188,8 @@ extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #endif +#define INSTANCE_WR(inst,ofs,val) NV_WRITE(NV_RAMIN+(inst)+((ofs)<<2),(val)) +#define INSTANCE_RD(inst,ofs) NV_READ(NV_RAMIN+(inst)+((ofs)<<2)) + #endif /* __NOUVEAU_DRV_H__ */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d67cdc3c..9ff0563c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -247,7 +247,7 @@ static void nouveau_context_init(drm_device_t *dev, NV_WRITE(ctx_addr,init->put_base); NV_WRITE(ctx_addr+4,init->put_base); // that's what is done in nvosdk, but that part of the code is buggy so... - NV_WRITE(ctx_addr+8, cb_obj->instance >> 4); + NV_WRITE(ctx_addr+8, nouveau_chip_instance_get(dev, cb_obj->instance)); #ifdef __BIG_ENDIAN NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); #else @@ -274,7 +274,8 @@ static void nouveau_nv10_context_init(drm_device_t *dev, */ RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); - RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); + RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, + cb_obj->instance)); #ifdef __BIG_ENDIAN RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | @@ -332,7 +333,8 @@ static void nouveau_nv40_context_init(drm_device_t *dev, */ RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); - RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); + RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, + cb_obj->instance)); RAMFC_WR(DMA_FETCH , 0x30086078); RAMFC_WR(DMA_SUBROUTINE, init->put_base); RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */ @@ -471,7 +473,8 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); - NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_obj->instance >> 4); + NV_WRITE(NV_PFIFO_CACH1_DMAI, + nouveau_chip_instance_get(dev, cb_obj->instance)); NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 0db92ec4..2c899335 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -40,6 +40,15 @@ * - Get rid of DMA object creation, this should be wrapped by MM routines. */ +/* Translate a RAMIN offset into a value the card understands, will be useful + * in the future when we can access more instance ram which isn't mapped into + * the PRAMIN aperture + */ +uint32_t nouveau_chip_instance_get(drm_device_t *dev, uint32_t instance) +{ + return (instance>>4); +} + static void nouveau_object_link(drm_device_t *dev, int fifo_num, struct nouveau_object *obj) { @@ -171,14 +180,14 @@ static int nouveau_hash_table_insert(drm_device_t* dev, int fifo, NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs, (fifo << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT) | - (obj->instance>>4) + nouveau_chip_instance_get(dev, obj->instance) ); else NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs, NV_RAMHT_CONTEXT_VALID | (fifo << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | (obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT) | - (obj->instance>>4) + nouveau_chip_instance_get(dev, obj->instance) ); obj->ht_loc = ofs; @@ -255,16 +264,15 @@ static void nouveau_object_instance_free(drm_device_t *dev, else count = 4; + /* Clean RAMIN entry */ DRM_DEBUG("Instance entry for 0x%08x" "(engine %d, class 0x%x) before destroy:\n", obj->handle, obj->engine, obj->class); - for (i=0;iinstance + (i*4))); - - /* Clean RAMIN entry */ - for (i=0;iinstance + (i*4), 0x00000000); + INSTANCE_RD(obj->instance, i)); + INSTANCE_WR(obj->instance, i, 0x00000000); + } /* Mark instance as free */ obj->instance -= objs->first_instance; @@ -336,21 +344,18 @@ struct nouveau_object *nouveau_dma_object_create(drm_device_t* dev, obj->engine = 0; obj->class = 0; - NV_WRITE(NV_RAMIN + obj->instance + 0, ((1<<12) - | (1<<13) - | (adjust<<20) - | (access<<14) - | (target<<16) - | 0x3D /* DMA_IN_MEMORY */) - ); - NV_WRITE(NV_RAMIN + obj->instance + 4, - size - 1); - NV_WRITE(NV_RAMIN + obj->instance + 8, + INSTANCE_WR(obj->instance, 0, ((1<<12) | (1<<13) | + (adjust << 20) | + (access << 14) | + (target << 16) | + 0x3D /* DMA_IN_MEMORY */)); + INSTANCE_WR(obj->instance, 1, size-1); + INSTANCE_WR(obj->instance, 2, frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0)); /* I don't actually know what this is, the DMA objects I see * in renouveau dumps usually have this as the same as +8 */ - NV_WRITE(NV_RAMIN + obj->instance + 12, + INSTANCE_WR(obj->instance, 3, frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0)); return obj; @@ -467,24 +472,25 @@ static struct nouveau_object *nouveau_context_object_create(drm_device_t* dev, obj->engine = 1; obj->class = class; - d0 = dma0 ? (dma0->instance >> 4) : 0; - d1 = dma1 ? (dma1->instance >> 4) : 0; - dn = dma_notifier ? (dma_notifier->instance >> 4) : 0; + d0 = dma0 ? nouveau_chip_instance_get(dev, dma0->instance) : 0; + d1 = dma1 ? nouveau_chip_instance_get(dev, dma1->instance) : 0; + dn = dma_notifier ? + nouveau_chip_instance_get(dev, dma_notifier->instance) : 0; if (dev_priv->card_type >= NV_40) { - NV_WRITE(NV_RAMIN + obj->instance + 0, class | flags0); - NV_WRITE(NV_RAMIN + obj->instance + 4, dn | flags1); - NV_WRITE(NV_RAMIN + obj->instance + 8, d0 | flags2); - NV_WRITE(NV_RAMIN + obj->instance + 12, d1); - NV_WRITE(NV_RAMIN + obj->instance + 16, 0x00000000); - NV_WRITE(NV_RAMIN + obj->instance + 20, 0x00000000); - NV_WRITE(NV_RAMIN + obj->instance + 24, 0x00000000); - NV_WRITE(NV_RAMIN + obj->instance + 28, 0x00000000); + INSTANCE_WR(obj->instance, 0, class | flags0); + INSTANCE_WR(obj->instance, 1, dn | flags1); + INSTANCE_WR(obj->instance, 2, d0 | flags2); + INSTANCE_WR(obj->instance, 3, d1); + INSTANCE_WR(obj->instance, 4, 0x00000000); + INSTANCE_WR(obj->instance, 5, 0x00000000); + INSTANCE_WR(obj->instance, 6, 0x00000000); + INSTANCE_WR(obj->instance, 7, 0x00000000); } else { - NV_WRITE(NV_RAMIN + obj->instance + 0, class | flags0); - NV_WRITE(NV_RAMIN + obj->instance + 4, (dn << 16) | flags1); - NV_WRITE(NV_RAMIN + obj->instance + 8, d0 | (d1 << 16)); - NV_WRITE(NV_RAMIN + obj->instance + 12, 0); + INSTANCE_WR(obj->instance, 0, class | flags0); + INSTANCE_WR(obj->instance, 1, (dn << 16) | flags1); + INSTANCE_WR(obj->instance, 2, d0 | (d1 << 16)); + INSTANCE_WR(obj->instance, 3, 0); } return obj; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index b05442fb..1128da54 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -76,11 +76,15 @@ int nouveau_firstopen(struct drm_device *dev) /* FIXME: doesn't belong here, and have no idea what it's for.. */ if (dev_priv->card_type >= NV_40) { + uint32_t pg0220_inst; + dev_priv->fb_obj = nouveau_dma_object_create(dev, 0, nouveau_mem_fb_amount(dev), NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); - NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4); + pg0220_inst = nouveau_chip_instance_get(dev, + dev_priv->fb_obj->instance); + NV_WRITE(NV_PGRAPH_NV40_UNK220, pg0220_inst); } return 0; -- cgit v1.2.3