From 8bba183b9eeb162661a287bf2e118c6dd419dd24 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 20 May 2009 14:05:03 -0700 Subject: intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it. This happens to rendering with textures with a border, which had resulted in a segfault on dereferencing the irb. --- src/mesa/drivers/dri/intel/intel_fbo.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.c') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 52647ddf8b..0b0f0f980b 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -679,6 +679,11 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) if (rb == NULL) continue; + if (irb == NULL) { + fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT; + continue; + } + switch (irb->texformat->MesaFormat) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_RGB565: -- cgit v1.2.3 From e78a6aa2b94683faa8d43a39aa68d806b14f8833 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 20 May 2009 14:16:34 -0700 Subject: intel: Fall back on any rendering to texture with no miptree. Fixes segfault on an fbo.c negative test for FBO with texture width/height of 0. Previously we just tested for border != 0 to work around this segfault. --- src/mesa/drivers/dri/intel/intel_fbo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.c') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 0b0f0f980b..04723a2f91 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -574,9 +574,10 @@ intel_render_texture(GLcontext * ctx, ASSERT(newImage); - if (newImage->Border != 0) { - /* Fallback on drawing to a texture with a border, which won't have a - * miptree. + intel_image = intel_texture_image(newImage); + if (!intel_image->mt) { + /* Fallback on drawing to a texture that doesn't have a miptree + * (has a border, width/height 0, etc.) */ _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); _mesa_render_texture(ctx, fb, att); @@ -607,7 +608,6 @@ intel_render_texture(GLcontext * ctx, irb->Base.RefCount); /* point the renderbufer's region to the texture image region */ - intel_image = intel_texture_image(newImage); if (irb->region != intel_image->mt->region) { if (irb->region) intel_region_release(&irb->region); -- cgit v1.2.3 From 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 3 Jun 2009 16:40:20 +0000 Subject: intel: Add support for tiled textures. This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now. --- src/mesa/drivers/dri/intel/intel_fbo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.c') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 04723a2f91..0ea413aee1 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -217,7 +217,8 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, DBG("Allocating %d x %d Intel RBO (pitch %d)\n", width, height, pitch); - irb->region = intel_region_alloc(intel, cpp, width, height, pitch, + irb->region = intel_region_alloc(intel, I915_TILING_NONE, + cpp, width, height, pitch, GL_TRUE); if (!irb->region) return GL_FALSE; /* out of memory? */ -- cgit v1.2.3