From 0b22615c2c860968a027c04519e25864ae69f6cd Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 2 May 2009 17:27:03 +0200 Subject: r300: set proper texture row alignment for IGP chips Looks like r400 based IGP chips require 64 byte alignment --- src/mesa/drivers/dri/r300/r300_context.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri/r300/r300_context.c') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 4d1f10ba4d..70c7730be9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (r300->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 || + screen->chip_family == CHIP_FAMILY_RS740) { + r300->radeon.texture_row_align = 64; + } + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); -- cgit v1.2.3