From a369963b18fc7ef75f6f5354e0d685cef9ecb70d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Jul 2009 17:22:59 -0400 Subject: r600: add user clip plane support --- src/mesa/drivers/dri/r600/r700_chip.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 087d17312e..91aa8fc8fc 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -722,3 +722,25 @@ GLboolean r700SendSQConfig(context_t *context) return GL_TRUE; } +GLboolean r700SendUCPState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + int i; + + for (i = 0; i < R700_MAX_UCP; i++) { + if (r700->ucp[i].enabled) { + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All); + END_BATCH(); + COMMIT_BATCH(); + } + } + + return GL_TRUE; +} + -- cgit v1.2.3 From 9e6d38f8a2cc89e3d45ef2bb169b72c3c41fc27b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 21 Jul 2009 01:58:05 -0400 Subject: r600: add alpha test support --- src/mesa/drivers/dri/r600/r700_chip.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 91aa8fc8fc..635dd58e72 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -139,6 +139,7 @@ GLboolean r700InitChipObject(context_t *context) // SX LINK_STATES(SX_MISC); LINK_STATES(SX_ALPHA_TEST_CONTROL); + LINK_STATES(SX_ALPHA_REF); // VGT LINK_STATES(VGT_MAX_VTX_INDX); -- cgit v1.2.3 From 0b3d51ee3118a7f12a44650d1c14e1bfcf50ed58 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 24 Jul 2009 12:39:51 -0400 Subject: r600: switch vtx resource setup to use SETfield macros For consistency --- src/mesa/drivers/dri/r600/r700_chip.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 635dd58e72..899b464c54 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -306,15 +306,19 @@ void r700SetupVTXConstants(GLcontext * ctx, uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1; - uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ - |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift - |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ - |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift - |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; - - uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; - - uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; + SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */ + SETfield(uSQ_VTX_CONSTANT_WORD2_0, stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask); + SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(GL_FLOAT, size, NULL), + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */ + SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); + + SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask); + SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); BEGIN_BATCH_NO_AUTOSTATE(9); -- cgit v1.2.3 From 48b2fea142af93317e095461fc1f7ef6531268c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 27 Jul 2009 02:07:59 -0400 Subject: r600: set VGT NUM_INSTANCES as part of the draw command set VGT NUM_INSTANCES as part of the draw command rather than as state as recommended by the pm4 guide. Also, use the NUM_INSTANCES packet. --- src/mesa/drivers/dri/r600/r700_chip.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 899b464c54..e683c8cf92 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -160,7 +160,6 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL); LINK_STATES(VGT_GS_MODE); LINK_STATES(VGT_PRIMITIVEID_EN); - LINK_STATES(VGT_DMA_NUM_INSTANCES); LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); LINK_STATES(VGT_INSTANCE_STEP_RATE_0); LINK_STATES(VGT_INSTANCE_STEP_RATE_1); -- cgit v1.2.3 From 719abd7fc088c5ebc567e9ea20bdd6fc9fe1af3b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 28 Jul 2009 16:58:41 -0400 Subject: r600: fix flat shading Set the flat shading bit on the appropriate PS input depending on the type of attribute it is. The VS output and PS input routing should probably be made more dynamic at some point. We may want to use semantic ids to make it easier. --- src/mesa/drivers/dri/r600/r700_chip.c | 44 ++++++++--------------------------- 1 file changed, 10 insertions(+), 34 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e683c8cf92..c083862f36 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -213,39 +213,6 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(SPI_VS_OUT_ID_8); LINK_STATES(SPI_VS_OUT_ID_9); - LINK_STATES(SPI_PS_INPUT_CNTL_0); - LINK_STATES(SPI_PS_INPUT_CNTL_1); - LINK_STATES(SPI_PS_INPUT_CNTL_2); - LINK_STATES(SPI_PS_INPUT_CNTL_3); - LINK_STATES(SPI_PS_INPUT_CNTL_4); - LINK_STATES(SPI_PS_INPUT_CNTL_5); - LINK_STATES(SPI_PS_INPUT_CNTL_6); - LINK_STATES(SPI_PS_INPUT_CNTL_7); - LINK_STATES(SPI_PS_INPUT_CNTL_8); - LINK_STATES(SPI_PS_INPUT_CNTL_9); - LINK_STATES(SPI_PS_INPUT_CNTL_10); - LINK_STATES(SPI_PS_INPUT_CNTL_11); - LINK_STATES(SPI_PS_INPUT_CNTL_12); - LINK_STATES(SPI_PS_INPUT_CNTL_13); - LINK_STATES(SPI_PS_INPUT_CNTL_14); - LINK_STATES(SPI_PS_INPUT_CNTL_15); - LINK_STATES(SPI_PS_INPUT_CNTL_16); - LINK_STATES(SPI_PS_INPUT_CNTL_17); - LINK_STATES(SPI_PS_INPUT_CNTL_18); - LINK_STATES(SPI_PS_INPUT_CNTL_19); - LINK_STATES(SPI_PS_INPUT_CNTL_20); - LINK_STATES(SPI_PS_INPUT_CNTL_21); - LINK_STATES(SPI_PS_INPUT_CNTL_22); - LINK_STATES(SPI_PS_INPUT_CNTL_23); - LINK_STATES(SPI_PS_INPUT_CNTL_24); - LINK_STATES(SPI_PS_INPUT_CNTL_25); - LINK_STATES(SPI_PS_INPUT_CNTL_26); - LINK_STATES(SPI_PS_INPUT_CNTL_27); - LINK_STATES(SPI_PS_INPUT_CNTL_28); - LINK_STATES(SPI_PS_INPUT_CNTL_29); - LINK_STATES(SPI_PS_INPUT_CNTL_30); - LINK_STATES(SPI_PS_INPUT_CNTL_31); - LINK_STATES(SPI_VS_OUT_CONFIG); LINK_STATES(SPI_THREAD_GROUPING); LINK_STATES(SPI_PS_IN_CONTROL_0); @@ -435,12 +402,21 @@ GLboolean r700SendContextStates(context_t *context) }; END_BATCH(); }; + + /* todo: + * - split this into a separate function? + * - only emit the ones we use + */ + BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS); + R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS); + for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++) + R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All); + END_BATCH(); COMMIT_BATCH(); return GL_TRUE; } - GLboolean r700SendDepthTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); -- cgit v1.2.3 From 643d52a39443a81bbc7e9b234450754375052b20 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Jul 2009 21:27:05 -0400 Subject: r600: warning fixes --- src/mesa/drivers/dri/r600/r700_chip.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index c083862f36..994463fa6d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -249,7 +249,6 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int count) /* number of vectors in stream */ { context_t *context = R700_CONTEXT(ctx); - uint32_t *dest; struct radeon_aos * paos = (struct radeon_aos *)pAos; offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; @@ -417,7 +416,7 @@ GLboolean r700SendContextStates(context_t *context) return GL_TRUE; } -GLboolean r700SendDepthTargetState(context_t *context, int id) +GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; @@ -540,7 +539,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) GLboolean r700SendPSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -575,7 +573,6 @@ GLboolean r700SendPSState(context_t *context) GLboolean r700SendVSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -609,7 +606,6 @@ GLboolean r700SendVSState(context_t *context) GLboolean r700SendFSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -652,8 +648,6 @@ GLboolean r700SendFSState(context_t *context) GLboolean r700SendViewportState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); if (id > R700_MAX_VIEWPORTS) -- cgit v1.2.3 From be1687a89271a58d7e4e6f613affa609589f5048 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 10:53:06 -0400 Subject: r600: re-arrange state setup and emit so they are not mixed --- src/mesa/drivers/dri/r600/r700_chip.c | 64 +++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 994463fa6d..beb5b70245 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -38,6 +38,8 @@ #include "r700_vertprog.h" #include "r700_ioctl.h" +#include "radeon_mipmap_tree.h" + #define LINK_STATES(reg) \ do \ { \ @@ -241,6 +243,68 @@ GLboolean r700InitChipObject(context_t *context) return GL_TRUE; } +GLboolean r700SendTextureState(context_t *context) +{ + unsigned int i; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + struct radeon_bo *bo = NULL; + BATCH_LOCALS(&context->radeon); + + for (i=0; itextures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + r700->textures[i]->SQ_TEX_RESOURCE3, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(5); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(2 + 4); + R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); + END_BATCH(); + + COMMIT_BATCH(); + } + } + } + return GL_TRUE; +} + void r700SetupVTXConstants(GLcontext * ctx, unsigned int nStreamID, void * pAos, -- cgit v1.2.3 From 54a16419235d298e4b7c1761d6abe8066e6cf393 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 11:12:10 -0400 Subject: r600: unify state emit into one function --- src/mesa/drivers/dri/r600/r700_chip.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index beb5b70245..f6face50db 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -373,7 +373,6 @@ void r700SetupVTXConstants(GLcontext * ctx, int r700SetupStreams(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); struct r700_vertex_program *vpc @@ -387,7 +386,7 @@ int r700SetupStreams(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); R600_OUT_BATCH(0); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); -- cgit v1.2.3 From 177c33c481d84058f57e761b25cba735b9c7e6ea Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 12:06:26 -0400 Subject: r600: remove unused offset_mod stuff this is a step in migrating to the common cs code --- src/mesa/drivers/dri/r600/r700_chip.c | 44 +++++++---------------------------- 1 file changed, 8 insertions(+), 36 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index f6face50db..ad4f29b729 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -247,7 +247,6 @@ GLboolean r700SendTextureState(context_t *context) { unsigned int i; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; struct radeon_bo *bo = NULL; BATCH_LOCALS(&context->radeon); @@ -272,11 +271,11 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); @@ -314,8 +313,6 @@ void r700SetupVTXConstants(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; - BATCH_LOCALS(&context->radeon); unsigned int uSQ_VTX_CONSTANT_WORD0_0; @@ -357,7 +354,7 @@ void r700SetupVTXConstants(GLcontext * ctx, R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, paos->bo, uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); @@ -483,7 +480,6 @@ GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_depthbuffer(&context->radeon); @@ -492,10 +488,6 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); @@ -504,7 +496,7 @@ GLboolean r700SendDepthTargetState(context_t *context) R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All); END_BATCH(); @@ -541,7 +533,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_colorbuffer(&context->radeon); @@ -556,16 +547,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) if (!r700->render_target[id].enabled) return GL_FALSE; - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, rrb->bo, r700->render_target[id].CB_COLOR0_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && @@ -603,15 +590,10 @@ GLboolean r700SendPSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -619,7 +601,7 @@ GLboolean r700SendPSState(context_t *context) R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, pbo, r700->ps.SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(9); @@ -637,15 +619,10 @@ GLboolean r700SendVSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -653,7 +630,7 @@ GLboolean r700SendVSState(context_t *context) R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, pbo, r700->vs.SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); @@ -670,7 +647,6 @@ GLboolean r700SendFSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); /* XXX fixme @@ -684,10 +660,6 @@ GLboolean r700SendFSState(context_t *context) r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; /* XXX */ - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -695,7 +667,7 @@ GLboolean r700SendFSState(context_t *context) R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, pbo, r700->fs.SQ_PGM_START_FS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); -- cgit v1.2.3 From 95b64c0ed20725db2722314d527d63aace6b7f7a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 15:11:41 -0400 Subject: r600: make sure bos are valid before usign that --- src/mesa/drivers/dri/r600/r700_chip.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index ad4f29b729..78779e841d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -321,6 +321,9 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + if (!paos->bo) + return GL_FALSE; + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || @@ -594,6 +597,9 @@ GLboolean r700SendPSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -623,6 +629,9 @@ GLboolean r700SendVSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -660,6 +669,9 @@ GLboolean r700SendFSState(context_t *context) r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; /* XXX */ + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); -- cgit v1.2.3 From b0c191acaf0fbbfa743781908187344f5081a083 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 12 Aug 2009 15:34:24 -0400 Subject: r600: state cleanups --- src/mesa/drivers/dri/r600/r700_chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 78779e841d..e5e0f556cb 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -322,7 +322,7 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; if (!paos->bo) - return GL_FALSE; + return; if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || -- cgit v1.2.3 From 083b04e809c8d4db9033d18416f2cf761d1207bb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 13 Aug 2009 17:29:24 -0400 Subject: r600: move non-surface related depth state to general state --- src/mesa/drivers/dri/r600/r700_chip.c | 38 ++++++++++++++--------------------- 1 file changed, 15 insertions(+), 23 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e5e0f556cb..083b9973ac 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -138,6 +138,19 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(CB_CLRCMP_MSK); LINK_STATES(CB_BLEND_CONTROL); + //DB + LINK_STATES(DB_HTILE_DATA_BASE); + LINK_STATES(DB_STENCIL_CLEAR); + LINK_STATES(DB_DEPTH_CLEAR); + LINK_STATES(DB_STENCILREFMASK); + LINK_STATES(DB_STENCILREFMASK_BF); + LINK_STATES(DB_DEPTH_CONTROL); + LINK_STATES(DB_SHADER_CONTROL); + LINK_STATES(DB_RENDER_CONTROL); + LINK_STATES(DB_RENDER_OVERRIDE); + LINK_STATES(DB_HTILE_SURFACE); + LINK_STATES(DB_ALPHA_TO_MASK); + // SX LINK_STATES(SX_MISC); LINK_STATES(SX_ALPHA_TEST_CONTROL); @@ -491,37 +504,16 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - BEGIN_BATCH_NO_AUTOSTATE(9); + BEGIN_BATCH_NO_AUTOSTATE(8); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All); - R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3); + R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2); R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); - R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All); - END_BATCH(); - - BEGIN_BATCH_NO_AUTOSTATE(24); - R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); - R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); - R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All); - - R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); - R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All); - R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All); - - R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All); - R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All); - - R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2); - R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All); - R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All); - - R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All); - R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From 9d96095c1e40a2ffe988443eb2cb36b4b0a7ca1f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 13 Aug 2009 17:55:42 -0400 Subject: r600: move non-surface related cb state to general state --- src/mesa/drivers/dri/r600/r700_chip.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 083b9973ac..9bb3fcd68f 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -487,6 +487,18 @@ GLboolean r700SendContextStates(context_t *context) for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++) R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All); END_BATCH(); + + if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { + for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { + if (r700->render_target[ui].enabled) { + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui), + r700->render_target[ui].CB_BLEND0_CONTROL.u32All); + END_BATCH(); + } + } + } + COMMIT_BATCH(); return GL_TRUE; @@ -567,12 +579,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All); END_BATCH(); - if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { - BEGIN_BATCH_NO_AUTOSTATE(3); - R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All); - END_BATCH(); - } - COMMIT_BATCH(); r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, -- cgit v1.2.3 From 7069a7548f17bec2b6525775a496f1afb6364c38 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 14 Aug 2009 01:33:45 -0400 Subject: r600: emit SURFACE_BASE_UPDATE on depth base updates on rv6xx --- src/mesa/drivers/dri/r600/r700_chip.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_chip.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 9bb3fcd68f..0fb355a0b6 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -528,6 +528,14 @@ GLboolean r700SendDepthTargetState(context_t *context) R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); END_BATCH(); + if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && + (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) { + BEGIN_BATCH_NO_AUTOSTATE(2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); + R600_OUT_BATCH(1 << 0); + END_BATCH(); + } + COMMIT_BATCH(); r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, -- cgit v1.2.3