From 94c5faad26eae7bb4b95d6c95548860ff52354ba Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sat, 2 Jan 2010 20:47:15 -0800 Subject: sis: ifdef out unused variable. Silences GCC warning. --- src/mesa/drivers/dri/sis/sis_context.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/sis/sis_context.c b/src/mesa/drivers/dri/sis/sis_context.c index f501e7ad2e..346e8c5568 100644 --- a/src/mesa/drivers/dri/sis/sis_context.c +++ b/src/mesa/drivers/dri/sis/sis_context.c @@ -83,6 +83,7 @@ static struct dri_extension card_extensions[] = { NULL, NULL } }; +#if 0 static struct dri_extension card_extensions_6326[] = { /*{ "GL_ARB_texture_border_clamp", NULL },*/ @@ -90,6 +91,7 @@ static struct dri_extension card_extensions_6326[] = /*{ "GL_MESA_ycbcr_texture", NULL },*/ { NULL, NULL } }; +#endif static const struct dri_debug_control debug_control[] = { -- cgit v1.2.3 From d27effbfd88463fc395c364c4e6fc59636074bda Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sat, 2 Jan 2010 21:05:06 -0800 Subject: i810: Fix include recursion. --- src/mesa/drivers/dri/i810/i810tex.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i810/i810tex.h b/src/mesa/drivers/dri/i810/i810tex.h index d980927030..28958dcb4b 100644 --- a/src/mesa/drivers/dri/i810/i810tex.h +++ b/src/mesa/drivers/dri/i810/i810tex.h @@ -29,7 +29,6 @@ #include "main/mtypes.h" #include "main/mm.h" -#include "i810context.h" #include "i810_3d_reg.h" #include "texmem.h" -- cgit v1.2.3 From 58531029e6eba11c374d996ea031f1bbe4386c54 Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sun, 3 Jan 2010 18:32:07 -0800 Subject: r300: Silence 'mixed declarations and code' warning. --- src/mesa/drivers/dri/r300/compiler/memory_pool.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/compiler/memory_pool.c b/src/mesa/drivers/dri/r300/compiler/memory_pool.c index 37aa2b6579..76c7c60d8f 100644 --- a/src/mesa/drivers/dri/r300/compiler/memory_pool.c +++ b/src/mesa/drivers/dri/r300/compiler/memory_pool.c @@ -71,12 +71,14 @@ static void refill_pool(struct memory_pool * pool) void * memory_pool_malloc(struct memory_pool * pool, unsigned int bytes) { if (bytes < POOL_LARGE_ALLOC) { + void * ptr; + if (pool->head + bytes > pool->end) refill_pool(pool); assert(pool->head + bytes <= pool->end); - void * ptr = pool->head; + ptr = pool->head; pool->head += bytes; pool->head = (unsigned char*)(((unsigned long)pool->head + POOL_ALIGN - 1) & ~(POOL_ALIGN - 1)); -- cgit v1.2.3 From 0214b7b3c1eae5573b03b485b18e4c10729831ee Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sun, 3 Jan 2010 20:16:59 -0800 Subject: r300: Silence 'mixed declarations and code' warning. --- src/mesa/drivers/dri/r300/compiler/radeon_code.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.c b/src/mesa/drivers/dri/r300/compiler/radeon_code.c index 1a3d8bb641..853b2becd1 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_code.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.c @@ -143,7 +143,8 @@ unsigned rc_constants_add_immediate_scalar(struct rc_constant_list * c, float da for(index = 0; index < c->Count; ++index) { if (c->Constants[index].Type == RC_CONSTANT_IMMEDIATE) { - for(unsigned comp = 0; comp < c->Constants[index].Size; ++comp) { + unsigned comp; + for(comp = 0; comp < c->Constants[index].Size; ++comp) { if (c->Constants[index].u.Immediate[comp] == data) { *swizzle = RC_MAKE_SWIZZLE(comp, comp, comp, comp); return index; -- cgit v1.2.3 From b14cbfaebc135351a72d86128ae987611ef8c31f Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sun, 3 Jan 2010 20:51:23 -0800 Subject: r300: Silence 'mixed declarations and code' warnings. --- src/mesa/drivers/dri/r300/compiler/radeon_compiler.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c index c0e7a7f7a0..41ea23ee32 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c @@ -232,12 +232,16 @@ void rc_copy_output(struct radeon_compiler * c, unsigned output, unsigned dup_ou void rc_transform_fragment_wpos(struct radeon_compiler * c, unsigned wpos, unsigned new_input) { unsigned tempregi = rc_find_free_temporary(c); + struct rc_instruction * inst_rcp; + struct rc_instruction * inst_mul; + struct rc_instruction * inst_mad; + struct rc_instruction * inst; c->Program.InputsRead &= ~(1 << wpos); c->Program.InputsRead |= 1 << new_input; /* perspective divide */ - struct rc_instruction * inst_rcp = rc_insert_new_instruction(c, &c->Program.Instructions); + inst_rcp = rc_insert_new_instruction(c, &c->Program.Instructions); inst_rcp->U.I.Opcode = RC_OPCODE_RCP; inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; @@ -248,7 +252,7 @@ void rc_transform_fragment_wpos(struct radeon_compiler * c, unsigned wpos, unsig inst_rcp->U.I.SrcReg[0].Index = new_input; inst_rcp->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW; - struct rc_instruction * inst_mul = rc_insert_new_instruction(c, inst_rcp); + inst_mul = rc_insert_new_instruction(c, inst_rcp); inst_mul->U.I.Opcode = RC_OPCODE_MUL; inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; @@ -263,7 +267,7 @@ void rc_transform_fragment_wpos(struct radeon_compiler * c, unsigned wpos, unsig inst_mul->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW; /* viewport transformation */ - struct rc_instruction * inst_mad = rc_insert_new_instruction(c, inst_mul); + inst_mad = rc_insert_new_instruction(c, inst_mul); inst_mad->U.I.Opcode = RC_OPCODE_MAD; inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY; @@ -282,7 +286,6 @@ void rc_transform_fragment_wpos(struct radeon_compiler * c, unsigned wpos, unsig inst_mad->U.I.SrcReg[2].Index = inst_mad->U.I.SrcReg[1].Index; inst_mad->U.I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO); - struct rc_instruction * inst; for (inst = inst_mad->Next; inst != &c->Program.Instructions; inst = inst->Next) { const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); unsigned i; -- cgit v1.2.3 From d1e2fc19cc1b8e4c23f5ad82ec68779c41101b41 Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Sun, 3 Jan 2010 23:33:32 -0800 Subject: r300: Use C-style comments. --- .../drivers/dri/r300/compiler/radeon_program_alu.c | 30 +++++++++++----------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c index ced66af1eb..b5c08aea49 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c @@ -267,9 +267,9 @@ static void transform_LIT(struct radeon_compiler* c, temp = inst->U.I.DstReg.Index; srctemp = srcreg(RC_FILE_TEMPORARY, temp); - // tmp.x = max(0.0, Src.x); - // tmp.y = max(0.0, Src.y); - // tmp.w = clamp(Src.z, -128+eps, 128-eps); + /* tmp.x = max(0.0, Src.x); */ + /* tmp.y = max(0.0, Src.y); */ + /* tmp.w = clamp(Src.z, -128+eps, 128-eps); */ emit2(c, inst->Prev, RC_OPCODE_MAX, 0, dstregtmpmask(temp, RC_MASK_XYW), inst->U.I.SrcReg[0], @@ -280,7 +280,7 @@ static void transform_LIT(struct radeon_compiler* c, swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W), negate(srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle))); - // tmp.w = Pow(tmp.y, tmp.w) + /* tmp.w = Pow(tmp.y, tmp.w) */ emit1(c, inst->Prev, RC_OPCODE_LG2, 0, dstregtmpmask(temp, RC_MASK_W), swizzle(srctemp, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y)); @@ -292,14 +292,14 @@ static void transform_LIT(struct radeon_compiler* c, dstregtmpmask(temp, RC_MASK_W), swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W)); - // tmp.z = (tmp.x > 0) ? tmp.w : 0.0 + /* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */ emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, dstregtmpmask(temp, RC_MASK_Z), negate(swizzle(srctemp, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)), swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W), builtin_zero); - // tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 + /* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */ emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, dstregtmpmask(temp, RC_MASK_XYW), swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE)); @@ -533,16 +533,16 @@ static void sincos_constants(struct radeon_compiler* c, unsigned int *constants) { static const float SinCosConsts[2][4] = { { - 1.273239545, // 4/PI - -0.405284735, // -4/(PI*PI) - 3.141592654, // PI - 0.2225 // weight + 1.273239545, /* 4/PI */ + -0.405284735, /* -4/(PI*PI) */ + 3.141592654, /* PI */ + 0.2225 /* weight */ }, { 0.75, 0.5, - 0.159154943, // 1/(2*PI) - 6.283185307 // 2*PI + 0.159154943, /* 1/(2*PI) */ + 6.283185307 /* 2*PI */ } }; int i; @@ -602,9 +602,9 @@ int radeonTransformTrigSimple(struct radeon_compiler* c, sincos_constants(c, constants); if (inst->U.I.Opcode == RC_OPCODE_COS) { - // MAD tmp.x, src, 1/(2*PI), 0.75 - // FRC tmp.x, tmp.x - // MAD tmp.z, tmp.x, 2*PI, -PI + /* MAD tmp.x, src, 1/(2*PI), 0.75 */ + /* FRC tmp.x, tmp.x */ + /* MAD tmp.z, tmp.x, 2*PI, -PI */ emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W), swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X), swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z), -- cgit v1.2.3 From a160d1c27de8afcf072b4fd438d6a37f16742e75 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 29 Dec 2009 14:47:01 +0200 Subject: r600: support vertex_array_bgra Use vertex program key mechanism and swizzle during vertex fetch - is there a better way? --- src/mesa/drivers/dri/r600/r600_context.h | 1 + src/mesa/drivers/dri/r600/r700_assembler.c | 20 ++++++++++++++++---- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + src/mesa/drivers/dri/r600/r700_vertprog.c | 8 ++++++-- src/mesa/drivers/dri/r600/r700_vertprog.h | 1 + 5 files changed, 25 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 394fd757d4..94662ab547 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -108,6 +108,7 @@ typedef struct StreamDesc GLint size; //number of data element GLenum type; //data element type GLsizei stride; + GLenum format; // GL_RGBA,GLBGRA struct radeon_bo *bo; GLint bo_offset; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 67e0ee7746..b0b38927e6 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -798,6 +798,7 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, GLubyte element, GLuint _signed, GLboolean normalize, + GLenum format, VTX_FETCH_METHOD * pFetchMethod) { GLuint client_size_inbyte; @@ -846,10 +847,21 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X; vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count; - vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X; - vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y; - vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z; - vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W; + if(format == GL_BGRA) + { + vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_Z; + vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y; + vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_X; + vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W; + } + else + { + vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X; + vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y; + vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z; + vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W; + + } vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1; vfetch_instruction_ptr->m_Word1.f.data_format = data_format; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index c66db502a1..ee12582661 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -422,6 +422,7 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, GLubyte element, GLuint _signed, GLboolean normalize, + GLenum format, VTX_FETCH_METHOD * pFetchMethod); GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm); GLuint gethelpr(r700_AssemblerBase* pAsm); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index ffc6068bd8..4ca5ce693a 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -179,7 +179,8 @@ GLboolean Process_Vertex_Program_Vfetch_Instructions2( context->stream_desc[i].size, context->stream_desc[i].element, context->stream_desc[i]._signed, - context->stream_desc[i].normalize, + context->stream_desc[i].normalize, + context->stream_desc[i].format, &vtxFetchMethod); } @@ -308,6 +309,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, vp->aos_desc[i].size = context->stream_desc[i].size; vp->aos_desc[i].stride = context->stream_desc[i].stride; vp->aos_desc[i].type = context->stream_desc[i].type; + vp->aos_desc[i].format = context->stream_desc[i].format; } if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) @@ -368,7 +370,8 @@ void r700SelectVertexShader(GLcontext *ctx) match = GL_TRUE; for(i=0; inNumActiveAos; i++) { - if (vp->aos_desc[i].size != context->stream_desc[i].size) + if (vp->aos_desc[i].size != context->stream_desc[i].size || + vp->aos_desc[i].format != context->stream_desc[i].format) { match = GL_FALSE; break; @@ -471,6 +474,7 @@ static void r700TranslateAttrib(GLcontext *ctx, GLuint unLoc, int count, const s pStreamDesc->size = input->Size; pStreamDesc->dst_loc = context->nNumActiveAos; pStreamDesc->element = unLoc; + pStreamDesc->format = input->Format; switch (pStreamDesc->type) { //GetSurfaceFormat diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index 00824c29d3..645c9ac84a 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -39,6 +39,7 @@ typedef struct ArrayDesc //TEMP GLint size; //number of data element GLenum type; //data element type GLsizei stride; + GLenum format; //GL_RGBA or GL_BGRA } ArrayDesc; struct r700_vertex_program -- cgit v1.2.3 From 63610fae4f46361f2500577a83bf5ac6f9e8b0ac Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 4 Jan 2010 08:47:01 -0800 Subject: i965: Fix the surface offset calculation for tiled buffers. If we ever had a non-tile-aligned tiled renderbuffer, the math was all off. Use the existing x,y coordinates instead of trying to reconstruct them from an incorrectly-calculated offset value. --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 50 ++++++++++++++---------- 1 file changed, 30 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8335e5a650..afb36b7bd7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -522,7 +522,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, GLubyte color_mask[4]; GLboolean color_blend; uint32_t tiling; - uint32_t draw_offset; + uint32_t draw_x; + uint32_t draw_y; } key; memset(&key, 0, sizeof(key)); @@ -564,7 +565,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, } key.pitch = region->pitch; key.cpp = region->cpp; - key.draw_offset = region->draw_offset; /* cur 3d or cube face offset */ + key.draw_x = region->draw_x; + key.draw_y = region->draw_y; } else { key.surface_type = BRW_SURFACE_NULL; key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; @@ -572,7 +574,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.width = 1; key.height = 1; key.cpp = 4; - key.draw_offset = 0; + key.draw_x = 0; + key.draw_y = 0; } /* _NEW_COLOR */ memcpy(key.color_mask, ctx->Color.ColorMask, @@ -602,25 +605,32 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss0.surface_format = key.surface_format; surf.ss0.surface_type = key.surface_type; if (key.tiling == I915_TILING_NONE) { - surf.ss1.base_addr = key.draw_offset; + surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp; } else { - uint32_t tile_offset = key.draw_offset % 4096; - - surf.ss1.base_addr = key.draw_offset - tile_offset; - - assert(BRW_IS_G4X(brw) || tile_offset == 0); - if (BRW_IS_G4X(brw)) { - if (key.tiling == I915_TILING_X) { - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - surf.ss5.x_offset = (tile_offset % 512) / key.cpp / 4; - surf.ss5.y_offset = tile_offset / 512 / 2; - } else { - surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4; - surf.ss5.y_offset = tile_offset / 128 / 2; - } + uint32_t tile_base, tile_x, tile_y; + uint32_t pitch = key.pitch * key.cpp; + + if (key.tiling == I915_TILING_X) { + tile_x = key.draw_x % (512 / key.cpp); + tile_y = key.draw_y % 8; + tile_base = ((key.draw_y / 8) * (8 * pitch)); + tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096; + } else { + /* Y */ + tile_x = key.draw_x % (128 / key.cpp); + tile_y = key.draw_y % 32; + tile_base = ((key.draw_y / 32) * (32 * pitch)); + tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096; } + assert(BRW_IS_G4X(brw) || (tile_x == 0 && tile_y == 0)); + assert(tile_x % 4 == 0); + assert(tile_y % 2 == 0); + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. + */ + surf.ss1.base_addr = tile_base; + surf.ss5.x_offset = tile_x / 4; + surf.ss5.y_offset = tile_y / 2; } if (region_bo != NULL) surf.ss1.base_addr += region_bo->offset; /* reloc */ -- cgit v1.2.3 From 19a26dfc474618ecfe881846a8c9dac221332d44 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 4 Jan 2010 09:39:07 -0800 Subject: intel: Fix CopyTexImage from tiled mipmap levels > 0. Fixes piglit fbo-copyteximage. --- src/mesa/drivers/dri/intel/intel_tex_copy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index ee953cfbe7..ef5aed32f3 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -160,13 +160,14 @@ do_copy_texsubimage(struct intel_context *intel, intelImage->mt->cpp, src_pitch, src->buffer, - src->draw_offset, + 0, src->tiling, intelImage->mt->pitch, dst_bo, 0, intelImage->mt->region->tiling, - x, y, image_x + dstx, image_y + dsty, + src->draw_x + x, src->draw_y + y, + image_x + dstx, image_y + dsty, width, height, GL_COPY)) { UNLOCK_HARDWARE(intel); -- cgit v1.2.3 From b434a816d7a4b298e16a8b51b54e5a2d5ea28da8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 29 Dec 2009 15:55:34 -0800 Subject: i915: Use _MaxLevel on principle in texture setup. It was OK before because we proceed to clamp the value to hardware limits, but given that other use of MaxLevel has been a trap, let's avoid it. --- src/mesa/drivers/dri/i915/i915_texstate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index de258484d6..825f1dbbe3 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -196,10 +196,11 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) state[I915_TEXREG_MS3] |= MS3_TILE_WALK; } - /* We get one field with fraction bits to cover the maximum addressable (smallest - * resolution) LOD. Use it to cover both MAX_LEVEL and MAX_LOD. + /* We get one field with fraction bits for the maximum addressable + * (lowest resolution) LOD. Use it to cover both MAX_LEVEL and + * MAX_LOD. */ - maxlod = MIN2(tObj->MaxLod, tObj->MaxLevel - tObj->BaseLevel); + maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel); state[I915_TEXREG_MS4] = ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK | -- cgit v1.2.3