diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 18:11:33 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 18:11:33 -0700 |
| commit | f7d02ae76ebbf5b8a9531fe150c49e126a397704 (patch) | |
| tree | bcfdcab6e70658d55a3c843694e04e938bf9168f | |
| parent | 78db2ad6f4df9145bfd6aab1c0f1c56d615288ec (diff) | |
| parent | 158304ef09a28c7f2dd37d78f536a4e09ba084a1 (diff) | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (30 commits)
[ARM] Use new get_irqnr_preamble
[ARM] Ensure machine class menu is sorted alphabetically
[ARM] 4333/2: KS8695: Micrel Development board
[ARM] 4332/2: KS8695: Serial driver
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
[ARM] 4371/1: AT91: Support for Atmel AT91SAM9RL-EK development board
[ARM] 4372/1: Define byte sizes in asm-arm/sizes.h
[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
[ARM] Update mach-types
[ARM] export symbol csum_partial_copy_from_user
[ARM] iop13xx: msi support
[ARM] stacktrace fix
[ARM] Spinlock initializer cleanup
[ARM] remove useless config option GENERIC_BUST_SPINLOCK
[ARM] 4303/3: base kernel support for TI DaVinci
[ARM] 4369/1: AT91: Fix circular dependency in header files
[ARM] 4368/1: S3C24xx: build fix
[ARM] 4364/1: AT91: LEDS on AT91SAM9261-EK
[ARM] Fix iop32x/iop33x build
[ARM] EBSA110: fix build errors caused by missing "const"
...
139 files changed, 8624 insertions, 548 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7c0984d4a8..e55bbd32dca 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -114,9 +114,6 @@ config GENERIC_CALIBRATE_DELAY bool default y -config GENERIC_BUST_SPINLOCK - bool - config ARCH_MAY_HAVE_PC_FDC bool @@ -247,6 +244,15 @@ config ARCH_IMX help Support for Motorola's i.MX family of processors (MX1, MXL). +config ARCH_IOP13XX + bool "IOP13xx-based" + depends on MMU + select PLAT_IOP + select PCI + select ARCH_SUPPORTS_MSI + help + Support for Intel's IOP13XX (XScale) family of processors. + config ARCH_IOP32X bool "IOP32x-based" depends on MMU @@ -264,22 +270,12 @@ config ARCH_IOP33X help Support for Intel's IOP33X (XScale) family of processors. -config ARCH_IOP13XX - bool "IOP13xx-based" - depends on MMU - select PLAT_IOP - select PCI - select ARCH_SUPPORTS_MSI - help - Support for Intel's IOP13XX (XScale) family of processors. - -config ARCH_IXP4XX - bool "IXP4xx-based" +config ARCH_IXP23XX + bool "IXP23XX-based" depends on MMU - select GENERIC_TIME - select GENERIC_CLOCKEVENTS + select PCI help - Support for Intel's IXP4XX (XScale) family of processors. + Support for Intel's IXP23xx (XScale) family of processors. config ARCH_IXP2000 bool "IXP2400/2800-based" @@ -288,12 +284,13 @@ config ARCH_IXP2000 help Support for Intel's IXP2400/2800 (XScale) family of processors. -config ARCH_IXP23XX - bool "IXP23XX-based" +config ARCH_IXP4XX + bool "IXP4xx-based" depends on MMU - select PCI + select GENERIC_TIME + select GENERIC_CLOCKEVENTS help - Support for Intel's IXP23xx (XScale) family of processors. + Support for Intel's IXP4XX (XScale) family of processors. config ARCH_L7200 bool "LinkUp-L7200" @@ -308,6 +305,12 @@ config ARCH_L7200 If you have any questions or comments about the Linux kernel port to this board, send e-mail to <sjhill@cotw.com>. +config ARCH_KS8695 + bool "Micrel/Kendin KS8695" + help + Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based + System-on-Chip devices. + config ARCH_NS9XXX bool "NetSilicon NS9xxx" help @@ -354,7 +357,6 @@ config ARCH_SA1100 config ARCH_S3C2410 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" select GENERIC_GPIO - select GENERIC_TIME help Samsung S3C2410X CPU based systems, such as the Simtec Electronics BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or @@ -377,6 +379,13 @@ config ARCH_LH7A40X core with a wide array of integrated devices for hand-held and low-power applications. +config ARCH_DAVINCI + bool "TI DaVinci" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for TI's DaVinci platform. + config ARCH_OMAP bool "TI OMAP" select GENERIC_GPIO @@ -445,6 +454,10 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-ns9xxx/Kconfig" +source "arch/arm/mach-davinci/Kconfig" + +source "arch/arm/mach-ks8695/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -505,7 +518,7 @@ config ISA_DMA_API bool config PCI - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -674,7 +687,8 @@ config LEDS ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ - ARCH_AT91 || MACH_TRIZEPS4 + ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ + ARCH_KS8695 help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 00ea4305ad5..cbd5010d3bc 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -135,6 +135,8 @@ endif machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 + machine-$(CONFIG_ARCH_DAVINCI) := davinci + machine-$(CONFIG_ARCH_KS8695) := ks8695 ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig new file mode 100644 index 00000000000..fbe8b304934 --- /dev/null +++ b/arch/arm/configs/at91sam9rlek_defconfig @@ -0,0 +1,957 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.21 +# Mon May 7 16:30:40 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set + +# +# Atmel AT91 System-on-Chip +# +# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +# CONFIG_ARCH_AT91SAM9263 is not set +CONFIG_ARCH_AT91SAM9RL=y + +# +# AT91SAM9RL Board Type +# +CONFIG_MACH_AT91SAM9RLEK=y + +# +# AT91 Board Options +# + +# +# AT91 Feature Selections +# +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +# CONFIG_INET is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_AT91=y +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=24576 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_DEBUG is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +# CONFIG_NETDEVICES is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_ATMEL=y +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_SEQ_DUMMY=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +# CONFIG_SND_PCM_XRUN_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# + +# +# SoC audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_AT91=y + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig new file mode 100644 index 00000000000..8ab21a0719e --- /dev/null +++ b/arch/arm/configs/ks8695_defconfig @@ -0,0 +1,880 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.17-rc4 +# Thu May 25 15:42:51 2006 +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_VECTORS_BASE=0xffff0000 + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_UID16=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set +CONFIG_OBSOLETE_INTERMODULE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +# CONFIG_BLK_DEV_IO_TRACE is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_AT91 is not set +CONFIG_ARCH_KS8695=y + +# +# Kendin/Micrel KS8695 Implementations +# +CONFIG_MACH_KS8695=y +# CONFIG_MACH_DSM320 is not set +# CONFIG_MACH_CM4002 is not set +# CONFIG_MACH_CM4008 is not set +# CONFIG_MACH_CM40xx is not set +# CONFIG_MACH_LITE300 is not set +# CONFIG_MACH_SE4200 is not set +# CONFIG_MACH_MANGA_KS8695 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM922T=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=y +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +# CONFIG_PD6729 is not set +# CONFIG_I82092 is not set +CONFIG_PCCARD_NONSTATIC=y + +# +# Kernel Features +# +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_APM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_ARM_KS8695_ETHER=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_KS8695=y +CONFIG_SERIAL_KS8695_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +CONFIG_FRAME_POINTER=y +# CONFIG_UNWIND_INFO is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index a6698dc4f6b..6db6392806f 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -1,15 +1,27 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.17 -# Sat Jun 24 22:45:14 2006 +# Linux kernel version: 2.6.21 +# Mon Apr 30 21:23:20 2007 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_ARCH_MTD_XIP=y CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # # Code maturity level options @@ -26,18 +38,25 @@ CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_SYSCTL=y -CONFIG_AUDIT=y +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_UID16=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_HOTPLUG=y @@ -49,10 +68,11 @@ CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SHMEM=y CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 # CONFIG_SLOB is not set -CONFIG_OBSOLETE_INTERMODULE=y # # Loadable module support @@ -60,14 +80,17 @@ CONFIG_OBSOLETE_INTERMODULE=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set +CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y # # Block layer # +CONFIG_BLOCK=y +CONFIG_LBD=y # CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LSF=y # # IO Schedulers @@ -85,18 +108,29 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # # System Type # +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP23XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set CONFIG_ARCH_PXA=y # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set @@ -104,12 +138,6 @@ CONFIG_ARCH_PXA=y # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91RM9200 is not set # # Intel PXA2xx Implementations @@ -133,11 +161,16 @@ CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features # CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y CONFIG_XSCALE_PMU=y # @@ -147,16 +180,16 @@ CONFIG_XSCALE_PMU=y # # PCCARD (PCMCIA/CardBus) support # -CONFIG_PCCARD=m +CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=m -CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA=y +# CONFIG_PCMCIA_LOAD_CIS is not set CONFIG_PCMCIA_IOCTL=y # # PC-card bridges # -CONFIG_PCMCIA_PXA2XX=m +CONFIG_PCMCIA_PXA2XX=y # # Kernel Features @@ -164,7 +197,8 @@ CONFIG_PCMCIA_PXA2XX=m CONFIG_PREEMPT=y # CONFIG_NO_IDLE_HZ is not set CONFIG_HZ=100 -# CONFIG_AEABI is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -174,6 +208,8 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 CONFIG_LEDS=y CONFIG_LEDS_TIMER=y CONFIG_LEDS_CPU=y @@ -184,8 +220,9 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200n8" +CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set # # Floating point emulation @@ -203,16 +240,16 @@ CONFIG_FPE_NWFPE_XP=y # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=m -# CONFIG_ARTHUR is not set +# CONFIG_BINFMT_MISC is not set # # Power management options # CONFIG_PM=y -CONFIG_PM_LEGACY=y +# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set -CONFIG_APM=y +# CONFIG_PM_SYSFS_DEPRECATED is not set +# CONFIG_APM_EMULATION is not set # # Networking @@ -222,13 +259,15 @@ CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -246,24 +285,25 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # # IP: Virtual Server Configuration # # CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set -# CONFIG_IPV6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set @@ -271,29 +311,16 @@ CONFIG_NETFILTER=y # Core Netfilter Configuration # # CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NF_CONNTRACK_ENABLED is not set +# CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set # # IP: Netfilter Configuration # -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_CONNTRACK_EVENTS is not set -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -# CONFIG_IP_NF_NETBIOS_NS is not set -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -# CONFIG_IP_NF_PPTP is not set -# CONFIG_IP_NF_H323 is not set CONFIG_IP_NF_QUEUE=m - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set # # DCCP Configuration (EXPERIMENTAL) @@ -318,7 +345,6 @@ CONFIG_VLAN_8021Q=m # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -378,6 +404,7 @@ CONFIG_IRTTY_SIR=m # CONFIG_USB_IRDA is not set # CONFIG_SIGMATEL_FIR is not set # CONFIG_PXA_FICP is not set +# CONFIG_MCS_FIR is not set CONFIG_BT=m CONFIG_BT_L2CAP=m CONFIG_BT_SCO=m @@ -401,14 +428,20 @@ CONFIG_BT_HIDP=m # CONFIG_BT_HCIBLUECARD is not set # CONFIG_BT_HCIBTUART is not set # CONFIG_BT_HCIVHCI is not set -CONFIG_IEEE80211=m +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +CONFIG_IEEE80211=y # CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_WEP=y CONFIG_IEEE80211_CRYPT_CCMP=m CONFIG_IEEE80211_CRYPT_TKIP=m CONFIG_IEEE80211_SOFTMAC=m # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y # # Device Drivers @@ -420,16 +453,13 @@ CONFIG_WIRELESS_EXT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set # # Connector - unified userspace <-> kernelspace linker # CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set CONFIG_MTD_CONCAT=y @@ -445,12 +475,13 @@ CONFIG_MTD_REDBOOT_PARTS_READONLY=y # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set -CONFIG_NFTL=y -CONFIG_NFTL_RW=y -CONFIG_INFTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set # # RAM/ROM/Flash chip drivers @@ -490,9 +521,8 @@ CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x0 -CONFIG_MTD_PHYSMAP_LEN=0x4000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_TRIZEPS4 is not set # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_IMPA7 is not set # CONFIG_MTD_SHARP_SL is not set @@ -501,42 +531,45 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_BLOCK2MTD=y # # Disk-On-Chip Device Drivers # -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set +CONFIG_MTD_DOC2000=y +CONFIG_MTD_DOC2001=y CONFIG_MTD_DOC2001PLUS=y CONFIG_MTD_DOCPROBE=y CONFIG_MTD_DOCECC=y -# CONFIG_MTD_DOCPROBE_ADVANCED is not set -CONFIG_MTD_DOCPROBE_ADDRESS=0 - -# -# NAND Flash Device Drivers -# +CONFIG_MTD_DOCPROBE_ADVANCED=y +CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000 +CONFIG_MTD_DOCPROBE_HIGH=y +# CONFIG_MTD_DOCPROBE_55AA is not set CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set # CONFIG_MTD_NAND_H1900 is not set CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_DISKONCHIP=y -# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 -# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y # CONFIG_MTD_NAND_SHARPSL is not set # CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_ONENAND=y +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set +# CONFIG_MTD_ONENAND_GENERIC is not set +# CONFIG_MTD_ONENAND_OTP is not set # -# OneNAND Flash Device Drivers +# UBI - Unsorted block images # -# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_UBI is not set # # Parallel port support @@ -546,6 +579,7 @@ CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 # # Plug and Play support # +# CONFIG_PNPACPI is not set # # Block devices @@ -556,9 +590,9 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=y # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_COUNT=8 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set @@ -566,6 +600,7 @@ CONFIG_BLK_DEV_INITRD=y # ATA/ATAPI/MFM/RLL support # CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # @@ -585,27 +620,27 @@ CONFIG_BLK_DEV_IDECS=m # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y -CONFIG_IDE_PXA_CF=y -CONFIG_IDE_ARM=y +# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set # CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set -CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set # @@ -614,21 +649,23 @@ CONFIG_CHR_DEV_SG=m CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set # -# SCSI Transport Attributes +# SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set # # SCSI low-level drivers # # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_SATA is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_ESP_CORE is not set # # PCMCIA SCSI adapter support @@ -640,6 +677,14 @@ CONFIG_SCSI_MULTI_LUN=y # CONFIG_PCMCIA_SYM53C500 is not set # +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PLATFORM=m + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set @@ -675,10 +720,14 @@ CONFIG_PHYLIB=y # MII PHY device drivers # # CONFIG_MARVELL_PHY is not set -CONFIG_DAVICOM_PHY=y +# CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_FIXED_PHY is not set # # Ethernet (10 or 100Mbit) @@ -687,6 +736,7 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_SMC91X is not set CONFIG_DM9000=y +# CONFIG_SMC911X is not set # # Ethernet (1000 Mbit) @@ -701,41 +751,23 @@ CONFIG_DM9000=y # # -# Wireless LAN (non-hamradio) -# -CONFIG_NET_RADIO=y -# CONFIG_NET_WIRELESS_RTNETLINK is not set - -# -# Obsolete Wireless cards support (pre-802.11) -# -# CONFIG_STRIP is not set -# CONFIG_PCMCIA_WAVELAN is not set -# CONFIG_PCMCIA_NETWAVE is not set - -# -# Wireless 802.11 Frequency Hopping cards support +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y # CONFIG_PCMCIA_RAYCS is not set - -# -# Wireless 802.11b ISA/PCI cards support -# -CONFIG_HERMES=m +CONFIG_HERMES=y # CONFIG_ATMEL is not set - -# -# Wireless 802.11b Pcmcia/Cardbus cards support -# -CONFIG_PCMCIA_HERMES=m -# CONFIG_PCMCIA_SPECTRUM is not set -CONFIG_AIRO_CS=m +CONFIG_PCMCIA_HERMES=y +CONFIG_PCMCIA_SPECTRUM=y +# CONFIG_AIRO_CS is not set # CONFIG_PCMCIA_WL3501 is not set -CONFIG_HOSTAP=m +# CONFIG_USB_ZD1201 is not set +CONFIG_HOSTAP=y CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_HOSTAP_CS=m -CONFIG_NET_WIRELESS=y +CONFIG_HOSTAP_CS=y +# CONFIG_ZD1211RW is not set # # PCMCIA network device support @@ -756,6 +788,7 @@ CONFIG_PPP_BSDCOMP=m CONFIG_PPP_MPPE=m # CONFIG_PPPOE is not set # CONFIG_SLIP is not set +CONFIG_SLHC=m # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set @@ -770,6 +803,7 @@ CONFIG_PPP_MPPE=m # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set # # Userland interfaces @@ -789,22 +823,27 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_ATKBD=m # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=y +CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_UCB1400=y CONFIG_INPUT_MISC=y CONFIG_INPUT_UINPUT=m @@ -823,6 +862,7 @@ CONFIG_SERIO_LIBPS2=y CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -862,15 +902,12 @@ CONFIG_SA1100_WATCHDOG=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set +CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # -# Ftape, the floppy tape device driver -# - -# # PCMCIA character devices # # CONFIG_SYNCLINK_CS is not set @@ -882,7 +919,6 @@ CONFIG_SA1100_WATCHDOG=y # TPM devices # # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set # # I2C support @@ -902,6 +938,7 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_PXA=y CONFIG_I2C_PXA_SLAVE=y +# CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set # CONFIG_I2C_PCA_ISA is not set @@ -911,7 +948,7 @@ CONFIG_I2C_PXA_SLAVE=y # # CONFIG_SENSORS_DS1337 is not set # CONFIG_SENSORS_DS1374 is not set -CONFIG_SENSORS_EEPROM=m +# CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set @@ -924,18 +961,8 @@ CONFIG_SENSORS_EEPROM=m # # SPI support # -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -CONFIG_SPI_PXA2XX=m - -# -# SPI Protocol Masters -# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # # Dallas's 1-wire bus @@ -947,9 +974,11 @@ CONFIG_SPI_PXA2XX=m # CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ASB100 is not set @@ -973,10 +1002,15 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set @@ -987,16 +1021,15 @@ CONFIG_HWMON=y # # -# Multimedia Capabilities Port drivers +# Multifunction device drivers # -CONFIG_UCB1400=y -CONFIG_UCB1400_TS=y +# CONFIG_MFD_SM501 is not set # # LED devices # CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS is not set # # LED drivers @@ -1007,13 +1040,13 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_IDE_DISK=y +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y # # Multimedia devices # # CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y # # Digital Video Broadcasting Devices @@ -1024,17 +1057,28 @@ CONFIG_VIDEO_V4L2=y # # Graphics support # +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_LCD_CLASS_DEVICE=y CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set -CONFIG_FB_FIRMWARE_EDID=y +# CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set CONFIG_FB_PXA=y # CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set # CONFIG_FB_VIRTUAL is not set # @@ -1063,11 +1107,6 @@ CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_DEVICE=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_DEVICE=y # # Sound @@ -1082,7 +1121,7 @@ CONFIG_SND_TIMER=y CONFIG_SND_PCM=y CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m -CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQUENCER=y # CONFIG_SND_SEQ_DUMMY is not set CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y @@ -1093,13 +1132,14 @@ CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y -# CONFIG_SND_DEBUG is not set +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +# CONFIG_SND_PCM_XRUN_DEBUG is not set # # Generic devices # CONFIG_SND_AC97_CODEC=y -CONFIG_SND_AC97_BUS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_VIRMIDI is not set # CONFIG_SND_MTPAV is not set @@ -1124,9 +1164,32 @@ CONFIG_SND_USB_AUDIO=m # CONFIG_SND_PDAUDIOCF is not set # +# SoC audio support +# +# CONFIG_SND_SOC is not set + +# # Open Sound System # # CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set # # USB support @@ -1141,7 +1204,7 @@ CONFIG_USB=y # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set @@ -1151,7 +1214,8 @@ CONFIG_USB_DEVICEFS=y # # CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SL811_HCD is not set @@ -1179,38 +1243,25 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_LIBUSUAL is not set # # USB Input Devices # -CONFIG_USB_HID=m -CONFIG_USB_HIDINPUT=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -# CONFIG_USB_HIDDEV is not set - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set # CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set -CONFIG_USB_TOUCHSCREEN=m -# CONFIG_USB_TOUCHSCREEN_EGALAX is not set -# CONFIG_USB_TOUCHSCREEN_PANJIT is not set -# CONFIG_USB_TOUCHSCREEN_3M is not set -# CONFIG_USB_TOUCHSCREEN_ITM is not set +# CONFIG_USB_TOUCHSCREEN is not set # CONFIG_USB_YEALINK is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set # CONFIG_USB_ATI_REMOTE2 is not set # CONFIG_USB_KEYSPAN_REMOTE is not set # CONFIG_USB_APPLETOUCH is not set +# CONFIG_USB_GTCO is not set # # USB Imaging devices @@ -1225,9 +1276,9 @@ CONFIG_USB_TOUCHSCREEN=m # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set # CONFIG_USB_USBNET is not set -# CONFIG_USB_ZD1201 is not set -CONFIG_USB_MON=y +# CONFIG_USB_MON is not set # # USB port drivers @@ -1236,23 +1287,66 @@ CONFIG_USB_MON=y # # USB Serial Converter support # -# CONFIG_USB_SERIAL is not set +CONFIG_USB_SERIAL=m +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_AIRPRIME is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set # CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETKIT is not set -# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # @@ -1262,9 +1356,10 @@ CONFIG_USB_MON=y # # USB Gadget Support # -CONFIG_USB_GADGET=y +CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_PXA2XX is not set # CONFIG_USB_GADGET_GOKU is not set @@ -1272,15 +1367,14 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_OMAP is not set # CONFIG_USB_GADGET_AT91 is not set CONFIG_USB_GADGET_DUMMY_HCD=y -CONFIG_USB_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set # # MMC/SD Card support @@ -1295,8 +1389,8 @@ CONFIG_MMC_PXA=y # CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set # # RTC interfaces @@ -1304,17 +1398,25 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # # RTC drivers # +# CONFIG_RTC_DRV_CMOS is not set # CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_PCF8563 is not set +CONFIG_RTC_DRV_PCF8583=m # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_M48T86 is not set CONFIG_RTC_DRV_SA1100=y # CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set # # File systems @@ -1328,6 +1430,7 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y @@ -1335,10 +1438,12 @@ CONFIG_FS_MBCACHE=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -1365,8 +1470,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set @@ -1376,18 +1483,17 @@ CONFIG_RAMFS=y # # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS_FS=y -CONFIG_JFFS_FS_VERBOSE=0 -CONFIG_JFFS_PROC_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y @@ -1407,20 +1513,18 @@ CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y +# CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y +# CONFIG_NFSD_V3_ACL is not set CONFIG_NFSD_V4=y CONFIG_NFSD_TCP=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y @@ -1430,7 +1534,9 @@ CONFIG_SMB_FS=m # CONFIG_SMB_NLS_DEFAULT is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_EXPERIMENTAL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1504,22 +1610,28 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=m # +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# # Profiling support # -CONFIG_PROFILING=y -CONFIG_OPROFILE=y +# CONFIG_PROFILING is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_FS is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set CONFIG_DEBUG_USER=y # @@ -1531,22 +1643,31 @@ CONFIG_SECURITY=y # CONFIG_SECURITY_NETWORK is not set CONFIG_SECURITY_CAPABILITIES=y # CONFIG_SECURITY_ROOTPLUG is not set -# CONFIG_SECURITY_SECLVL is not set # # Cryptographic options # CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_MD4=y +# CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_SERPENT is not set @@ -1554,12 +1675,13 @@ CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_TEA is not set -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_ANUBIS is not set CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set # @@ -1569,6 +1691,7 @@ CONFIG_CRYPTO_CRC32C=y # # Library routines # +CONFIG_BITREVERSE=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC32=y @@ -1577,3 +1700,6 @@ CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_DEC16=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 4779f474f91..9179e822031 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -76,6 +76,7 @@ EXPORT_SYMBOL(__const_udelay); /* networking */ EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_from_user); EXPORT_SYMBOL(csum_partial_copy_nocheck); EXPORT_SYMBOL(__csum_ipv6_magic); diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index bdbd7da9928..f56d48c451e 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -41,11 +41,11 @@ #include <linux/init.h> #include <linux/mutex.h> #include <linux/kthread.h> +#include <linux/io.h> #include <asm/dma.h> #include <asm/ecard.h> #include <asm/hardware.h> -#include <asm/io.h> #include <asm/irq.h> #include <asm/mmu_context.h> #include <asm/mach/irq.h> @@ -958,6 +958,31 @@ void ecard_release_resources(struct expansion_card *ec) } EXPORT_SYMBOL(ecard_release_resources); +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data) +{ + ec->irq_data = irq_data; + barrier(); + ec->ops = ops; +} +EXPORT_SYMBOL(ecard_setirq); + +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize) +{ + unsigned long start = ecard_resource_start(ec, res); + unsigned long end = ecard_resource_end(ec, res); + + if (offset > (end - start)) + return NULL; + + start += offset; + if (maxsize && end - start > maxsize) + end = start + maxsize; + + return devm_ioremap(&ec->dev, start, end - start); +} +EXPORT_SYMBOL(ecardm_iomap); + /* * Probe for an expansion card. * @@ -1133,6 +1158,14 @@ static int ecard_drv_remove(struct device *dev) drv->remove(ec); ecard_release(ec); + /* + * Restore the default operations. We ensure that the + * ops are set before we change the data. + */ + ec->ops = &ecard_default_ops; + barrier(); + ec->irq_data = NULL; + return 0; } diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 77ef35efaa8..398d0c0511e 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -52,21 +52,15 @@ static int save_trace(struct stackframe *frame, void *d) return trace->nr_entries >= trace->max_entries; } -void save_stack_trace(struct stack_trace *trace, struct task_struct *task) +void save_stack_trace(struct stack_trace *trace) { struct stack_trace_data data; unsigned long fp, base; data.trace = trace; data.skip = trace->skip; - - if (task) { - base = (unsigned long)task_stack_page(task); - fp = 0; /* FIXME */ - } else { - base = (unsigned long)task_stack_page(current); - asm("mov %0, fp" : "=r" (fp)); - } + base = (unsigned long)task_stack_page(current); + asm("mov %0, fp" : "=r" (fp)); walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); } diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index d0540e4eaf5..1533d3ecd7a 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -512,7 +512,7 @@ void __init time_init(void) #ifdef CONFIG_NO_IDLE_HZ if (system_timer->dyn_tick) - system_timer->dyn_tick->lock = SPIN_LOCK_UNLOCKED; + spin_lock_init(&system_timer->dyn_tick->lock); #endif } diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 018d637f87f..a31157f1655 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -17,6 +17,9 @@ config ARCH_AT91SAM9261 config ARCH_AT91SAM9263 bool "AT91SAM9263" +config ARCH_AT91SAM9RL + bool "AT91SAM9RL" + endchoice # ---------------------------------------------------------- @@ -152,6 +155,20 @@ endif # ---------------------------------------------------------- +if ARCH_AT91SAM9RL + +comment "AT91SAM9RL Board Type" + +config MACH_AT91SAM9RLEK + bool "Atmel AT91SAM9RL-EK Evaluation Kit" + depends on ARCH_AT91SAM9RL + help + Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a412ae18a42..a4d80eb056e 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o # AT91RM9200 board-specific support obj-$(CONFIG_MACH_ONEARM) += board-1arm.o @@ -36,9 +37,13 @@ obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o # AT91SAM9263 board-specific support obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o +# AT91SAM9RL board-specific support +obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o + # LEDs support led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o led-$(CONFIG_MACH_AT91RM9200EK) += leds.o +led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o led-$(CONFIG_MACH_CSB337) += leds.o led-$(CONFIG_MACH_CSB637) += leds.o led-$(CONFIG_MACH_KB9200) += leds.o diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 2624a4f22d6..70599bcf451 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -22,9 +22,6 @@ #include "generic.h" -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 40586e22cd3..ffd3154c1e5 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -22,9 +22,6 @@ #include "generic.h" -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 8e781997716..9db58da0475 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -23,9 +23,6 @@ #include "generic.h" -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 2b2e18a6712..635695787f9 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -22,9 +22,6 @@ #include "generic.h" -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c new file mode 100644 index 00000000000..4813a35f6cf --- /dev/null +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -0,0 +1,341 @@ +/* + * arch/arm/mach-at91/at91sam9rl.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include <linux/module.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/arch/cpu.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> + +#include "generic.h" +#include "clock.h" + +static struct map_desc at91sam9rl_io_desc[] __initdata = { + { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_16K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc at91sam9rl_sram_desc[] __initdata = { + { + .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), + .type = MT_DEVICE, + } +}; + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi1_clk = { + .name = "twi1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi_clk = { + .name = "spi_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SPI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc0_clk = { + .name = "tc0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc1_clk = { + .name = "tc1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc2_clk = { + .name = "tc2_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pwmc_clk = { + .name = "pwmc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tsc_clk = { + .name = "tsc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TSC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma_clk = { + .name = "dma_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_DMA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ac97_clk = { + .name = "ac97_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &mmc_clk, + &twi0_clk, + &twi1_clk, + &spi_clk, + &ssc0_clk, + &ssc1_clk, + &tc0_clk, + &tc1_clk, + &tc2_clk, + &pwmc_clk, + &tsc_clk, + &dma_clk, + &udphs_clk, + &lcdc_clk, + &ac97_clk, + // irq0 +}; + +/* + * The two programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static void __init at91sam9rl_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9rl_gpio[] = { + { + .id = AT91SAM9RL_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9RL_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9RL_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + }, { + .id = AT91SAM9RL_ID_PIOD, + .offset = AT91_PIOD, + .clock = &pioD_clk, + } +}; + +static void at91sam9rl_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + + +/* -------------------------------------------------------------------- + * AT91SAM9RL processor initialization + * -------------------------------------------------------------------- */ + +void __init at91sam9rl_initialize(unsigned long main_clock) +{ + unsigned long cidr, sram_size; + + /* Map peripherals */ + iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); + + cidr = at91_sys_read(AT91_DBGU_CIDR); + + switch (cidr & AT91_CIDR_SRAMSIZ) { + case AT91_CIDR_SRAMSIZ_32K: + sram_size = 2 * SZ_16K; + break; + case AT91_CIDR_SRAMSIZ_16K: + default: + sram_size = SZ_16K; + } + + at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; + at91sam9rl_sram_desc->length = sram_size; + + /* Map SRAM */ + iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); + + at91_arch_reset = at91sam9rl_reset; + at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); + + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91sam9rl_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9rl_gpio, 4); +} + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller */ + 7, /* System Peripherals */ + 1, /* Parallel IO Controller A */ + 1, /* Parallel IO Controller B */ + 1, /* Parallel IO Controller C */ + 1, /* Parallel IO Controller D */ + 5, /* USART 0 */ + 5, /* USART 1 */ + 5, /* USART 2 */ + 5, /* USART 3 */ + 0, /* Multimedia Card Interface */ + 6, /* Two-Wire Interface 0 */ + 6, /* Two-Wire Interface 1 */ + 5, /* Serial Peripheral Interface */ + 4, /* Serial Synchronous Controller 0 */ + 4, /* Serial Synchronous Controller 1 */ + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 0, + 0, /* Touch Screen Controller */ + 0, /* DMA Controller */ + 2, /* USB Device High speed port */ + 2, /* LCD Controller */ + 6, /* AC97 Controller */ + 0, + 0, + 0, + 0, + 0, + 0, + 0, /* Advanced Interrupt Controller */ +}; + +void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91sam9rl_default_irq_priority; + + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c new file mode 100644 index 00000000000..cd7532bcd4e --- /dev/null +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -0,0 +1,630 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <linux/platform_device.h> +#include <linux/fb.h> + +#include <video/atmel_lcdc.h> + +#include <asm/arch/board.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/at91sam9rl_matrix.h> +#include <asm/arch/at91sam926x_mc.h> + +#include "generic.h" + + +/* -------------------------------------------------------------------- + * MMC / SD + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) +static u64 mmc_dmamask = 0xffffffffUL; +static struct at91_mmc_data mmc_data; + +static struct resource mmc_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_MCI, + .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_MCI, + .end = AT91SAM9RL_ID_MCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9rl_mmc_device = { + .name = "at91_mci", + .id = -1, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mmc_data, + }, + .resource = mmc_resources, + .num_resources = ARRAY_SIZE(mmc_resources), +}; + +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) +{ + if (!data) + return; + + /* input/irq */ + if (data->det_pin) { + at91_set_gpio_input(data->det_pin, 1); + at91_set_deglitch(data->det_pin, 1); + } + if (data->wp_pin) + at91_set_gpio_input(data->wp_pin, 1); + if (data->vcc_pin) + at91_set_gpio_output(data->vcc_pin, 0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA2, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA0, 1); + if (data->wire4) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + + mmc_data = *data; + platform_device_register(&at91sam9rl_mmc_device); +} +#else +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) +static struct at91_nand_data nand_data; + +#define NAND_BASE AT91_CHIPSELECT_3 + +static struct resource nand_resources[] = { + { + .start = NAND_BASE, + .end = NAND_BASE + SZ_256M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device at91_nand_device = { + .name = "at91_nand", + .id = -1, + .dev = { + .platform_data = &nand_data, + }, + .resource = nand_resources, + .num_resources = ARRAY_SIZE(nand_resources), +}; + +void __init at91_add_device_nand(struct at91_nand_data *data) +{ + unsigned long csa; + + if (!data) + return; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* set the bus interface characteristics */ + at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) + | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + + at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) + | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); + + at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + + at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ + + nand_data = *data; + platform_device_register(&at91_nand_device); +} + +#else +void __init at91_add_device_nand(struct at91_nand_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * TWI (i2c) + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) + +static struct resource twi_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_TWI0, + .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_TWI0, + .end = AT91SAM9RL_ID_TWI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9rl_twi_device = { + .name = "at91_i2c", + .id = -1, + .resource = twi_resources, + .num_resources = ARRAY_SIZE(twi_resources), +}; + +void __init at91_add_device_i2c(void) +{ + /* pins used for TWI interface */ + at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ + at91_set_multi_drive(AT91_PIN_PA23, 1); + + at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ + at91_set_multi_drive(AT91_PIN_PA24, 1); + + platform_device_register(&at91sam9rl_twi_device); +} +#else +void __init at91_add_device_i2c(void) {} +#endif + + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) +static u64 spi_dmamask = 0xffffffffUL; + +static struct resource spi_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_SPI, + .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_SPI, + .end = AT91SAM9RL_ID_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9rl_spi_device = { + .name = "atmel_spi", + .id = 0, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi_resources, + .num_resources = ARRAY_SIZE(spi_resources), +}; + +static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 }; + + +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) +{ + int i; + unsigned long cs_pin; + + at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */ + + /* Enable SPI chip-selects */ + for (i = 0; i < nr_devices; i++) { + if (devices[i].controller_data) + cs_pin = (unsigned long) devices[i].controller_data; + else + cs_pin = spi_standard_cs[devices[i].chip_select]; + + /* enable chip-select pin */ + at91_set_gpio_output(cs_pin, 1); + + /* pass chip-select pin to driver */ + devices[i].controller_data = (void *) cs_pin; + } + + spi_register_board_info(devices, nr_devices); + platform_device_register(&at91sam9rl_spi_device); +} +#else +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} +#endif + + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) +static u64 lcdc_dmamask = 0xffffffffUL; +static struct atmel_lcdfb_info lcdc_data; + +static struct resource lcdc_resources[] = { + [0] = { + .start = AT91SAM9RL_LCDC_BASE, + .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_LCDC, + .end = AT91SAM9RL_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, +#if defined(CONFIG_FB_INTSRAM) + [2] = { + .start = AT91SAM9RL_SRAM_BASE, + .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device at91_lcdc_device = { + .name = "atmel_lcdfb", + .id = 0, + .dev = { + .dma_mask = &lcdc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &lcdc_data, + }, + .resource = lcdc_resources, + .num_resources = ARRAY_SIZE(lcdc_resources), +}; + +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) +{ + if (!data) { + return; + } + + at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ + at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ + at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ + at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ + at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ + at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ + at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ + + lcdc_data = *data; + platform_device_register(&at91_lcdc_device); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} +#endif + + +/* -------------------------------------------------------------------- + * LEDs + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_LEDS) +u8 at91_leds_cpu; +u8 at91_leds_timer; + +void __init at91_init_leds(u8 cpu_led, u8 timer_led) +{ + /* Enable GPIO to access the LEDs */ + at91_set_gpio_output(cpu_led, 1); + at91_set_gpio_output(timer_led, 1); + + at91_leds_cpu = cpu_led; + at91_leds_timer = timer_led; +} +#else +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} +#endif + + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SERIAL_ATMEL) +static struct resource dbgu_resources[] = { + [0] = { + .start = AT91_VA_BASE_SYS + AT91_DBGU, + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data dbgu_data = { + .use_dma_tx = 0, + .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), +}; + +static struct platform_device at91sam9rl_dbgu_device = { + .name = "atmel_usart", + .id = 0, + .dev = { + .platform_data = &dbgu_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = dbgu_resources, + .num_resources = ARRAY_SIZE(dbgu_resources), +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ +} + +static struct resource uart0_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_US0, + .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_US0, + .end = AT91SAM9RL_ID_US0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart0_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9rl_uart0_device = { + .name = "atmel_usart", + .id = 1, + .dev = { + .platform_data = &uart0_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart0_resources, + .num_resources = ARRAY_SIZE(uart0_resources), +}; + +static inline void configure_usart0_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */ +} + +static struct resource uart1_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_US1, + .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_US1, + .end = AT91SAM9RL_ID_US1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart1_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9rl_uart1_device = { + .name = "atmel_usart", + .id = 2, + .dev = { + .platform_data = &uart1_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart1_resources, + .num_resources = ARRAY_SIZE(uart1_resources), +}; + +static inline void configure_usart1_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ +} + +static struct resource uart2_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_US2, + .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_US2, + .end = AT91SAM9RL_ID_US2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart2_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9rl_uart2_device = { + .name = "atmel_usart", + .id = 3, + .dev = { + .platform_data = &uart2_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart2_resources, + .num_resources = ARRAY_SIZE(uart2_resources), +}; + +static inline void configure_usart2_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ +} + +static struct resource uart3_resources[] = { + [0] = { + .start = AT91SAM9RL_BASE_US3, + .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9RL_ID_US3, + .end = AT91SAM9RL_ID_US3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart3_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9rl_uart3_device = { + .name = "atmel_usart", + .id = 4, + .dev = { + .platform_data = &uart3_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart3_resources, + .num_resources = ARRAY_SIZE(uart3_resources), +}; + +static inline void configure_usart3_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */ +} + +struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ +struct platform_device *atmel_default_console_device; /* the serial console device */ + +void __init at91_init_serial(struct at91_uart_config *config) +{ + int i; + + /* Fill in list of supported UARTs */ + for (i = 0; i < config->nr_tty; i++) { + switch (config->tty_map[i]) { + case 0: + configure_usart0_pins(); + at91_uarts[i] = &at91sam9rl_uart0_device; + at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart"); + break; + case 1: + configure_usart1_pins(); + at91_uarts[i] = &at91sam9rl_uart1_device; + at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart"); + break; + case 2: + configure_usart2_pins(); + at91_uarts[i] = &at91sam9rl_uart2_device; + at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart"); + break; + case 3: + configure_usart3_pins(); + at91_uarts[i] = &at91sam9rl_uart3_device; + at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart"); + break; + case 4: + configure_dbgu_pins(); + at91_uarts[i] = &at91sam9rl_dbgu_device; + at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart"); + break; + default: + continue; + } + at91_uarts[i]->id = i; /* update ID number to mapped ID */ + } + + /* Set serial console device */ + if (config->console_tty < ATMEL_MAX_UART) + atmel_default_console_device = at91_uarts[config->console_tty]; + if (!atmel_default_console_device) + printk(KERN_INFO "AT91: No default serial console defined.\n"); +} + +void __init at91_add_device_serial(void) +{ + int i; + + for (i = 0; i < ATMEL_MAX_UART; i++) { + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +} +#else +void __init at91_init_serial(struct at91_uart_config *config) {} +void __init at91_add_device_serial(void) {} +#endif + + +/* -------------------------------------------------------------------- */ + +/* + * These devices are always present and don't need any board-specific + * setup. + */ +static int __init at91_add_standard_devices(void) +{ + return 0; +} + +arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index bcf71536cc6..1f0c8a400b3 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -60,6 +60,9 @@ static void __init ek_map_io(void) /* Initialize processor: 18.432 MHz crystal */ at91sam9261_initialize(18432000); + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); + /* Setup the serial ports and console */ at91_init_serial(&ek_uart_config); } diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c new file mode 100644 index 00000000000..30c79aca84d --- /dev/null +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2005 SAN People + * Copyright (C) 2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/fb.h> +#include <linux/clk.h> + +#include <video/atmel_lcdc.h> + +#include <asm/hardware.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/irq.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/arch/board.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91sam926x_mc.h> + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata ek_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init ek_map_io(void) +{ + /* Initialize processor: 12.000 MHz crystal */ + at91sam9rl_initialize(12000000); + + /* Setup the serial ports and console */ + at91_init_serial(&ek_uart_config); +} + +static void __init ek_init_irq(void) +{ + at91sam9rl_init_interrupts(NULL); +} + + +/* + * MCI (SD/MMC) + */ +static struct at91_mmc_data __initdata ek_mmc_data = { + .wire4 = 1, + .det_pin = AT91_PIN_PA15, +// .wp_pin = ... not connected +// .vcc_pin = ... not connected +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Partition 1", + .offset = 0, + .size = 256 * 1024, + }, + { + .name = "Partition 2", + .offset = 256 * 1024 , + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +static struct at91_nand_data __initdata ek_nand_data = { + .ale = 21, + .cle = 22, +// .det_pin = ... not connected + .rdy_pin = AT91_PIN_PD17, + .enable_pin = AT91_PIN_PB6, + .partition_info = nand_partitions, + .bus_width_16 = 0, +}; + + +/* + * SPI devices + */ +static struct spi_board_info ek_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +}; + + +/* + * LCD Controller + */ +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static struct fb_monspecs at91fb_default_monspecs = { + .manufacturer = "HIT", + .monitor = "TX09D50VM1CCA", + + .modedb = at91_tft_vga_modes, + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), + .hfmin = 15000, + .hfmax = 64000, + .vfmin = 50, + .vfmax = 150, +}; + +#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + if (on) + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ + else + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ +} + +/* Driver datas */ +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, + .default_monspecs = &at91fb_default_monspecs, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .guard_time = 1, +}; + +#else +static struct atmel_lcdfb_info __initdata ek_lcdc_data; +#endif + + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* I2C */ + at91_add_device_i2c(); + /* NAND */ + at91_add_device_nand(&ek_nand_data); + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + /* MMC */ + at91_add_device_mmc(0, &ek_mmc_data); + /* LCD Controller */ + at91_add_device_lcdc(&ek_lcdc_data); +} + +MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") + /* Maintainer: Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index bda26221c52..68ed71a3e6c 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned shor extern void __init at91sam9260_initialize(unsigned long main_clock); extern void __init at91sam9261_initialize(unsigned long main_clock); extern void __init at91sam9263_initialize(unsigned long main_clock); +extern void __init at91sam9rl_initialize(unsigned long main_clock); /* Interrupts */ extern void __init at91rm9200_init_interrupts(unsigned int priority[]); extern void __init at91sam9260_init_interrupts(unsigned int priority[]); extern void __init at91sam9261_init_interrupts(unsigned int priority[]); extern void __init at91sam9263_init_interrupts(unsigned int priority[]); +extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); extern void __init at91_aic_init(unsigned int priority[]); /* Timer */ diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig new file mode 100644 index 00000000000..bac988e7a4c --- /dev/null +++ b/arch/arm/mach-davinci/Kconfig @@ -0,0 +1,23 @@ +if ARCH_DAVINCI + +menu "TI DaVinci Implementations" + +comment "DaVinci Core Type" + +config ARCH_DAVINCI644x + default y + bool "DaVinci 644x based system" + +comment "DaVinci Board Type" + +config MACH_DAVINCI_EVM + bool "TI DaVinci EVM" + default y + depends on ARCH_DAVINCI644x + help + Configure this option to specify the whether the board used + for development is a DaVinci EVM + +endmenu + +endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile new file mode 100644 index 00000000000..a8f88cd2990 --- /dev/null +++ b/arch/arm/mach-davinci/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# +# + +# Common objects +obj-y := time.o irq.o serial.o io.o id.o psc.o + +# Board specific +obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot new file mode 100644 index 00000000000..e1dd366f836 --- /dev/null +++ b/arch/arm/mach-davinci/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c new file mode 100644 index 00000000000..633c12e4304 --- /dev/null +++ b/arch/arm/mach-davinci/board-evm.c @@ -0,0 +1,131 @@ +/* + * TI DaVinci EVM board support + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> + +#include <asm/setup.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/hardware.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <asm/arch/common.h> + +/* other misc. init functions */ +void __init davinci_psc_init(void); +void __init davinci_irq_init(void); +void __init davinci_map_common_io(void); + +/* NOR Flash base address set to CS0 by default */ +#define NOR_FLASH_PHYS 0x02000000 + +static struct mtd_partition davinci_evm_partitions[] = { + /* bootloader (U-Boot, etc) in first 4 sectors */ + { + .name = "bootloader", + .offset = 0, + .size = 4 * SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next 1 sectors */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct physmap_flash_data davinci_evm_flash_data = { + .width = 2, + .parts = davinci_evm_partitions, + .nr_parts = ARRAY_SIZE(davinci_evm_partitions), +}; + +/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF + * limits addresses to 16M, so using addresses past 16M will wrap */ +static struct resource davinci_evm_flash_resource = { + .start = NOR_FLASH_PHYS, + .end = NOR_FLASH_PHYS + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device davinci_evm_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &davinci_evm_flash_data, + }, + .num_resources = 1, + .resource = &davinci_evm_flash_resource, +}; + +static struct platform_device *davinci_evm_devices[] __initdata = { + &davinci_evm_flash_device, +}; + +static void __init +davinci_evm_map_io(void) +{ + davinci_map_common_io(); +} + +static __init void davinci_evm_init(void) +{ + davinci_psc_init(); + +#if defined(CONFIG_BLK_DEV_DAVINCI) || defined(CONFIG_BLK_DEV_DAVINCI_MODULE) + printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " + "but share pins.\n\t Disable IDE for NOR support.\n"); +#endif + + platform_add_devices(davinci_evm_devices, + ARRAY_SIZE(davinci_evm_devices)); +} + +static __init void davinci_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_EVM, "DaVinci EVM") + /* Maintainer: MontaVista Software <source@mvista.com> */ + .phys_io = IO_PHYS, + .io_pg_offst = (io_p2v(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DAVINCI_DDR_BASE + 0x100), + .map_io = davinci_evm_map_io, + .init_irq = davinci_evm_irq_init, + .timer = &davinci_timer, + .init_machine = davinci_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c new file mode 100644 index 00000000000..70608f76aed --- /dev/null +++ b/arch/arm/mach-davinci/id.c @@ -0,0 +1,94 @@ +/* + * Davinci CPU identification code + * + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> + * + * Derived from OMAP1 CPU identification code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/io.h> + +#define JTAG_ID_BASE 0x01c40028 + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u32 manufacturer; /* JTAG ID bits 11:1 */ + u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */ +}; + +/* Register values to detect the DaVinci version */ +static struct davinci_id davinci_ids[] __initdata = { + { + /* DM6446 */ + .part_no = 0xb700, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64460000, + }, +}; + +/* + * Get Device Part No. from JTAG ID register + */ +static u16 __init davinci_get_part_no(void) +{ + u32 dev_id, part_no; + + dev_id = davinci_readl(JTAG_ID_BASE); + + part_no = ((dev_id >> 12) & 0xffff); + + return part_no; +} + +/* + * Get Device Revision from JTAG ID register + */ +static u8 __init davinci_get_variant(void) +{ + u32 variant; + + variant = davinci_readl(JTAG_ID_BASE); + + variant = (variant >> 28) & 0xf; + + return variant; +} + +void __init davinci_check_revision(void) +{ + int i; + u16 part_no; + u8 variant; + + part_no = davinci_get_part_no(); + variant = davinci_get_variant(); + + /* First check only the major version in a safe way */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == (davinci_ids[i].part_no)) { + system_rev = davinci_ids[i].type; + break; + } + } + + /* Check if we can find the dev revision */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == davinci_ids[i].part_no && + variant == davinci_ids[i].variant) { + system_rev = davinci_ids[i].type; + break; + } + } + + printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); +} diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c new file mode 100644 index 00000000000..87fae6fb6ec --- /dev/null +++ b/arch/arm/mach-davinci/io.c @@ -0,0 +1,51 @@ +/* + * DaVinci I/O mapping code + * + * Copyright (C) 2005-2006 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/tlb.h> +#include <asm/io.h> +#include <asm/memory.h> + +#include <asm/mach/map.h> + +extern void davinci_check_revision(void); + +/* + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. + */ +static struct map_desc davinci_io_desc[] __initdata = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, +}; + +void __init davinci_map_common_io(void) +{ + iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc)); + + /* Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + /* We want to check CPU revision early for cpu_is_xxxx() macros. + * IO space mapping must be initialized before we can do that. + */ + davinci_check_revision(); +} diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c new file mode 100644 index 00000000000..1333d84d2e4 --- /dev/null +++ b/arch/arm/mach-davinci/irq.c @@ -0,0 +1,226 @@ +/* + * Interrupt handler for DaVinci boards. + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/mach/irq.h> + +#define IRQ_BIT(irq) ((irq) & 0x1f) + +#define FIQ_REG0_OFFSET 0x0000 +#define FIQ_REG1_OFFSET 0x0004 +#define IRQ_REG0_OFFSET 0x0008 +#define IRQ_REG1_OFFSET 0x000C +#define IRQ_ENT_REG0_OFFSET 0x0018 +#define IRQ_ENT_REG1_OFFSET 0x001C +#define IRQ_INCTL_REG_OFFSET 0x0020 +#define IRQ_EABASE_REG_OFFSET 0x0024 +#define IRQ_INTPRI0_REG_OFFSET 0x0030 +#define IRQ_INTPRI7_REG_OFFSET 0x004C + +static inline unsigned int davinci_irq_readl(int offset) +{ + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); +} + +static inline void davinci_irq_writel(unsigned long value, int offset) +{ + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); +} + +/* Disable interrupt */ +static void davinci_mask_irq(unsigned int irq) +{ + unsigned int mask; + u32 l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } +} + +/* Enable interrupt */ +static void davinci_unmask_irq(unsigned int irq) +{ + unsigned int mask; + u32 l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } +} + +/* EOI interrupt */ +static void davinci_ack_irq(unsigned int irq) +{ + unsigned int mask; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) + davinci_irq_writel(mask, IRQ_REG1_OFFSET); + else + davinci_irq_writel(mask, IRQ_REG0_OFFSET); +} + +static struct irq_chip davinci_irq_chip_0 = { + .name = "AINTC", + .ack = davinci_ack_irq, + .mask = davinci_mask_irq, + .unmask = davinci_unmask_irq, +}; + + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [7] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_VLCDINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_EMACINT] = 4, + [14] = 7, + [15] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_PSCIN] = 7, + [21] = 7, + [IRQ_IDE] = 4, + [23] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_SDIOINT] = 7, + [28] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_VLQINT] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_UARTINT2] = 3, + [IRQ_SPINT0] = 3, + [IRQ_SPINT1] = 3, + [45] = 7, + [IRQ_DSP2ARM0] = 4, + [IRQ_DSP2ARM1] = 4, + [IRQ_GPIO0] = 7, + [IRQ_GPIO1] = 7, + [IRQ_GPIO2] = 7, + [IRQ_GPIO3] = 7, + [IRQ_GPIO4] = 7, + [IRQ_GPIO5] = 7, + [IRQ_GPIO6] = 7, + [IRQ_GPIO7] = 7, + [IRQ_GPIOBNK0] = 7, + [IRQ_GPIOBNK1] = 7, + [IRQ_GPIOBNK2] = 7, + [IRQ_GPIOBNK3] = 7, + [IRQ_GPIOBNK4] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +/* ARM Interrupt Controller Initialization */ +void __init davinci_irq_init(void) +{ + unsigned i; + const u8 *priority = default_priorities; + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + /* Disable all interrupts */ + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + + /* Interrupts disabled immediately, IRQ entry reflects all */ + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + + /* we don't use the hardware vector table, just its entry addresses */ + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + unsigned j; + u32 pri; + + for (j = 0, pri = 0; j < 32; j += 4, priority++) + pri |= (*priority & 0x07) << j; + davinci_irq_writel(pri, i); + } + + /* set up genirq dispatch for ARM INTC */ + for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { + set_irq_chip(i, &davinci_irq_chip_0); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + if (i != IRQ_TINT1_TINT34) + set_irq_handler(i, handle_edge_irq); + else + set_irq_handler(i, handle_level_irq); + } +} diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c new file mode 100644 index 00000000000..e1b0050283a --- /dev/null +++ b/arch/arm/mach-davinci/psc.c @@ -0,0 +1,113 @@ +/* + * TI DaVinci Power and Sleep Controller (PSC) + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> + +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/arch/psc.h> + +#define PTCMD __REG(0x01C41120) +#define PDSTAT __REG(0x01C41200) +#define PDCTL1 __REG(0x01C41304) +#define EPCPR __REG(0x01C41070) +#define PTSTAT __REG(0x01C41128) + +#define MDSTAT IO_ADDRESS(0x01C41800) +#define MDCTL IO_ADDRESS(0x01C41A00) + +#define PINMUX0 __REG(0x01c40000) +#define PINMUX1 __REG(0x01c40004) +#define VDD3P3V_PWDN __REG(0x01C40048) + +static void davinci_psc_mux(unsigned int id) +{ + switch (id) { + case DAVINCI_LPSC_ATA: + PINMUX0 |= (1 << 17) | (1 << 16); + break; + case DAVINCI_LPSC_MMC_SD: + /* VDD power manupulations are done in U-Boot for CPMAC + * so applies to MMC as well + */ + /*Set up the pull regiter for MMC */ + VDD3P3V_PWDN = 0x0; + PINMUX1 &= (~(1 << 9)); + break; + case DAVINCI_LPSC_I2C: + PINMUX1 |= (1 << 7); + break; + case DAVINCI_LPSC_McBSP: + PINMUX1 |= (1 << 10); + break; + default: + break; + } +} + +/* Enable or disable a PSC domain */ +void davinci_psc_config(unsigned int domain, unsigned int id, char enable) +{ + volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); + volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); + + if (id < 0) + return; + + if (enable) + *mdctl |= 0x00000003; /* Enable Module */ + else + *mdctl &= 0xFFFFFFF2; /* Disable Module */ + + if ((PDSTAT & 0x00000001) == 0) { + PDCTL1 |= 0x1; + PTCMD = (1 << domain); + while ((((EPCPR >> domain) & 1) == 0)); + + PDCTL1 |= 0x100; + while (!(((PTSTAT >> domain) & 1) == 0)); + } else { + PTCMD = (1 << domain); + while (!(((PTSTAT >> domain) & 1) == 0)); + } + + if (enable) + while (!((*mdstat & 0x0000001F) == 0x3)); + else + while (!((*mdstat & 0x0000001F) == 0x2)); + + if (enable) + davinci_psc_mux(id); +} + +void __init davinci_psc_init(void) +{ + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); + + /* Turn on WatchDog timer LPSC. Needed for RESET to work */ + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1); +} diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c new file mode 100644 index 00000000000..8368c93c788 --- /dev/null +++ b/arch/arm/mach-davinci/serial.c @@ -0,0 +1,96 @@ +/* + * TI DaVinci serial driver + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/serial_8250.h> +#include <linux/serial_reg.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/clk.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/hardware.h> +#include <asm/arch/serial.h> +#include <asm/arch/irqs.h> + +#define UART_DAVINCI_PWREMU 0x0c + +static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up, + int offset) +{ + offset <<= up->regshift; + return (unsigned int)__raw_readb(up->membase + offset); +} + +static inline void davinci_serial_outp(struct plat_serial8250_port *p, + int offset, int value) +{ + offset <<= p->regshift; + __raw_writeb(value, p->membase + offset); +} + +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), + .mapbase = (unsigned long)DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 27000000, + }, + { + .flags = 0 + }, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static void __init davinci_serial_reset(struct plat_serial8250_port *p) +{ + /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ + unsigned int pwremu = 0; + + davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ + + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + mdelay(10); + + pwremu |= (0x3 << 13); + pwremu |= 0x1; + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); +} + +static int __init davinci_init(void) +{ + davinci_serial_reset(&serial_platform_data[0]); + return platform_device_register(&serial_device); +} + +arch_initcall(davinci_init); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c new file mode 100644 index 00000000000..4d8425de692 --- /dev/null +++ b/arch/arm/mach-davinci/time.c @@ -0,0 +1,372 @@ +/* + * DaVinci timer subsystem + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/spinlock.h> + +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/system.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/errno.h> +#include <asm/arch/io.h> + +static struct clock_event_device clockevent_davinci; + +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + +enum { + T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS, +}; + +#define IS_TIMER1(id) (id & 0x2) +#define IS_TIMER0(id) (!IS_TIMER1(id)) +#define IS_TIMER_TOP(id) ((id & 0x1)) +#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) + +static int timer_irqs[NUM_TIMERS] = { + IRQ_TINT0_TINT12, + IRQ_TINT0_TINT34, + IRQ_TINT1_TINT12, + IRQ_TINT1_TINT34, +}; + +/* + * This driver configures the 2 64-bit count-up timers as 4 independent + * 32-bit count-up timers used as follows: + * + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : <unused> + */ +#define TID_CLOCKEVENT T0_BOT +#define TID_CLOCKSOURCE T0_TOP + +/* Timer register offsets */ +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 + +/* Timer register bitfields */ +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 + +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 + +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 + +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xa5c6 +#define WDTCR_WDKEY_SEQ1 0xda7e + +struct timer_s { + char *name; + unsigned int id; + unsigned long period; + unsigned long opts; + unsigned long reg_base; + unsigned long tim_reg; + unsigned long prd_reg; + unsigned long enamode_shift; + struct irqaction irqaction; +}; +static struct timer_s timers[]; + +/* values for 'opts' field of struct timer_s */ +#define TIMER_OPTS_DISABLED 0x00 +#define TIMER_OPTS_ONESHOT 0x01 +#define TIMER_OPTS_PERIODIC 0x02 + +static int timer32_config(struct timer_s *t) +{ + u32 tcr = davinci_readl(t->reg_base + TCR); + + /* disable timer */ + tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); + davinci_writel(tcr, t->reg_base + TCR); + + /* reset counter to zero, set new period */ + davinci_writel(0, t->tim_reg); + davinci_writel(t->period, t->prd_reg); + + /* Set enable mode */ + if (t->opts & TIMER_OPTS_ONESHOT) { + tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; + } else if (t->opts & TIMER_OPTS_PERIODIC) { + tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; + } + + davinci_writel(tcr, t->reg_base + TCR); + return 0; +} + +static inline u32 timer32_read(struct timer_s *t) +{ + return davinci_readl(t->tim_reg); +} + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_davinci; + + evt->event_handler(evt); + return IRQ_HANDLED; +} + +/* called when 32-bit counter wraps */ +static irqreturn_t freerun_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static struct timer_s timers[] = { + [TID_CLOCKEVENT] = { + .name = "clockevent", + .opts = TIMER_OPTS_DISABLED, + .irqaction = { + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = timer_interrupt, + } + }, + [TID_CLOCKSOURCE] = { + .name = "free-run counter", + .period = ~0, + .opts = TIMER_OPTS_PERIODIC, + .irqaction = { + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = freerun_interrupt, + } + }, +}; + +static void __init timer_init(void) +{ + u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; + int i; + + /* Global init of each 64-bit timer as a whole */ + for(i=0; i<2; i++) { + u32 tgcr, base = bases[i]; + + /* Disabled, Internal clock source */ + davinci_writel(0, base + TCR); + + /* reset both timers, no pre-scaler for timer34 */ + tgcr = 0; + davinci_writel(tgcr, base + TGCR); + + /* Set both timers to unchained 32-bit */ + tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; + davinci_writel(tgcr, base + TGCR); + + /* Unreset timers */ + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TGCR); + + /* Init both counters to zero */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + } + + /* Init of each timer as a 32-bit timer */ + for (i=0; i< ARRAY_SIZE(timers); i++) { + struct timer_s *t = &timers[i]; + + if (t->name) { + t->id = i; + t->reg_base = (IS_TIMER1(t->id) ? + DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); + + if (IS_TIMER_BOT(t->id)) { + t->enamode_shift = 6; + t->tim_reg = t->reg_base + TIM12; + t->prd_reg = t->reg_base + PRD12; + } else { + t->enamode_shift = 22; + t->tim_reg = t->reg_base + TIM34; + t->prd_reg = t->reg_base + PRD34; + } + + /* Register interrupt */ + t->irqaction.name = t->name; + t->irqaction.dev_id = (void *)t; + if (t->irqaction.handler != NULL) { + setup_irq(timer_irqs[t->id], &t->irqaction); + } + + timer32_config(&timers[i]); + } + } +} + +/* + * clocksource + */ +static cycle_t read_cycles(void) +{ + struct timer_s *t = &timers[TID_CLOCKSOURCE]; + + return (cycles_t)timer32_read(t); +} + +static struct clocksource clocksource_davinci = { + .name = "timer0_1", + .rating = 300, + .read = read_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 24, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * clockevent + */ +static int davinci_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + t->period = cycles; + timer32_config(t); + return 0; +} + +static void davinci_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + t->period = CLOCK_TICK_RATE / (HZ); + t->opts = TIMER_OPTS_PERIODIC; + timer32_config(t); + break; + case CLOCK_EVT_MODE_ONESHOT: + t->opts = TIMER_OPTS_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + t->opts = TIMER_OPTS_DISABLED; + break; + } +} + +static struct clock_event_device clockevent_davinci = { + .name = "timer0_0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = davinci_set_next_event, + .set_mode = davinci_set_mode, +}; + + +static void __init davinci_timer_init(void) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + /* init timer hw */ + timer_init(); + + /* setup clocksource */ + clocksource_davinci.mult = + clocksource_khz2mult(CLOCK_TICK_RATE/1000, + clocksource_davinci.shift); + if (clocksource_register(&clocksource_davinci)) + printk(err, clocksource_davinci.name); + + /* setup clockevent */ + clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + clockevent_davinci.shift); + clockevent_davinci.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_davinci); + clockevent_davinci.min_delta_ns = + clockevent_delta2ns(1, &clockevent_davinci); + + clockevent_davinci.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&clockevent_davinci); +} + +struct sys_timer davinci_timer = { + .init = davinci_timer_init, +}; + + +/* reset board using watchdog timer */ +void davinci_watchdog_reset(void) { + u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; + + /* disable, internal clock source */ + davinci_writel(0, base + TCR); + + /* reset timer, set mode to 64-bit watchdog, and unreset */ + tgcr = 0; + davinci_writel(tgcr, base + TCR); + tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TCR); + + /* clear counter and period regs */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + davinci_writel(0, base + PRD12); + davinci_writel(0, base + PRD34); + + /* enable */ + wdtcr = davinci_readl(base + WDTCR); + wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; + davinci_writel(wdtcr, base + WDTCR); + + /* put watchdog in pre-active state */ + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* write an invalid value to the WDKEY field to trigger + * a watchdog reset */ + wdtcr = 0x00004000; + davinci_writel(wdtcr, base + WDTCR); +} diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c index bbf0d332407..6b2380e153e 100644 --- a/arch/arm/mach-ebsa110/io.c +++ b/arch/arm/mach-ebsa110/io.c @@ -102,7 +102,7 @@ EXPORT_SYMBOL(__readb); EXPORT_SYMBOL(__readw); EXPORT_SYMBOL(__readl); -void readsw(void __iomem *addr, void *data, int len) +void readsw(const void __iomem *addr, void *data, int len) { void __iomem *a = __isamem_convert_addr(addr); @@ -112,7 +112,7 @@ void readsw(void __iomem *addr, void *data, int len) } EXPORT_SYMBOL(readsw); -void readsl(void __iomem *addr, void *data, int len) +void readsl(const void __iomem *addr, void *data, int len) { void __iomem *a = __isamem_convert_addr(addr); @@ -157,7 +157,7 @@ EXPORT_SYMBOL(__writeb); EXPORT_SYMBOL(__writew); EXPORT_SYMBOL(__writel); -void writesw(void __iomem *addr, void *data, int len) +void writesw(void __iomem *addr, const void *data, int len) { void __iomem *a = __isamem_convert_addr(addr); @@ -167,7 +167,7 @@ void writesw(void __iomem *addr, void *data, int len) } EXPORT_SYMBOL(writesw); -void writesl(void __iomem *addr, void *data, int len) +void writesl(void __iomem *addr, const void *data, int len) { void __iomem *a = __isamem_convert_addr(addr); diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile index da1609dc0de..cad015fee12 100644 --- a/arch/arm/mach-iop13xx/Makefile +++ b/arch/arm/mach-iop13xx/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_IOP13XX) += io.o obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o +obj-$(CONFIG_PCI_MSI) += msi.o diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index b2eb0b96103..5791addd436 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -26,6 +26,7 @@ #include <asm/hardware.h> #include <asm/mach-types.h> #include <asm/arch/irqs.h> +#include <asm/arch/msi.h> /* INTCTL0 CP6 R0 Page 4 */ @@ -258,7 +259,7 @@ void __init iop13xx_init_irq(void) write_intbase(INTBASE); write_intsize(INTSIZE_4); - for(i = 0; i < NR_IOP13XX_IRQS; i++) { + for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) set_irq_chip(i, &iop13xx_irqchip1); else if (i < 64) @@ -271,4 +272,6 @@ void __init iop13xx_init_irq(void) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } + + iop13xx_msi_init(); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c new file mode 100644 index 00000000000..2d236930222 --- /dev/null +++ b/arch/arm/mach-iop13xx/msi.c @@ -0,0 +1,194 @@ +/* + * arch/arm/mach-iop13xx/msi.c + * + * PCI MSI support for the iop13xx processor + * + * Copyright (c) 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ +#include <linux/pci.h> +#include <linux/msi.h> +#include <asm/mach/irq.h> +#include <asm/irq.h> + + +#define IOP13XX_NUM_MSI_IRQS 128 +static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); + +/* IMIPR0 CP6 R8 Page 1 + */ +static inline u32 read_imipr_0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); +} + +/* IMIPR1 CP6 R9 Page 1 + */ +static inline u32 read_imipr_1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); +} + +/* IMIPR2 CP6 R10 Page 1 + */ +static inline u32 read_imipr_2(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_2(u32 val) +{ + asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); +} + +/* IMIPR3 CP6 R11 Page 1 + */ +static inline u32 read_imipr_3(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_3(u32 val) +{ + asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); +} + +static u32 (*read_imipr[])(void) = { + read_imipr_0, + read_imipr_1, + read_imipr_2, + read_imipr_3, +}; + +static void (*write_imipr[])(u32) = { + write_imipr_0, + write_imipr_1, + write_imipr_2, + write_imipr_3, +}; + +static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) +{ + int i, j; + unsigned long status; + + /* read IMIPR registers and find any active interrupts, + * then call ISR for each active interrupt + */ + for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { + status = (read_imipr[i])(); + if (!status) + continue; + + do { + j = find_first_bit(&status, 32); + (write_imipr[i])(1 << j); /* write back to clear bit */ + desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i); + desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc); + status = (read_imipr[i])(); + } while (status); + } +} + +void __init iop13xx_msi_init(void) +{ + set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); +} + +/* + * Dynamic irq allocate and deallocation + */ +int create_irq(void) +{ + int irq, pos; + +again: + pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); + irq = IRQ_IOP13XX_MSI_0 + pos; + if (irq > NR_IRQS) + return -ENOSPC; + /* test_and_set_bit operates on 32-bits at a time */ + if (test_and_set_bit(pos, msi_irq_in_use)) + goto again; + + dynamic_irq_init(irq); + + return irq; +} + +void destroy_irq(unsigned int irq) +{ + int pos = irq - IRQ_IOP13XX_MSI_0; + + dynamic_irq_cleanup(irq); + + clear_bit(pos, msi_irq_in_use); +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + destroy_irq(irq); +} + +static void iop13xx_msi_nop(unsigned int irq) +{ + return; +} + +static struct irq_chip iop13xx_msi_chip = { + .name = "PCI-MSI", + .ack = iop13xx_msi_nop, + .enable = unmask_msi_irq, + .disable = mask_msi_irq, + .mask = mask_msi_irq, + .unmask = unmask_msi_irq, +}; + +int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +{ + int id, irq = create_irq(); + struct msi_msg msg; + + if (irq < 0) + return irq; + + set_irq_msi(irq, desc); + + msg.address_hi = 0x0; + msg.address_lo = IOP13XX_MU_MIMR_PCI; + + id = iop13xx_cpu_id(); + msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); + + write_msi_msg(irq, &msg); + set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + + return irq; +} diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index d1d0d32ca77..1c9e94c38b7 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -559,6 +559,14 @@ void __init iop13xx_atue_setup(void) int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); u32 reg_val; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, @@ -720,6 +728,14 @@ void __init iop13xx_atux_setup(void) else atux_trhfa_timeout = jiffies; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig new file mode 100644 index 00000000000..ce1cf8de2b4 --- /dev/null +++ b/arch/arm/mach-ks8695/Kconfig @@ -0,0 +1,13 @@ +if ARCH_KS8695 + +menu "Kendin/Micrel KS8695 Implementations" + +config MACH_KS8695 + bool "KS8695 development board" + help + Say 'Y' here if you want your kernel to run on the original + Kendin-Micrel KS8695 development board. + +endmenu + +endif diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile new file mode 100644 index 00000000000..56b7d337333 --- /dev/null +++ b/arch/arm/mach-ks8695/Makefile @@ -0,0 +1,15 @@ +# arch/arm/mach-ks8695/Makefile +# +# Makefile for KS8695 architecture support +# + +obj-y := cpu.o irq.o time.o devices.o +obj-m := +obj-n := +obj- := + +# PCI support is optional +#obj-$(CONFIG_PCI) += pci.o + +# Board-specific support +obj-$(CONFIG_MACH_KS8695) += board-micrel.o diff --git a/arch/arm/mach-ks8695/Makefile.boot b/arch/arm/mach-ks8695/Makefile.boot new file mode 100644 index 00000000000..48eb2cb3ac7 --- /dev/null +++ b/arch/arm/mach-ks8695/Makefile.boot @@ -0,0 +1,8 @@ +# Note: the following conditions must always be true: +# ZRELADDR == virt_to_phys(TEXTADDR) +# PARAMS_PHYS must be within 4MB of ZRELADDR +# INITRD_PHYS must be in RAM + + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c new file mode 100644 index 00000000000..8fc0edb5211 --- /dev/null +++ b/arch/arm/mach-ks8695/board-micrel.c @@ -0,0 +1,60 @@ +/* + * arch/arm/mach-ks8695/board-micrel.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/arch/devices.h> + +#include "generic.h" + +#ifdef CONFIG_PCI +static int __init micrel_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return KS8695_IRQ_EXTERN0; +} + +static struct ks8695_pci_cfg micrel_pci = { + .mode = KS8695_MODE_MINIPCI, + .map_irq = micrel_pci_map_irq, +}; +#endif + + +static void micrel_init(void) +{ + printk(KERN_INFO "Micrel KS8695 Development Board initializing\n"); + +#ifdef CONFIG_PCI + ks8695_init_pci(&micrel_pci); +#endif + + /* Add devices */ + ks8695_add_device_wan(); /* eth0 = WAN */ + ks8695_add_device_lan(); /* eth1 = LAN */ +} + +MACHINE_START(KS8695, "KS8695 Centaur Development Board") + /* Maintainer: Micrel Semiconductor Inc. */ + .phys_io = KS8695_IO_PA, + .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc, + .boot_params = KS8695_SDRAM_PA + 0x100, + .map_io = ks8695_map_io, + .init_irq = ks8695_init_irq, + .init_machine = micrel_init, + .timer = &ks8695_timer, +MACHINE_END diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c new file mode 100644 index 00000000000..407d255e42b --- /dev/null +++ b/arch/arm/mach-ks8695/cpu.c @@ -0,0 +1,73 @@ +/* + * arch/arm/mach-ks8695/cpu.c + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <asm/arch/regs-sys.h> +#include <asm/arch/regs-misc.h> + + +static struct __initdata map_desc ks8695_io_desc[] = { + { + .virtual = KS8695_IO_VA, + .pfn = __phys_to_pfn(KS8695_IO_PA), + .length = KS8695_IO_SIZE, + .type = MT_DEVICE, + } +}; + +static void __init ks8695_processor_info(void) +{ + unsigned long id, rev; + + id = __raw_readl(KS8695_MISC_VA + KS8695_DID); + rev = __raw_readl(KS8695_MISC_VA + KS8695_RID); + + printk("KS8695 ID=%04lx SubID=%02lx Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION)); +} + +static unsigned int sysclk[8] = { 125000000, 100000000, 62500000, 50000000, 41700000, 33300000, 31300000, 25000000 }; +static unsigned int cpuclk[8] = { 166000000, 166000000, 83000000, 83000000, 55300000, 55300000, 41500000, 41500000 }; + +static void __init ks8695_clock_info(void) +{ + unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC; + + printk("Clocks: System %u MHz, CPU %u MHz\n", + sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000); +} + +void __init ks8695_map_io(void) +{ + iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc)); + + ks8695_processor_info(); + ks8695_clock_info(); +} diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c new file mode 100644 index 00000000000..386593f8ac6 --- /dev/null +++ b/arch/arm/mach-ks8695/devices.c @@ -0,0 +1,191 @@ +/* + * arch/arm/mach-ks8695/devices.c + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <linux/platform_device.h> + +#include <asm/arch/regs-wan.h> +#include <asm/arch/regs-lan.h> +#include <asm/arch/regs-hpna.h> + + +/* -------------------------------------------------------------------- + * Ethernet + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_ARM_KS8695_ETHER) || defined(CONFIG_ARM_KS8695_ETHER_MODULE) +static u64 eth_dmamask = 0xffffffffUL; + +static struct resource ks8695_wan_resources[] = { + [0] = { + .start = KS8695_WAN_VA, + .end = KS8695_WAN_VA + 0x00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "WAN RX", + .start = KS8695_IRQ_WAN_RX_STATUS, + .end = KS8695_IRQ_WAN_RX_STATUS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "WAN TX", + .start = KS8695_IRQ_WAN_TX_STATUS, + .end = KS8695_IRQ_WAN_TX_STATUS, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .name = "WAN Link", + .start = KS8695_IRQ_WAN_LINK, + .end = KS8695_IRQ_WAN_LINK, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ks8695_wan_device = { + .name = "ks8695_ether", + .id = 0, + .dev = { + .dma_mask = ð_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ks8695_wan_resources, + .num_resources = ARRAY_SIZE(ks8695_wan_resources), +}; + + +static struct resource ks8695_lan_resources[] = { + [0] = { + .start = KS8695_LAN_VA, + .end = KS8695_LAN_VA + 0x00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "LAN RX", + .start = KS8695_IRQ_LAN_RX_STATUS, + .end = KS8695_IRQ_LAN_RX_STATUS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "LAN TX", + .start = KS8695_IRQ_LAN_TX_STATUS, + .end = KS8695_IRQ_LAN_TX_STATUS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ks8695_lan_device = { + .name = "ks8695_ether", + .id = 1, + .dev = { + .dma_mask = ð_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ks8695_lan_resources, + .num_resources = ARRAY_SIZE(ks8695_lan_resources), +}; + + +static struct resource ks8695_hpna_resources[] = { + [0] = { + .start = KS8695_HPNA_VA, + .end = KS8695_HPNA_VA + 0x00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "HPNA RX", + .start = KS8695_IRQ_HPNA_RX_STATUS, + .end = KS8695_IRQ_HPNA_RX_STATUS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "HPNA TX", + .start = KS8695_IRQ_HPNA_TX_STATUS, + .end = KS8695_IRQ_HPNA_TX_STATUS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ks8695_hpna_device = { + .name = "ks8695_ether", + .id = 2, + .dev = { + .dma_mask = ð_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ks8695_hpna_resources, + .num_resources = ARRAY_SIZE(ks8695_hpna_resources), +}; + +void __init ks8695_add_device_wan(void) +{ + platform_device_register(&ks8695_wan_device); +} + +void __init ks8695_add_device_lan(void) +{ + platform_device_register(&ks8695_lan_device); +} + +void __init ks8696_add_device_hpna(void) +{ + platform_device_register(&ks8695_hpna_device); +} +#else +void __init ks8695_add_device_wan(void) {} +void __init ks8695_add_device_lan(void) {} +void __init ks8696_add_device_hpna(void) {} +#endif + + +/* -------------------------------------------------------------------- + * Watchdog + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_KS8695_WATCHDOG) || defined(CONFIG_KS8695_WATCHDOG_MODULE) +static struct platform_device ks8695_wdt_device = { + .name = "ks8695_wdt", + .id = -1, + .num_resources = 0, +}; + +static void __init ks8695_add_device_watchdog(void) +{ + platform_device_register(&ks8695_wdt_device); +} +#else +static void __init ks8695_add_device_watchdog(void) {} +#endif + + +/* -------------------------------------------------------------------- */ + +/* + * These devices are always present and don't need any board-specific + * setup. + */ +static int __init ks8695_add_standard_devices(void) +{ + ks8695_add_device_watchdog(); + return 0; +} + +arch_initcall(ks8695_add_standard_devices); diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h new file mode 100644 index 00000000000..2fbfab8d5fa --- /dev/null +++ b/arch/arm/mach-ks8695/generic.h @@ -0,0 +1,15 @@ +/* + * arch/arm/mach-ks8695/generic.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. +*/ + +extern __init void ks8695_map_io(void); +extern __init void ks8695_init_irq(void); +extern struct sys_timer ks8695_timer; diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c new file mode 100644 index 00000000000..2407bba0054 --- /dev/null +++ b/arch/arm/mach-ks8695/irq.c @@ -0,0 +1,175 @@ +/* + * arch/arm/mach-ks8695/irq.c + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/ptrace.h> +#include <linux/sysdev.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/io.h> + +#include <asm/mach/irq.h> + +#include <asm/arch/regs-irq.h> +#include <asm/arch/regs-gpio.h> + +static void ks8695_irq_mask(unsigned int irqno) +{ + unsigned long inten; + + inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); + inten &= ~(1 << irqno); + + __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); +} + +static void ks8695_irq_unmask(unsigned int irqno) +{ + unsigned long inten; + + inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); + inten |= (1 << irqno); + + __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); +} + +static void ks8695_irq_ack(unsigned int irqno) +{ + __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST); +} + + +static struct irq_chip ks8695_irq_level_chip; +static struct irq_chip ks8695_irq_edge_chip; + + +static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) +{ + unsigned long ctrl, mode; + unsigned short level_triggered = 0; + + ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); + + switch (type) { + case IRQT_HIGH: + mode = IOPC_TM_HIGH; + level_triggered = 1; + break; + case IRQT_LOW: + mode = IOPC_TM_LOW; + level_triggered = 1; + break; + case IRQT_RISING: + mode = IOPC_TM_RISING; + break; + case IRQT_FALLING: + mode = IOPC_TM_FALLING; + break; + case IRQT_BOTHEDGE: + mode = IOPC_TM_EDGE; + break; + default: + return -EINVAL; + } + + switch (irqno) { + case KS8695_IRQ_EXTERN0: + ctrl &= ~IOPC_IOEINT0TM; + ctrl |= IOPC_IOEINT0_MODE(mode); + break; + case KS8695_IRQ_EXTERN1: + ctrl &= ~IOPC_IOEINT1TM; + ctrl |= IOPC_IOEINT1_MODE(mode); + break; + case KS8695_IRQ_EXTERN2: + ctrl &= ~IOPC_IOEINT2TM; + ctrl |= IOPC_IOEINT2_MODE(mode); + break; + case KS8695_IRQ_EXTERN3: + ctrl &= ~IOPC_IOEINT3TM; + ctrl |= IOPC_IOEINT3_MODE(mode); + break; + default: + return -EINVAL; + } + + if (level_triggered) { + set_irq_chip(irqno, &ks8695_irq_level_chip); + set_irq_handler(irqno, handle_level_irq); + } + else { + set_irq_chip(irqno, &ks8695_irq_edge_chip); + set_irq_handler(irqno, handle_edge_irq); + } + + __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); + return 0; +} + +static struct irq_chip ks8695_irq_level_chip = { + .ack = ks8695_irq_mask, + .mask = ks8695_irq_mask, + .unmask = ks8695_irq_unmask, + .set_type = ks8695_irq_set_type, +}; + +static struct irq_chip ks8695_irq_edge_chip = { + .ack = ks8695_irq_ack, + .mask = ks8695_irq_mask, + .unmask = ks8695_irq_unmask, + .set_type = ks8695_irq_set_type, +}; + +void __init ks8695_init_irq(void) +{ + unsigned int irq; + + /* Disable all interrupts initially */ + __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC); + __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN); + + for (irq = 0; irq < NR_IRQS; irq++) { + switch (irq) { + /* Level-triggered interrupts */ + case KS8695_IRQ_BUS_ERROR: + case KS8695_IRQ_UART_MODEM_STATUS: + case KS8695_IRQ_UART_LINE_STATUS: + case KS8695_IRQ_UART_RX: + case KS8695_IRQ_COMM_TX: + case KS8695_IRQ_COMM_RX: + set_irq_chip(irq, &ks8695_irq_level_chip); + set_irq_handler(irq, handle_level_irq); + break; + + /* Edge-triggered interrupts */ + default: + ks8695_irq_ack(irq); /* clear pending bit */ + set_irq_chip(irq, &ks8695_irq_edge_chip); + set_irq_handler(irq, handle_edge_irq); + } + + set_irq_flags(irq, IRQF_VALID); + } +} diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c new file mode 100644 index 00000000000..d2c86e4a72e --- /dev/null +++ b/arch/arm/mach-ks8695/time.c @@ -0,0 +1,114 @@ +/* + * arch/arm/mach-ks8695/time.c + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/sched.h> + +#include <asm/io.h> +#include <asm/mach/time.h> + +#include <asm/arch/regs-timer.h> +#include <asm/arch/regs-irq.h> + +#include "generic.h" + +/* + * Returns number of ms since last clock interrupt. Note that interrupts + * will have been disabled by do_gettimeoffset() + */ +static unsigned long ks8695_gettimeoffset (void) +{ + unsigned long elapsed, tick2, intpending; + + /* + * Get the current number of ticks. Note that there is a race + * condition between us reading the timer and checking for an + * interrupt. We solve this by ensuring that the counter has not + * reloaded between our two reads. + */ + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); + do { + tick2 = elapsed; + intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1); + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); + } while (elapsed > tick2); + + /* Convert to number of ticks expired (not remaining) */ + elapsed = (CLOCK_TICK_RATE / HZ) - elapsed; + + /* Is interrupt pending? If so, then timer has been reloaded already. */ + if (intpending) + elapsed += (CLOCK_TICK_RATE / HZ); + + /* Convert ticks to usecs */ + return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; +} + +/* + * IRQ handler for the timer. + */ +static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) +{ + write_seqlock(&xtime_lock); + timer_tick(); + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction ks8695_timer_irq = { + .name = "ks8695_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = ks8695_timer_interrupt, +}; + +static void ks8695_timer_setup(void) +{ + unsigned long tmout = CLOCK_TICK_RATE / HZ; + unsigned long tmcon; + + /* disable timer1 */ + tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); + + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC); + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD); + + /* re-enable timer1 */ + __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); +} + +static void __init ks8695_timer_init (void) +{ + ks8695_timer_setup(); + + /* Enable timer interrupts */ + setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq); +} + +struct sys_timer ks8695_timer = { + .init = ks8695_timer_init, + .offset = ks8695_gettimeoffset, + .resume = ks8695_timer_setup, +}; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index ad519390dd5..48c8c9195dc 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -326,7 +326,7 @@ static struct omap_lcd_config h2_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_board_config_kernel h2_config[] = { +static struct omap_board_config_kernel h2_config[] __initdata = { { OMAP_TAG_USB, &h2_usb_config }, { OMAP_TAG_MMC, &h2_mmc_config }, { OMAP_TAG_UART, &h2_uart_config }, diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 6f4ea4bda5e..8caee68aa09 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -1,4 +1,3 @@ -//kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text) /* * linux/arch/arm/mach-omap1/pm.c * @@ -377,7 +376,7 @@ void omap_pm_suspend(void) * Jump to assembly code. The processor will stay there * until wake up. */ - omap_sram_suspend(arg0, arg1); + omap_sram_suspend(arg0, arg1); /* * If we are here, processor is woken up! @@ -631,10 +630,6 @@ static int omap_pm_prepare(suspend_state_t state) case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: break; - - case PM_SUSPEND_DISK: - return -ENOTSUPP; - default: return -EINVAL; } @@ -657,10 +652,6 @@ static int omap_pm_enter(suspend_state_t state) case PM_SUSPEND_MEM: omap_pm_suspend(); break; - - case PM_SUSPEND_DISK: - return -ENOTSUPP; - default: return -EINVAL; } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 54c836a9845..e290b989aa9 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -54,7 +54,7 @@ static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; -static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(gpmc_mem_lock); static unsigned gpmc_cs_map; static void __iomem *gpmc_base = diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index f538d0fdb13..0439906d5da 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -43,7 +43,7 @@ struct pin_config __initdata_or_module omap24xx_pins[] = { /* 24xx I2C */ MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1) MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 0, 1) +MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1) MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1) /* Menelaus interrupt */ @@ -52,7 +52,9 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) /* 24xx clocks */ MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) -/* 24xx GPMC wait pin monitoring */ +/* 24xx GPMC chipselects, wait pin monitoring */ +MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) +MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) @@ -66,6 +68,7 @@ MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) /* 24xx GPIO */ MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) +MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) @@ -75,7 +78,9 @@ MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) +MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) +MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) /* 242x DBG GPIO */ MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1) @@ -118,6 +123,30 @@ MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) +/* Full speed USB */ +MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1) +MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1) +MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1) +MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1) +MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1) +MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1) +MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1) + +MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1) +MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1) +MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1) +MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1) +MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1) +MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1) +MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1) +MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1) + +MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1) +MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1) +MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1) +MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1) +MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1) + /* Keypad GPIO*/ MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c index d6a279e4b52..f7009d845be 100644 --- a/arch/arm/mach-pnx4008/dma.c +++ b/arch/arm/mach-pnx4008/dma.c @@ -47,7 +47,7 @@ static struct ll_pool { int count; } ll_pool; -static spinlock_t ll_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(ll_lock); struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma) { @@ -135,7 +135,7 @@ static inline void dma_decrement_usage(void) } } -static spinlock_t dma_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(dma_lock); static inline void pnx4008_dma_lock(void) { diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 119c64b7223..28c79bd0a3a 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -24,6 +24,7 @@ #include <linux/delay.h> #include <linux/serial_8250.h> #include <linux/mtd/mtd.h> +#include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> #include <asm/types.h> @@ -55,23 +56,31 @@ static struct mtd_partition trizeps4_partitions[] = { { .name = "Bootloader", + .offset = 0x00000000, .size = 0x00040000, - .offset = 0, .mask_flags = MTD_WRITEABLE /* force read-only */ },{ - .name = "Kernel", - .size = 0x00400000, - .offset = 0x00040000 + .name = "Backup", + .offset = 0x00040000, + .size = 0x00040000, + },{ + .name = "Image", + .offset = 0x00080000, + .size = 0x01080000, + },{ + .name = "IPSM", + .offset = 0x01100000, + .size = 0x00e00000, },{ - .name = "Filesystem", + .name = "Registry", + .offset = 0x01f00000, .size = MTDPART_SIZ_FULL, - .offset = 0x00440000 } }; -static struct flash_platform_data trizeps4_flash_data[] = { +static struct physmap_flash_data trizeps4_flash_data[] = { { - .map_name = "cfi_probe", + .width = 4, /* bankwidth in bytes */ .parts = trizeps4_partitions, .nr_parts = ARRAY_SIZE(trizeps4_partitions) } @@ -79,15 +88,15 @@ static struct flash_platform_data trizeps4_flash_data[] = { static struct resource flash_resource = { .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_64M - 1, + .end = PXA_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; static struct platform_device flash_device = { - .name = "pxa2xx-flash", + .name = "physmap-flash", .id = 0, .dev = { - .platform_data = &trizeps4_flash_data, + .platform_data = trizeps4_flash_data, }, .resource = &flash_resource, .num_resources = 1, @@ -393,11 +402,37 @@ static struct pxafb_mach_info sharp_lcd = { .pxafb_backlight_power = board_backlight_power, }; +static struct pxafb_mode_info toshiba_lcd_mode = { + .pixclock = 39720, + .xres = 640, + .yres = 480, + .bpp = 8, + .hsync_len = 63, + .left_margin = 12, + .right_margin = 12, + .vsync_len = 4, + .upper_margin = 32, + .lower_margin = 10, + .sync = 0, + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info toshiba_lcd = { + .modes = &toshiba_lcd_mode, + .num_modes = 1, + .cmap_inverse = 0, + .cmap_static = 0, + .lccr0 = LCCR0_Color | LCCR0_Act, + .lccr3 = 0x03400002, + .pxafb_backlight_power = board_backlight_power, +}; + static void __init trizeps4_init(void) { platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices)); - set_pxa_fb_info(&sharp_lcd); +/* set_pxa_fb_info(&sharp_lcd); */ + set_pxa_fb_info(&toshiba_lcd); pxa_set_mci_info(&trizeps4_mci_platform_data); pxa_set_ficp_info(&trizeps4_ficp_platform_data); @@ -436,9 +471,10 @@ static void __init trizeps4_map_io(void) /* whats that for ??? */ pxa_gpio_mode(GPIO79_nCS_3_MD); +#ifdef CONFIG_LEDS pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */ pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */ - +#endif #ifdef CONFIG_MACH_TRIZEPS4_CONXS #ifdef CONFIG_IDE_PXA_CF /* if boot direct from compact flash dont disable power */ diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 9a3d3d24c08..3e7a85594d9 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_S3C2410_CLOCK) += clock.o # Machine support obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o -obj-$(CONFIG_ARCH_H1940) += mach-h1940.o +obj-$(CONFIG_ARCH_H1940) += mach-h1940.o h1940-bluetooth.o obj-$(CONFIG_PM_H1940) += pm-h1940.o obj-$(CONFIG_MACH_N30) += mach-n30.o obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c new file mode 100644 index 00000000000..3c48886521e --- /dev/null +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -0,0 +1,142 @@ +/* + * arch/arm/mach-s3c2410/h1940-bluetooth.c + * Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + * + * S3C2410 bluetooth "driver" + * + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/string.h> +#include <linux/ctype.h> +#include <linux/leds.h> +#include <asm/arch/regs-gpio.h> +#include <asm/hardware.h> +#include <asm/arch/h1940-latch.h> + +#define DRV_NAME "h1940-bt" + +#ifdef CONFIG_LEDS_H1940 +DEFINE_LED_TRIGGER(bt_led_trigger); +#endif + +static int state; + +/* Bluetooth control */ +static void h1940bt_enable(int on) +{ + if (on) { +#ifdef CONFIG_LEDS_H1940 + /* flashing Blue */ + led_trigger_event(bt_led_trigger, LED_HALF); +#endif + + /* Power on the chip */ + h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); + /* Reset the chip */ + mdelay(10); + s3c2410_gpio_setpin(S3C2410_GPH1, 1); + mdelay(10); + s3c2410_gpio_setpin(S3C2410_GPH1, 0); + + state = 1; + } + else { +#ifdef CONFIG_LEDS_H1940 + led_trigger_event(bt_led_trigger, 0); +#endif + + s3c2410_gpio_setpin(S3C2410_GPH1, 1); + mdelay(10); + s3c2410_gpio_setpin(S3C2410_GPH1, 0); + mdelay(10); + h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); + + state = 0; + } +} + +static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", state); +} + +static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +{ + int new_state; + char *endp; + + new_state = simple_strtoul(buf, &endp, 0); + if (*endp && !isspace(*endp)) + return -EINVAL; + + h1940bt_enable(new_state); + + return count; +} +static DEVICE_ATTR(enable, 0644, + h1940bt_show, + h1940bt_store); + +static int __init h1940bt_probe(struct platform_device *pdev) +{ + /* Configures BT serial port GPIOs */ + s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); + s3c2410_gpio_pullup(S3C2410_GPH0, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); + s3c2410_gpio_pullup(S3C2410_GPH1, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); + s3c2410_gpio_pullup(S3C2410_GPH2, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); + s3c2410_gpio_pullup(S3C2410_GPH3, 1); + +#ifdef CONFIG_LEDS_H1940 + led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); +#endif + + /* disable BT by default */ + h1940bt_enable(0); + + return device_create_file(&pdev->dev, &dev_attr_enable); +} + +static int h1940bt_remove(struct platform_device *pdev) +{ +#ifdef CONFIG_LEDS_H1940 + led_trigger_unregister_simple(bt_led_trigger); +#endif + return 0; +} + + +static struct platform_driver h1940bt_driver = { + .driver = { + .name = DRV_NAME, + }, + .probe = h1940bt_probe, + .remove = h1940bt_remove, +}; + + +static int __init h1940bt_init(void) +{ + return platform_driver_register(&h1940bt_driver); +} + +static void __exit h1940bt_exit(void) +{ + platform_driver_unregister(&h1940bt_driver); +} + +module_init(h1940bt_init); +module_exit(h1940bt_exit); + +MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); +MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 5d5f00e9c46..5ccd0be23a3 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -177,6 +177,11 @@ static struct platform_device s3c_device_leds = { .id = -1, }; +static struct platform_device s3c_device_bluetooth = { + .name = "h1940-bt", + .id = -1, +}; + static struct platform_device *h1940_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, @@ -185,6 +190,7 @@ static struct platform_device *h1940_devices[] __initdata = { &s3c_device_iis, &s3c_device_usbgadget, &s3c_device_leds, + &s3c_device_bluetooth, }; static void __init h1940_map_io(void) diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index dd2272fb113..0b6e360aeae 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -791,6 +791,10 @@ static struct clk init_clocks[] = { .name = "usb-bus-host", .id = -1, .parent = &clk_usb_bus_host, + }, { .name = "ac97", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C2443_PCLKCON_AC97, } }; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index b81391a4e37..15f0284010c 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -131,8 +131,8 @@ config CPU_ARM920T # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR - depends on ARCH_LH7A40X || ARCH_INTEGRATOR - default y if ARCH_LH7A40X + depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 + default y if ARCH_LH7A40X || ARCH_KS8695 select CPU_32v4T select CPU_ABRT_EV4T select CPU_CACHE_V4WT @@ -143,7 +143,7 @@ config CPU_ARM922T help The ARM922T is a version of the ARM920T, but with smaller instruction and data caches. It is used in Altera's - Excalibur XA device family. + Excalibur XA device family and Micrel's KS8695 Centaur. Say Y if you want support for the ARM922T processor. Otherwise, say N. @@ -171,8 +171,8 @@ config CPU_ARM925T # ARM926T config CPU_ARM926T bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_CACHE_VIVT diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 2d86b106ff3..55a4d3be16b 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -747,7 +747,7 @@ int omap_set_dma_callback(int lch, */ dma_addr_t omap_get_dma_src_pos(int lch) { - dma_addr_t offset; + dma_addr_t offset = 0; if (cpu_class_is_omap1()) offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | @@ -769,7 +769,7 @@ dma_addr_t omap_get_dma_src_pos(int lch) */ dma_addr_t omap_get_dma_dst_pos(int lch) { - dma_addr_t offset; + dma_addr_t offset = 0; if (cpu_class_is_omap1()) offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 6c798d28868..75211f20ccb 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -83,10 +83,21 @@ int __init_or_module omap_cfg_reg(const unsigned long index) reg |= OMAP24XX_PULL_ENA; if(cfg->pu_pd_val) reg |= OMAP24XX_PULL_UP; -#ifdef CONFIG_OMAP_MUX_DEBUG - printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n", - cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg, - omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg); +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) + { + u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); + u8 debug = 0; + +#ifdef CONFIG_OMAP_MUX_DEBUG + debug = cfg->debug; +#endif + warn = (orig != reg); + if (debug || warn) + printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", + cfg->name, + OMAP24XX_L4_BASE + cfg->mux_reg, + orig, reg); + } #endif omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index b1142ce4ac4..0a9a5e7f62e 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Mon Apr 16 21:01:04 2007 +# Last update: Fri May 11 19:53:41 2007 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1335,3 +1335,35 @@ at91sam9rlek MACH_AT91SAM9RLEK AT91SAM9RLEK 1326 comtech_router MACH_COMTECH_ROUTER COMTECH_ROUTER 1327 sbc2410x MACH_SBC2410X SBC2410X 1328 at4x0bd MACH_AT4X0BD AT4X0BD 1329 +cbifr MACH_CBIFR CBIFR 1330 +arcom_quantum MACH_ARCOM_QUANTUM ARCOM_QUANTUM 1331 +matrix520 MACH_MATRIX520 MATRIX520 1332 +matrix510 MACH_MATRIX510 MATRIX510 1333 +matrix500 MACH_MATRIX500 MATRIX500 1334 +m501 MACH_M501 M501 1335 +aaeon1270 MACH_AAEON1270 AAEON1270 1336 +matrix500ev MACH_MATRIX500EV MATRIX500EV 1337 +pac500 MACH_PAC500 PAC500 1338 +pnx8181 MACH_PNX8181 PNX8181 1339 +colibri320 MACH_COLIBRI320 COLIBRI320 1340 +aztoolbb MACH_AZTOOLBB AZTOOLBB 1341 +aztoolg2 MACH_AZTOOLG2 AZTOOLG2 1342 +dvlhost MACH_DVLHOST DVLHOST 1343 +zir9200 MACH_ZIR9200 ZIR9200 1344 +zir9260 MACH_ZIR9260 ZIR9260 1345 +cocopah MACH_COCOPAH COCOPAH 1346 +nds MACH_NDS NDS 1347 +rosencrantz MACH_ROSENCRANTZ ROSENCRANTZ 1348 +fttx_odsc MACH_FTTX_ODSC FTTX_ODSC 1349 +classe_r6904 MACH_CLASSE_R6904 CLASSE_R6904 1350 +cam60 MACH_CAM60 CAM60 1351 +mxc30031ads MACH_MXC30031ADS MXC30031ADS 1352 +datacall MACH_DATACALL DATACALL 1353 +at91eb01 MACH_AT91EB01 AT91EB01 1354 +rty MACH_RTY RTY 1355 +dwl2100 MACH_DWL2100 DWL2100 1356 +vinsi MACH_VINSI VINSI 1357 +db88f5281 MACH_DB88F5281 DB88F5281 1358 +csb726 MACH_CSB726 CSB726 1359 +tik27 MACH_TIK27 TIK27 1360 +mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361 diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c index dbc8ee2adcf..c791a46df46 100644 --- a/drivers/ata/pata_icside.c +++ b/drivers/ata/pata_icside.c @@ -60,6 +60,18 @@ struct pata_icside_state { struct scatterlist sg[PATA_ICSIDE_MAX_SG]; }; +struct pata_icside_info { + struct pata_icside_state *state; + struct expansion_card *ec; + void __iomem *base; + void __iomem *irqaddr; + unsigned int irqmask; + const expansioncard_ops_t *irqops; + unsigned int mwdma_mask; + unsigned int nr_ports; + const struct portinfo *port[2]; +}; + #define ICS_TYPE_A3IN 0 #define ICS_TYPE_A3USER 1 #define ICS_TYPE_V6 3 @@ -269,9 +281,10 @@ static u8 pata_icside_bmdma_status(struct ata_port *ap) return readb(irq_port) & 1 ? ATA_DMA_INTR : 0; } -static int icside_dma_init(struct ata_probe_ent *ae, struct expansion_card *ec) +static int icside_dma_init(struct pata_icside_info *info) { - struct pata_icside_state *state = ae->private_data; + struct pata_icside_state *state = info->state; + struct expansion_card *ec = info->ec; int i; for (i = 0; i < ATA_MAX_DEVICES; i++) { @@ -281,7 +294,7 @@ static int icside_dma_init(struct ata_probe_ent *ae, struct expansion_card *ec) if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { state->dma = ec->dma; - ae->mwdma_mask = 0x07; /* MW0..2 */ + info->mwdma_mask = 0x07; /* MW0..2 */ } return 0; @@ -371,6 +384,8 @@ static struct ata_port_operations pata_icside_port_ops = { .check_status = ata_check_status, .dev_select = ata_std_dev_select, + .cable_detect = ata_cable_40wire, + .bmdma_setup = pata_icside_bmdma_setup, .bmdma_start = pata_icside_bmdma_start, @@ -385,7 +400,6 @@ static struct ata_port_operations pata_icside_port_ops = { .error_handler = ata_bmdma_error_handler, .post_internal_cmd = pata_icside_bmdma_stop, - .irq_handler = ata_interrupt, .irq_clear = ata_dummy_noret, .irq_on = ata_irq_on, .irq_ack = pata_icside_irq_ack, @@ -396,11 +410,10 @@ static struct ata_port_operations pata_icside_port_ops = { .bmdma_status = pata_icside_bmdma_status, }; -static void -pata_icside_add_port(struct ata_probe_ent *ae, void __iomem *base, - const struct portinfo *info) +static void __devinit +pata_icside_setup_ioaddr(struct ata_ioports *ioaddr, void __iomem *base, + const struct portinfo *info) { - struct ata_ioports *ioaddr = &ae->port[ae->n_ports++]; void __iomem *cmd = base + info->dataoffset; ioaddr->cmd_addr = cmd; @@ -419,58 +432,44 @@ pata_icside_add_port(struct ata_probe_ent *ae, void __iomem *base, ioaddr->altstatus_addr = ioaddr->ctl_addr; } -static int __init -pata_icside_register_v5(struct ata_probe_ent *ae, struct expansion_card *ec) +static int __devinit pata_icside_register_v5(struct pata_icside_info *info) { - struct pata_icside_state *state = ae->private_data; + struct pata_icside_state *state = info->state; void __iomem *base; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); if (!base) return -ENOMEM; state->irq_port = base; - ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; - ec->irqmask = 1; - ec->irq_data = state; - ec->ops = &pata_icside_ops_arcin_v5; - - /* - * Be on the safe side - disable interrupts - */ - ec->ops->irqdisable(ec, ec->irq); - - pata_icside_add_port(ae, base, &pata_icside_portinfo_v5); + info->base = base; + info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; + info->irqmask = 1; + info->irqops = &pata_icside_ops_arcin_v5; + info->nr_ports = 1; + info->port[0] = &pata_icside_portinfo_v5; return 0; } -static int __init -pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) +static int __devinit pata_icside_register_v6(struct pata_icside_info *info) { - struct pata_icside_state *state = ae->private_data; + struct pata_icside_state *state = info->state; + struct expansion_card *ec = info->ec; void __iomem *ioc_base, *easi_base; unsigned int sel = 0; - int ret; - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); - if (!ioc_base) { - ret = -ENOMEM; - goto out; - } + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); + if (!ioc_base) + return -ENOMEM; easi_base = ioc_base; if (ecard_resource_flags(ec, ECARD_RES_EASI)) { - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), - ecard_resource_len(ec, ECARD_RES_EASI)); - if (!easi_base) { - ret = -ENOMEM; - goto unmap_slot; - } + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); + if (!easi_base) + return -ENOMEM; /* * Enable access to the EASI region. @@ -480,45 +479,72 @@ pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) writeb(sel, ioc_base); - ec->irq_data = state; - ec->ops = &pata_icside_ops_arcin_v6; - state->irq_port = easi_base; state->ioc_base = ioc_base; state->port[0].port_sel = sel; state->port[1].port_sel = sel | 1; /* - * Be on the safe side - disable interrupts - */ - ec->ops->irqdisable(ec, ec->irq); - - /* - * Find and register the interfaces. - */ - pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_1); - pata_icside_add_port(ae, easi_base, &pata_icside_portinfo_v6_2); - - /* * FIXME: work around libata's aversion to calling port_disable. * This permanently disables interrupts on port 0 - bad luck if * you have a drive on that port. */ state->port[0].disabled = 1; - return icside_dma_init(ae, ec); + info->base = easi_base; + info->irqops = &pata_icside_ops_arcin_v6; + info->nr_ports = 2; + info->port[0] = &pata_icside_portinfo_v6_1; + info->port[1] = &pata_icside_portinfo_v6_2; - unmap_slot: - iounmap(ioc_base); - out: - return ret; + return icside_dma_init(info); +} + +static int __devinit pata_icside_add_ports(struct pata_icside_info *info) +{ + struct expansion_card *ec = info->ec; + struct ata_host *host; + int i; + + if (info->irqaddr) { + ec->irqaddr = info->irqaddr; + ec->irqmask = info->irqmask; + } + if (info->irqops) + ecard_setirq(ec, info->irqops, info->state); + + /* + * Be on the safe side - disable interrupts + */ + ec->ops->irqdisable(ec, ec->irq); + + host = ata_host_alloc(&ec->dev, info->nr_ports); + if (!host) + return -ENOMEM; + + host->private_data = info->state; + host->flags = ATA_HOST_SIMPLEX; + + for (i = 0; i < info->nr_ports; i++) { + struct ata_port *ap = host->ports[i]; + + ap->pio_mask = 0x1f; + ap->mwdma_mask = info->mwdma_mask; + ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; + ap->ops = &pata_icside_port_ops; + + pata_icside_setup_ioaddr(&ap->ioaddr, info->base, info->port[i]); + } + + return ata_host_activate(host, ec->irq, ata_interrupt, 0, + &pata_icside_sht); } static int __devinit pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) { struct pata_icside_state *state; - struct ata_probe_ent ae; + struct pata_icside_info info; void __iomem *idmem; int ret; @@ -526,7 +552,7 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - state = kzalloc(sizeof(struct pata_icside_state), GFP_KERNEL); + state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); if (!state) { ret = -ENOMEM; goto release; @@ -535,8 +561,7 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) state->type = ICS_TYPE_NOTYPE; state->dma = NO_DMA; - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (idmem) { unsigned int type; @@ -544,21 +569,14 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; - iounmap(idmem); + ecardm_iounmap(ec, idmem); state->type = type; } - memset(&ae, 0, sizeof(ae)); - INIT_LIST_HEAD(&ae.node); - ae.dev = &ec->dev; - ae.port_ops = &pata_icside_port_ops; - ae.sht = &pata_icside_sht; - ae.pio_mask = 0x1f; - ae.irq = ec->irq; - ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; - ae._host_flags = ATA_HOST_SIMPLEX; - ae.private_data = state; + memset(&info, 0, sizeof(info)); + info.state = state; + info.ec = ec; switch (state->type) { case ICS_TYPE_A3IN: @@ -572,11 +590,11 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) break; case ICS_TYPE_V5: - ret = pata_icside_register_v5(&ae, ec); + ret = pata_icside_register_v5(&info); break; case ICS_TYPE_V6: - ret = pata_icside_register_v6(&ae, ec); + ret = pata_icside_register_v6(&info); break; default: @@ -586,12 +604,11 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) } if (ret == 0) - ret = ata_device_add(&ae) == 0 ? -ENODEV : 0; + ret = pata_icside_add_ports(&info); if (ret == 0) goto out; - kfree(state); release: ecard_release_resources(ec); out: @@ -609,8 +626,7 @@ static void pata_icside_shutdown(struct expansion_card *ec) * this register via that region. */ local_irq_save(flags); - if (ec->ops) - ec->ops->irqdisable(ec, ec->irq); + ec->ops->irqdisable(ec, ec->irq); local_irq_restore(flags); /* @@ -638,17 +654,9 @@ static void __devexit pata_icside_remove(struct expansion_card *ec) * don't NULL out the drvdata - devres/libata wants it * to free the ata_host structure. */ - ec->ops = NULL; - ec->irq_data = NULL; - if (state->dma != NO_DMA) free_dma(state->dma); - if (state->ioc_base) - iounmap(state->ioc_base); - if (state->ioc_base != state->irq_port) - iounmap(state->irq_port); - kfree(state); ecard_release_resources(ec); } diff --git a/drivers/ide/arm/icside.c b/drivers/ide/arm/icside.c index 1fe0457243d..66f826252ae 100644 --- a/drivers/ide/arm/icside.c +++ b/drivers/ide/arm/icside.c @@ -565,8 +565,7 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) ide_hwif_t *hwif; void __iomem *base; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) return -ENOMEM; @@ -574,8 +573,8 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; ec->irqmask = 1; - ec->irq_data = state; - ec->ops = &icside_ops_arcin_v5; + + ecard_setirq(ec, &icside_ops_arcin_v5, state); /* * Be on the safe side - disable interrupts @@ -583,10 +582,8 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) icside_irqdisable_arcin_v5(ec, 0); hwif = icside_setup(base, &icside_cardinfo_v5, ec); - if (!hwif) { - iounmap(base); + if (!hwif) return -ENODEV; - } state->hwif[0] = hwif; @@ -605,8 +602,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) unsigned int sel = 0; int ret; - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!ioc_base) { ret = -ENOMEM; goto out; @@ -615,11 +611,10 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) easi_base = ioc_base; if (ecard_resource_flags(ec, ECARD_RES_EASI)) { - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), - ecard_resource_len(ec, ECARD_RES_EASI)); + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); if (!easi_base) { ret = -ENOMEM; - goto unmap_slot; + goto out; } /* @@ -630,8 +625,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) writeb(sel, ioc_base); - ec->irq_data = state; - ec->ops = &icside_ops_arcin_v6; + ecard_setirq(ec, &icside_ops_arcin_v6, state); state->irq_port = easi_base; state->ioc_base = ioc_base; @@ -649,7 +643,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) if (!hwif || !mate) { ret = -ENODEV; - goto unmap_port; + goto out; } state->hwif[0] = hwif; @@ -686,11 +680,6 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) return 0; - unmap_port: - if (easi_base != ioc_base) - iounmap(easi_base); - unmap_slot: - iounmap(ioc_base); out: return ret; } @@ -716,8 +705,7 @@ icside_probe(struct expansion_card *ec, const struct ecard_id *id) state->type = ICS_TYPE_NOTYPE; state->dev = &ec->dev; - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (idmem) { unsigned int type; @@ -725,7 +713,7 @@ icside_probe(struct expansion_card *ec, const struct ecard_id *id) type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; - iounmap(idmem); + ecardm_iounmap(ec, idmem); state->type = type; } @@ -793,13 +781,6 @@ static void __devexit icside_remove(struct expansion_card *ec) } ecard_set_drvdata(ec, NULL); - ec->ops = NULL; - ec->irq_data = NULL; - - if (state->ioc_base) - iounmap(state->ioc_base); - if (state->ioc_base != state->irq_port) - iounmap(state->irq_port); kfree(state); ecard_release_resources(ec); diff --git a/drivers/ide/arm/rapide.c b/drivers/ide/arm/rapide.c index 890ea3fac3c..83811af1161 100644 --- a/drivers/ide/arm/rapide.c +++ b/drivers/ide/arm/rapide.c @@ -63,8 +63,7 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto release; @@ -81,7 +80,6 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id) goto out; } - iounmap(base); release: ecard_release_resources(ec); out: @@ -96,7 +94,6 @@ static void __devexit rapide_remove(struct expansion_card *ec) /* there must be a better way */ ide_unregister(hwif - ide_hwifs); - iounmap(hwif->hwif_data); ecard_release_resources(ec); } diff --git a/drivers/net/arm/ether1.c b/drivers/net/arm/ether1.c index f075cebe84a..f21148e7b57 100644 --- a/drivers/net/arm/ether1.c +++ b/drivers/net/arm/ether1.c @@ -1014,8 +1014,7 @@ ether1_probe(struct expansion_card *ec, const struct ecard_id *id) SET_NETDEV_DEV(dev, &ec->dev); dev->irq = ec->irq; - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!priv(dev)->base) { ret = -ENOMEM; goto free; @@ -1056,8 +1055,6 @@ ether1_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (priv(dev)->base) - iounmap(priv(dev)->base); free_netdev(dev); release: ecard_release_resources(ec); @@ -1072,7 +1069,6 @@ static void __devexit ether1_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - iounmap(priv(dev)->base); free_netdev(dev); ecard_release_resources(ec); } diff --git a/drivers/net/arm/ether3.c b/drivers/net/arm/ether3.c index 32da2eb9bce..da713500654 100644 --- a/drivers/net/arm/ether3.c +++ b/drivers/net/arm/ether3.c @@ -793,8 +793,7 @@ ether3_probe(struct expansion_card *ec, const struct ecard_id *id) SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, &ec->dev); - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!priv(dev)->base) { ret = -ENOMEM; goto free; @@ -869,8 +868,6 @@ ether3_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (priv(dev)->base) - iounmap(priv(dev)->base); free_netdev(dev); release: ecard_release_resources(ec); @@ -885,7 +882,6 @@ static void __devexit ether3_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - iounmap(priv(dev)->base); free_netdev(dev); ecard_release_resources(ec); } diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c index 61f574aa3a9..769ba69451f 100644 --- a/drivers/net/arm/etherh.c +++ b/drivers/net/arm/etherh.c @@ -686,7 +686,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) eh->supported = data->supported; eh->ctrl = 0; eh->id = ec->cid.product; - eh->memc = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), PAGE_SIZE); + eh->memc = ecardm_iomap(ec, ECARD_RES_MEMC, 0, PAGE_SIZE); if (!eh->memc) { ret = -ENOMEM; goto free; @@ -694,7 +694,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) eh->ctrl_port = eh->memc; if (data->ctrl_ioc) { - eh->ioc_fast = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), PAGE_SIZE); + eh->ioc_fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, PAGE_SIZE); if (!eh->ioc_fast) { ret = -ENOMEM; goto free; @@ -710,8 +710,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) * IRQ and control port handling - only for non-NIC slot cards. */ if (ec->slot_no != 8) { - ec->ops = ðerh_ops; - ec->irq_data = eh; + ecard_setirq(ec, ðerh_ops, eh); } else { /* * If we're in the NIC slot, make sure the IRQ is enabled @@ -759,10 +758,6 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (eh->ioc_fast) - iounmap(eh->ioc_fast); - if (eh->memc) - iounmap(eh->memc); free_netdev(dev); release: ecard_release_resources(ec); @@ -773,16 +768,10 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) static void __devexit etherh_remove(struct expansion_card *ec) { struct net_device *dev = ecard_get_drvdata(ec); - struct etherh_priv *eh = etherh_priv(dev); ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - ec->ops = NULL; - - if (eh->ioc_fast) - iounmap(eh->ioc_fast); - iounmap(eh->memc); free_netdev(dev); diff --git a/drivers/scsi/arm/arxescsi.c b/drivers/scsi/arm/arxescsi.c index 7e132c5bacf..2836fe248df 100644 --- a/drivers/scsi/arm/arxescsi.c +++ b/drivers/scsi/arm/arxescsi.c @@ -281,7 +281,6 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct arxescsi_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -289,9 +288,7 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -300,7 +297,7 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) host = scsi_host_alloc(&arxescsi_template, sizeof(struct arxescsi_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } info = (struct arxescsi_info *)host->hostdata; @@ -337,8 +334,6 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) fas216_release(host); out_unregister: scsi_host_put(host); - out_unmap: - iounmap(base); out_region: ecard_release_resources(ec); out: @@ -348,13 +343,10 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) static void __devexit arxescsi_remove(struct expansion_card *ec) { struct Scsi_Host *host = ecard_get_drvdata(ec); - struct arxescsi_info *info = (struct arxescsi_info *)host->hostdata; ecard_set_drvdata(ec, NULL); fas216_remove(host); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c index 82add77ad13..68a64123af8 100644 --- a/drivers/scsi/arm/cumana_2.c +++ b/drivers/scsi/arm/cumana_2.c @@ -401,7 +401,6 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct cumanascsi2_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -409,9 +408,7 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -421,7 +418,7 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof(struct cumanascsi2_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -450,8 +447,8 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = info->base + CUMANASCSI2_STATUS; ec->irqmask = STATUS_INT; - ec->irq_data = info; - ec->ops = &cumanascsi_2_ops; + + ecard_setirq(ec, &cumanascsi_2_ops, info); ret = fas216_init(host); if (ret) @@ -490,9 +487,6 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) out_free: scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -512,8 +506,6 @@ static void __devexit cumanascsi2_remove(struct expansion_card *ec) free_dma(info->info.scsi.dma); free_irq(ec->irq, info); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c index ed06a8c19ad..bb2477b3fb0 100644 --- a/drivers/scsi/arm/eesox.c +++ b/drivers/scsi/arm/eesox.c @@ -519,7 +519,6 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct eesoxscsi_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -527,9 +526,7 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -539,7 +536,7 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof(struct eesoxscsi_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -569,8 +566,8 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = base + EESOX_DMASTAT; ec->irqmask = EESOX_STAT_INTR; - ec->irq_data = info; - ec->ops = &eesoxscsi_ops; + + ecard_setirq(ec, &eesoxscsi_ops, info); device_create_file(&ec->dev, &dev_attr_bus_term); @@ -612,9 +609,6 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) device_remove_file(&ec->dev, &dev_attr_bus_term); scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -636,8 +630,6 @@ static void __devexit eesoxscsi_remove(struct expansion_card *ec) device_remove_file(&ec->dev, &dev_attr_bus_term); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c index 159047a3499..d9a546d1917 100644 --- a/drivers/scsi/arm/powertec.c +++ b/drivers/scsi/arm/powertec.c @@ -313,7 +313,6 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct powertec_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -321,9 +320,7 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -333,7 +330,7 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof (struct powertec_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -361,8 +358,8 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = base + POWERTEC_INTR_STATUS; ec->irqmask = POWERTEC_INTR_BIT; - ec->irq_data = info; - ec->ops = &powertecscsi_ops; + + ecard_setirq(ec, &powertecscsi_ops, info); device_create_file(&ec->dev, &dev_attr_bus_term); @@ -404,9 +401,6 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) device_remove_file(&ec->dev, &dev_attr_bus_term); scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -428,8 +422,6 @@ static void __devexit powertecscsi_remove(struct expansion_card *ec) free_dma(info->info.scsi.dma); free_irq(ec->irq, info); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/serial/8250_acorn.c b/drivers/serial/8250_acorn.c index 562ba745a04..b0ce8c56f1a 100644 --- a/drivers/serial/8250_acorn.c +++ b/drivers/serial/8250_acorn.c @@ -54,7 +54,7 @@ serial_card_probe(struct expansion_card *ec, const struct ecard_id *id) info->num_ports = type->num_ports; bus_addr = ecard_resource_start(ec, type->type); - info->vaddr = ioremap(bus_addr, ecard_resource_len(ec, type->type)); + info->vaddr = ecardm_iomap(ec, type->type, 0, 0); if (!info->vaddr) { kfree(info); return -ENOMEM; @@ -91,7 +91,6 @@ static void __devexit serial_card_remove(struct expansion_card *ec) if (info->ports[i] > 0) serial8250_unregister_port(info->ports[i]); - iounmap(info->vaddr); kfree(info); } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a6f5bfbb777..315ea991645 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -359,6 +359,23 @@ config SERIAL_ATMEL_TTYAT Say Y if you have an external 8250/16C550 UART. If unsure, say N. +config SERIAL_KS8695 + bool "Micrel KS8695 (Centaur) serial port support" + depends on ARCH_KS8695 + select SERIAL_CORE + help + This selects the Micrel Centaur KS8695 UART. Say Y here. + +config SERIAL_KS8695_CONSOLE + bool "Support for console on KS8695 (Centaur) serial port" + depends on SERIAL_KS8695=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use a KS8695 (Centaur) UART as the + system console (the system console is the device which + receives all kernel messages and warnings and which allows + logins in single user mode). + config SERIAL_CLPS711X tristate "CLPS711X serial port support" depends on ARM && ARCH_CLPS711X diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4959bcb8d1e..08ad0d97818 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -61,3 +61,4 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o +obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c new file mode 100644 index 00000000000..c5346d67731 --- /dev/null +++ b/drivers/serial/serial_ks8695.c @@ -0,0 +1,657 @@ +/* + * drivers/serial/serial_ks8695.c + * + * Driver for KS8695 serial ports + * + * Based on drivers/serial/serial_amba.c, by Kam Lee. + * + * Copyright 2002-2005 Micrel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <linux/module.h> +#include <linux/tty.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/console.h> +#include <linux/sysrq.h> +#include <linux/device.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> + +#include <asm/arch/regs-uart.h> +#include <asm/arch/regs-irq.h> + +#if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include <linux/serial_core.h> + + +#define SERIAL_KS8695_MAJOR 204 +#define SERIAL_KS8695_MINOR 16 +#define SERIAL_KS8695_DEVNAME "ttyAM" + +#define SERIAL_KS8695_NR 1 + +/* + * Access macros for the KS8695 UART + */ +#define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF) +#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + KS8695_URTH) +#define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC) +#define UART_PUT_FCR(p, c) __raw_writel((c), (p)->membase + KS8695_URFC) +#define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS) +#define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS) +#define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC) +#define UART_PUT_LCR(p, c) __raw_writel((c), (p)->membase + KS8695_URLC) +#define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC) +#define UART_PUT_MCR(p, c) __raw_writel((c), (p)->membase + KS8695_URMC) +#define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD) +#define UART_PUT_BRDR(p, c) __raw_writel((c), (p)->membase + KS8695_URBD) + +#define KS8695_CLR_TX_INT() __raw_writel(1 << KS8695_IRQ_UART_TX, KS8695_IRQ_VA + KS8695_INTST) + +#define UART_DUMMY_LSR_RX 0x100 +#define UART_PORT_SIZE (KS8695_USR - KS8695_URRB + 4) + +#define tx_enabled(port) ((port)->unused[0]) +#define rx_enabled(port) ((port)->unused[1]) + + +#ifdef SUPPORT_SYSRQ +static struct console ks8695_console; +#endif + +static void ks8695uart_stop_tx(struct uart_port *port) +{ + if (tx_enabled(port)) { + disable_irq(KS8695_IRQ_UART_TX); + tx_enabled(port) = 0; + } +} + +static void ks8695uart_start_tx(struct uart_port *port) +{ + if (!tx_enabled(port)) { + enable_irq(KS8695_IRQ_UART_TX); + tx_enabled(port) = 1; + } +} + +static void ks8695uart_stop_rx(struct uart_port *port) +{ + if (rx_enabled(port)) { + disable_irq(KS8695_IRQ_UART_RX); + rx_enabled(port) = 0; + } +} + +static void ks8695uart_enable_ms(struct uart_port *port) +{ + enable_irq(KS8695_IRQ_UART_MODEM_STATUS); +} + +static void ks8695uart_disable_ms(struct uart_port *port) +{ + disable_irq(KS8695_IRQ_UART_MODEM_STATUS); +} + +static irqreturn_t ks8695uart_rx_chars(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + struct tty_struct *tty = port->info->tty; + unsigned int status, ch, lsr, flg, max_count = 256; + + status = UART_GET_LSR(port); /* clears pending LSR interrupts */ + while ((status & URLS_URDR) && max_count--) { + ch = UART_GET_CHAR(port); + flg = TTY_NORMAL; + + port->icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + lsr = UART_GET_LSR(port) | UART_DUMMY_LSR_RX; + if (unlikely(lsr & (URLS_URBI | URLS_URPE | URLS_URFE | URLS_URROE))) { + if (lsr & URLS_URBI) { + lsr &= ~(URLS_URFE | URLS_URPE); + port->icount.brk++; + if (uart_handle_break(port)) + goto ignore_char; + } + if (lsr & URLS_URPE) + port->icount.parity++; + if (lsr & URLS_URFE) + port->icount.frame++; + if (lsr & URLS_URROE) + port->icount.overrun++; + + lsr &= port->read_status_mask; + + if (lsr & URLS_URBI) + flg = TTY_BREAK; + else if (lsr & URLS_URPE) + flg = TTY_PARITY; + else if (lsr & URLS_URFE) + flg = TTY_FRAME; + } + + if (uart_handle_sysrq_char(port, ch)) + goto ignore_char; + + uart_insert_char(port, lsr, URLS_URROE, ch, flg); + +ignore_char: + status = UART_GET_LSR(port); + } + tty_flip_buffer_push(tty); + + return IRQ_HANDLED; +} + + +static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + struct circ_buf *xmit = &port->info->xmit; + unsigned int count; + + if (port->x_char) { + KS8695_CLR_TX_INT(); + UART_PUT_CHAR(port, port->x_char); + port->icount.tx++; + port->x_char = 0; + return IRQ_HANDLED; + } + + if (uart_tx_stopped(port) || uart_circ_empty(xmit)) { + ks8695uart_stop_tx(port); + return IRQ_HANDLED; + } + + count = 16; /* fifo size */ + while (!uart_circ_empty(xmit) && (count-- > 0)) { + KS8695_CLR_TX_INT(); + UART_PUT_CHAR(port, xmit->buf[xmit->tail]); + + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (uart_circ_empty(xmit)) + ks8695uart_stop_tx(port); + + return IRQ_HANDLED; +} + +static irqreturn_t ks8695uart_modem_status(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + unsigned int status; + + /* + * clear modem interrupt by reading MSR + */ + status = UART_GET_MSR(port); + + if (status & URMS_URDDCD) + uart_handle_dcd_change(port, status & URMS_URDDCD); + + if (status & URMS_URDDST) + port->icount.dsr++; + + if (status & URMS_URDCTS) + uart_handle_cts_change(port, status & URMS_URDCTS); + + if (status & URMS_URTERI) + port->icount.rng++; + + wake_up_interruptible(&port->info->delta_msr_wait); + + return IRQ_HANDLED; +} + +static unsigned int ks8695uart_tx_empty(struct uart_port *port) +{ + return (UART_GET_LSR(port) & URLS_URTE) ? TIOCSER_TEMT : 0; +} + +static unsigned int ks8695uart_get_mctrl(struct uart_port *port) +{ + unsigned int result = 0; + unsigned int status; + + status = UART_GET_MSR(port); + if (status & URMS_URDCD) + result |= TIOCM_CAR; + if (status & URMS_URDSR) + result |= TIOCM_DSR; + if (status & URMS_URCTS) + result |= TIOCM_CTS; + if (status & URMS_URRI) + result |= TIOCM_RI; + + return result; +} + +static void ks8695uart_set_mctrl(struct uart_port *port, u_int mctrl) +{ + unsigned int mcr; + + mcr = UART_GET_MCR(port); + if (mctrl & TIOCM_RTS) + mcr |= URMC_URRTS; + else + mcr &= ~URMC_URRTS; + + if (mctrl & TIOCM_DTR) + mcr |= URMC_URDTR; + else + mcr &= ~URMC_URDTR; + + UART_PUT_MCR(port, mcr); +} + +static void ks8695uart_break_ctl(struct uart_port *port, int break_state) +{ + unsigned int lcr; + + lcr = UART_GET_LCR(port); + + if (break_state == -1) + lcr |= URLC_URSBC; + else + lcr &= ~URLC_URSBC; + + UART_PUT_LCR(port, lcr); +} + +static int ks8695uart_startup(struct uart_port *port) +{ + int retval; + + set_irq_flags(KS8695_IRQ_UART_TX, IRQF_VALID | IRQF_NOAUTOEN); + tx_enabled(port) = 0; + rx_enabled(port) = 1; + + /* + * Allocate the IRQ + */ + retval = request_irq(KS8695_IRQ_UART_TX, ks8695uart_tx_chars, IRQF_DISABLED, "UART TX", port); + if (retval) + goto err_tx; + + retval = request_irq(KS8695_IRQ_UART_RX, ks8695uart_rx_chars, IRQF_DISABLED, "UART RX", port); + if (retval) + goto err_rx; + + retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port); + if (retval) + return err_ls; + + retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port); + if (retval) + return err_ms; + + return 0; + +err_ms: + free_irq(KS8695_IRQ_UART_LINE_STATUS, port); +err_ls: + free_irq(KS8695_IRQ_UART_RX, port); +err_rx: + free_irq(KS8695_IRQ_UART_TX, port); +err_tx: + return retval; +} + +static void ks8695uart_shutdown(struct uart_port *port) +{ + /* + * Free the interrupt + */ + free_irq(KS8695_IRQ_UART_RX, port); + free_irq(KS8695_IRQ_UART_TX, port); + free_irq(KS8695_IRQ_UART_MODEM_STATUS, port); + free_irq(KS8695_IRQ_UART_LINE_STATUS, port); + + /* disable break condition and fifos */ + UART_PUT_LCR(port, UART_GET_LCR(port) & ~URLC_URSBC); + UART_PUT_FCR(port, UART_GET_FCR(port) & ~URFC_URFE); +} + +static void ks8695uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) +{ + unsigned int lcr, fcr = 0; + unsigned long flags; + unsigned int baud, quot; + + /* + * Ask the core to calculate the divisor for us. + */ + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); + quot = uart_get_divisor(port, baud); + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr = URCL_5; + break; + case CS6: + lcr = URCL_6; + break; + case CS7: + lcr = URCL_7; + break; + default: + lcr = URCL_8; + break; + } + + /* stop bits */ + if (termios->c_cflag & CSTOPB) + lcr |= URLC_URSB; + + /* parity */ + if (termios->c_cflag & PARENB) { + if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */ + if (termios->c_cflag & PARODD) + lcr |= URPE_MARK; + else + lcr |= URPE_SPACE; + } + else if (termios->c_cflag & PARODD) + lcr |= URPE_ODD; + else + lcr |= URPE_EVEN; + } + + if (port->fifosize > 1) + fcr = URFC_URFRT_8 | URFC_URTFR | URFC_URRFR | URFC_URFE; + + spin_lock_irqsave(&port->lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + port->read_status_mask = URLS_URROE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= (URLS_URFE | URLS_URPE); + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= URLS_URBI; + + /* + * Characters to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= (URLS_URFE | URLS_URPE); + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= URLS_URBI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= URLS_URROE; + } + + /* + * Ignore all characters if CREAD is not set. + */ + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_LSR_RX; + + /* first, disable everything */ + if (UART_ENABLE_MS(port, termios->c_cflag)) + ks8695uart_enable_ms(port); + else + ks8695uart_disable_ms(port); + + /* Set baud rate */ + UART_PUT_BRDR(port, quot); + + UART_PUT_LCR(port, lcr); + UART_PUT_FCR(port, fcr); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *ks8695uart_type(struct uart_port *port) +{ + return port->type == PORT_KS8695 ? "KS8695" : NULL; +} + +/* + * Release the memory region(s) being used by 'port' + */ +static void ks8695uart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, UART_PORT_SIZE); +} + +/* + * Request the memory region(s) being used by 'port' + */ +static int ks8695uart_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, UART_PORT_SIZE, + "serial_ks8695") != NULL ? 0 : -EBUSY; +} + +/* + * Configure/autoconfigure the port. + */ +static void ks8695uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_KS8695; + ks8695uart_request_port(port); + } +} + +/* + * verify the new serial_struct (for TIOCSSERIAL). + */ +static int ks8695uart_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + int ret = 0; + + if (ser->type != PORT_UNKNOWN && ser->type != PORT_KS8695) + ret = -EINVAL; + if (ser->irq != port->irq) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops ks8695uart_pops = { + .tx_empty = ks8695uart_tx_empty, + .set_mctrl = ks8695uart_set_mctrl, + .get_mctrl = ks8695uart_get_mctrl, + .stop_tx = ks8695uart_stop_tx, + .start_tx = ks8695uart_start_tx, + .stop_rx = ks8695uart_stop_rx, + .enable_ms = ks8695uart_enable_ms, + .break_ctl = ks8695uart_break_ctl, + .startup = ks8695uart_startup, + .shutdown = ks8695uart_shutdown, + .set_termios = ks8695uart_set_termios, + .type = ks8695uart_type, + .release_port = ks8695uart_release_port, + .request_port = ks8695uart_request_port, + .config_port = ks8695uart_config_port, + .verify_port = ks8695uart_verify_port, +}; + +static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = { + { + .membase = (void *) KS8695_UART_VA, + .mapbase = KS8695_UART_VA, + .iotype = SERIAL_IO_MEM, + .irq = KS8695_IRQ_UART_TX, + .uartclk = CLOCK_TICK_RATE * 16, + .fifosize = 16, + .ops = &ks8695uart_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + } +}; + +#ifdef CONFIG_SERIAL_KS8695_CONSOLE +static void ks8695_console_putchar(struct uart_port *port, int ch) +{ + while (!(UART_GET_LSR(port) & URLS_URTHRE)) + barrier(); + + UART_PUT_CHAR(port, ch); +} + +static void ks8695_console_write(struct console *co, const char *s, u_int count) +{ + struct uart_port *port = ks8695uart_ports + co->index; + + uart_console_write(port, s, count, ks8695_console_putchar); +} + +static void __init ks8695_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) +{ + unsigned int lcr; + + lcr = UART_GET_LCR(port); + + switch (lcr & URLC_PARITY) { + case URPE_ODD: + *parity = 'o'; + break; + case URPE_EVEN: + *parity = 'e'; + break; + default: + *parity = 'n'; + } + + switch (lcr & URLC_URCL) { + case URCL_5: + *bits = 5; + break; + case URCL_6: + *bits = 6; + break; + case URCL_7: + *bits = 7; + break; + default: + *bits = 8; + } + + *baud = port->uartclk / (UART_GET_BRDR(port) & 0x0FFF); + *baud /= 16; + *baud &= 0xFFFFFFF0; +} + +static int __init ks8695_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + port = uart_get_console(ks8695uart_ports, SERIAL_KS8695_NR, co); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + ks8695_console_get_options(port, &baud, &parity, &bits); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +extern struct uart_driver ks8695_reg; + +static struct console ks8695_console = { + .name = SERIAL_KS8695_DEVNAME, + .write = ks8695_console_write, + .device = uart_console_device, + .setup = ks8695_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &ks8695_reg, +}; + +static int __init ks8695_console_init(void) +{ + register_console(&ks8695_console); + return 0; +} + +console_initcall(ks8695_console_init); + +#define KS8695_CONSOLE &ks8695_console +#else +#define KS8695_CONSOLE NULL +#endif + +static struct uart_driver ks8695_reg = { + .owner = THIS_MODULE, + .driver_name = "serial_ks8695", + .dev_name = SERIAL_KS8695_DEVNAME, + .major = SERIAL_KS8695_MAJOR, + .minor = SERIAL_KS8695_MINOR, + .nr = SERIAL_KS8695_NR, + .cons = KS8695_CONSOLE, +}; + +static int __init ks8695uart_init(void) +{ + int i, ret; + + printk(KERN_INFO "Serial: Micrel KS8695 UART driver\n"); + + ret = uart_register_driver(&ks8695_reg); + if (ret) + return ret; + + for (i = 0; i < SERIAL_KS8695_NR; i++) + uart_add_one_port(&ks8695_reg, &ks8695uart_ports[0]); + + return 0; +} + +static void __exit ks8695uart_exit(void) +{ + int i; + + for (i = 0; i < SERIAL_KS8695_NR; i++) + uart_remove_one_port(&ks8695_reg, &ks8695uart_ports[0]); + uart_unregister_driver(&ks8695_reg); +} + +module_init(ks8695uart_init); +module_exit(ks8695uart_exit); + +MODULE_DESCRIPTION("KS8695 serial port driver"); +MODULE_AUTHOR("Micrel Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 8065f2b5370..f771a7cae9e 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -210,7 +210,7 @@ config USB_OTG config USB_GADGET_AT91 boolean "AT91 USB Device Port" - depends on ARCH_AT91 + depends on ARCH_AT91 && !ARCH_AT91SAM9RL select USB_GADGET_SELECTED help Many Atmel AT91 processors (such as the AT91RM2000) have a diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h new file mode 100644 index 00000000000..8a9708a370c --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -0,0 +1,110 @@ +/* + * include/asm-arm/arch-at91/at91sam9260.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Common definitions. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_H +#define AT91SAM9RL_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller */ +#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91SAM9RL_ID_US0 6 /* USART 0 */ +#define AT91SAM9RL_ID_US1 7 /* USART 1 */ +#define AT91SAM9RL_ID_US2 8 /* USART 2 */ +#define AT91SAM9RL_ID_US3 9 /* USART 3 */ +#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ +#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ +#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ +#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ +#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ +#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ +#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ +#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9RL_BASE_TCB0 0xfffa0000 +#define AT91SAM9RL_BASE_TC0 0xfffa0000 +#define AT91SAM9RL_BASE_TC1 0xfffa0040 +#define AT91SAM9RL_BASE_TC2 0xfffa0080 +#define AT91SAM9RL_BASE_MCI 0xfffa4000 +#define AT91SAM9RL_BASE_TWI0 0xfffa8000 +#define AT91SAM9RL_BASE_TWI1 0xfffac000 +#define AT91SAM9RL_BASE_US0 0xfffb0000 +#define AT91SAM9RL_BASE_US1 0xfffb4000 +#define AT91SAM9RL_BASE_US2 0xfffb8000 +#define AT91SAM9RL_BASE_US3 0xfffbc000 +#define AT91SAM9RL_BASE_SSC0 0xfffc0000 +#define AT91SAM9RL_BASE_SSC1 0xfffc4000 +#define AT91SAM9RL_BASE_PWMC 0xfffc8000 +#define AT91SAM9RL_BASE_SPI 0xfffcc000 +#define AT91SAM9RL_BASE_TSC 0xfffd0000 +#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 +#define AT91SAM9RL_BASE_AC97C 0xfffd8000 +#define AT91_BASE_SYS 0xffffc000 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) + + +/* + * Internal Memory. + */ +#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ + +#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h new file mode 100644 index 00000000000..b15f11b7c08 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h @@ -0,0 +1,96 @@ +/* + * include/asm-arm/arch-at91/at91sam9rl_matrix.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_MATRIX_H +#define AT91SAM9RL_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + + +#endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index 7ef4eebe9f8..ef93c30a9c5 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -26,6 +26,8 @@ #define ARCH_ID_AT91SAM9XE256 0x329a93a0 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); @@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void) #define cpu_is_at91sam9263() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154d..46835e945ae 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -24,6 +24,8 @@ #include <asm/arch/at91sam9261.h> #elif defined(CONFIG_ARCH_AT91SAM9263) #include <asm/arch/at91sam9263.h> +#elif defined(CONFIG_ARCH_AT91SAM9RL) +#include <asm/arch/at91sam9rl.h> #else #error "Unsupported AT91 processor" #endif @@ -69,22 +71,5 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -#ifndef __ASSEMBLY__ -#include <asm/io.h> - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif #endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327ec04..80073fd36b8 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -29,4 +29,22 @@ #define __mem_pci(a) (a) +#ifndef __ASSEMBLY__ + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif + #endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb9a9c..1127a3b5e92 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -21,6 +21,7 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H +#include <asm/io.h> #include <asm/arch/at91_aic.h> #define NR_AIC_IRQS 32 diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f41636d607a..2df1ee12dfb 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -37,6 +37,11 @@ #define AT91SAM9_MASTER_CLOCK 99959500 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91SAM9RL) + +#define AT91SAM9_MASTER_CLOCK 100000000 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + #endif #endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28304b..30ac587b3b4 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include <asm/hardware.h> +#include <asm/io.h> #include <asm/arch/at91_dbgu.h> /* diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S index 0cfb89b229d..038b761fdad 100644 --- a/include/asm-arm/arch-cl7500/entry-macro.S +++ b/include/asm-arm/arch-cl7500/entry-macro.S @@ -1,6 +1,14 @@ #include <asm/hardware.h> #include <asm/hardware/entry-macro-iomd.S> + + .equ ioc_base_high, IOC_BASE & 0xff000000 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 + .macro get_irqnr_preamble, base, tmp + mov \base, #ioc_base_high @ point at IOC + .if ioc_base_low + orr \base, \base, #ioc_base_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h new file mode 100644 index 00000000000..a97dfbb15e5 --- /dev/null +++ b/include/asm-arm/arch-davinci/common.h @@ -0,0 +1,19 @@ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +struct sys_timer; + +extern struct sys_timer davinci_timer; + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S new file mode 100644 index 00000000000..e6c0f0d5d06 --- /dev/null +++ b/include/asm-arm/arch-davinci/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro for DaVinci + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x01000000 @ physical base address + movne \rx, #0xfe000000 @ virtual base + orr \rx, \rx, #0x00c20000 @ UART 0 + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h new file mode 100644 index 00000000000..8e2f2d0ba66 --- /dev/null +++ b/include/asm-arm/arch-davinci/dma.h @@ -0,0 +1,16 @@ +/* + * DaVinci DMA definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S new file mode 100644 index 00000000000..3ebfcc5cb58 --- /dev/null +++ b/include/asm-arm/arch-davinci/entry-macro.S @@ -0,0 +1,32 @@ +/* + * Low-level IRQ helper macros for TI DaVinci-based platforms + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <asm/arch/io.h> +#include <asm/arch/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \tmp, [\base, #0x14] + mov \tmp, \tmp, lsr #2 + sub \irqnr, \tmp, #1 + cmp \tmp, #0 + .endm + + .macro irq_prio_table + .endm diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 00000000000..60362d80229 --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,14 @@ +/* + * Common hardware definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 00000000000..e7accb91086 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h @@ -0,0 +1,79 @@ +/* + * DaVinci IO address definitions + * + * Copied from include/asm/arm/arch-omap/io.h + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_p2v(pa) ((pa) + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define IO_ADDRESS(x) io_p2v(x) + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define PCIO_BASE 0 +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#ifndef __ASSEMBLER__ + +/* + * Functions to access the DaVinci IO region + * + * NOTE: - Use davinci_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) + +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) + +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] + +#define __REG(paddr) __REGV32(io_p2v(paddr)) +#else + +#define __REG(x) (*((volatile unsigned long *)io_p2v(x))) + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_ARCH_IO_H */ diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h new file mode 100644 index 00000000000..f4c5ca6da9f --- /dev/null +++ b/include/asm-arm/arch-davinci/irqs.h @@ -0,0 +1,105 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* Base address */ +#define DAVINCI_ARM_INTC_BASE 0x01C48000 + +/* Interrupt lines */ +#define IRQ_VDINT0 0 +#define IRQ_VDINT1 1 +#define IRQ_VDINT2 2 +#define IRQ_HISTINT 3 +#define IRQ_H3AINT 4 +#define IRQ_PRVUINT 5 +#define IRQ_RSZINT 6 +#define IRQ_VFOCINT 7 +#define IRQ_VENCINT 8 +#define IRQ_ASQINT 9 +#define IRQ_IMXINT 10 +#define IRQ_VLCDINT 11 +#define IRQ_USBINT 12 +#define IRQ_EMACINT 13 + +#define IRQ_CCINT0 16 +#define IRQ_CCERRINT 17 +#define IRQ_TCERRINT0 18 +#define IRQ_TCERRINT 19 +#define IRQ_PSCIN 20 + +#define IRQ_IDE 22 +#define IRQ_HPIINT 23 +#define IRQ_MBXINT 24 +#define IRQ_MBRINT 25 +#define IRQ_MMCINT 26 +#define IRQ_SDIOINT 27 +#define IRQ_MSINT 28 +#define IRQ_DDRINT 29 +#define IRQ_AEMIFINT 30 +#define IRQ_VLQINT 31 +#define IRQ_TINT0_TINT12 32 +#define IRQ_TINT0_TINT34 33 +#define IRQ_TINT1_TINT12 34 +#define IRQ_TINT1_TINT34 35 +#define IRQ_PWMINT0 36 +#define IRQ_PWMINT1 37 +#define IRQ_PWMINT2 38 +#define IRQ_I2C 39 +#define IRQ_UARTINT0 40 +#define IRQ_UARTINT1 41 +#define IRQ_UARTINT2 42 +#define IRQ_SPINT0 43 +#define IRQ_SPINT1 44 + +#define IRQ_DSP2ARM0 46 +#define IRQ_DSP2ARM1 47 +#define IRQ_GPIO0 48 +#define IRQ_GPIO1 49 +#define IRQ_GPIO2 50 +#define IRQ_GPIO3 51 +#define IRQ_GPIO4 52 +#define IRQ_GPIO5 53 +#define IRQ_GPIO6 54 +#define IRQ_GPIO7 55 +#define IRQ_GPIOBNK0 56 +#define IRQ_GPIOBNK1 57 +#define IRQ_GPIOBNK2 58 +#define IRQ_GPIOBNK3 59 +#define IRQ_GPIOBNK4 60 +#define IRQ_COMMTX 61 +#define IRQ_COMMRX 62 +#define IRQ_EMUINT 63 + +#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_GPIO 71 + +#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) + +#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h new file mode 100644 index 00000000000..dd1625c23cf --- /dev/null +++ b/include/asm-arm/arch-davinci/memory.h @@ -0,0 +1,64 @@ +/* + * DaVinci memory space definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/************************************************************************** + * Included Files + **************************************************************************/ +#include <asm/page.h> +#include <asm/sizes.h> + +/************************************************************************** + * Definitions + **************************************************************************/ +#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ + +#define PHYS_OFFSET DAVINCI_DDR_BASE + +/* + * Increase size of DMA-consistent memory region + */ +#define CONSISTENT_DMA_SIZE (14<<20) + +#ifndef __ASSEMBLY__ +/* + * Restrict DMA-able region to workaround silicon bug. The bug + * restricts buffers available for DMA to video hardware to be + * below 128M + */ +static inline void +__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) +{ + unsigned int sz = (128<<20) >> PAGE_SHIFT; + + if (node != 0) + sz = 0; + + size[1] = size[0] - sz; + size[0] = sz; +} + +#define arch_adjust_zones(node, zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) + +#endif + +/* + * Bus address is physical address + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h new file mode 100644 index 00000000000..4977aa071e1 --- /dev/null +++ b/include/asm-arm/arch-davinci/psc.h @@ -0,0 +1,76 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h new file mode 100644 index 00000000000..ed418ef7680 --- /dev/null +++ b/include/asm-arm/arch-davinci/serial.h @@ -0,0 +1,20 @@ +/* + * DaVinci serial device definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include <asm/arch/io.h> + +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h new file mode 100644 index 00000000000..440ac515804 --- /dev/null +++ b/include/asm-arm/arch-davinci/system.h @@ -0,0 +1,29 @@ +/* + * DaVinci system defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/io.h> +#include <asm/hardware.h> + +extern void davinci_watchdog_reset(void); + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static void arch_reset(char mode) +{ + davinci_watchdog_reset(); +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h new file mode 100644 index 00000000000..52827567841 --- /dev/null +++ b/include/asm-arm/arch-davinci/timex.h @@ -0,0 +1,17 @@ +/* + * DaVinci timer defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* The source frequency for the timers is the 27MHz clock */ +#define CLOCK_TICK_RATE 27000000 + +#endif /* __ASM_ARCH_TIMEX_H__ */ diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h new file mode 100644 index 00000000000..f6d1570f720 --- /dev/null +++ b/include/asm-arm/arch-davinci/uncompress.h @@ -0,0 +1,35 @@ +/* + * Serial port stubs for kernel decompress status messages + * + * Author: Anant Gole + * (C) Copyright (C) 2006, Texas Instruments, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/serial_reg.h> +#include <asm/arch/serial.h> + +/* PORT_16C550A, in polled non-fifo mode */ + +static void putc(char c) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); + uart[UART_TX] = c; +} + +static inline void flush(void) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h new file mode 100644 index 00000000000..9b47fa89b33 --- /dev/null +++ b/include/asm-arm/arch-davinci/vmalloc.h @@ -0,0 +1,15 @@ +/* + * DaVinci vmalloc definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <asm/memory.h> +#include <asm/arch/io.h> + +/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ +#define VMALLOC_END (IO_VIRT - (2<<20)) diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S index aa23c5d6c69..f242be5c49b 100644 --- a/include/asm-arm/arch-ebsa110/entry-macro.S +++ b/include/asm-arm/arch-ebsa110/entry-macro.S @@ -16,13 +16,13 @@ .endm .macro get_irqnr_preamble, base, tmp + mov \base, #IRQ_STAT .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, stat, base, tmp - mov \base, #IRQ_STAT ldrb \stat, [\base] @ get interrupts mov \irqnr, #0 tst \stat, #15 diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S index 4203dbf1066..e63064edb73 100644 --- a/include/asm-arm/arch-ebsa285/entry-macro.S +++ b/include/asm-arm/arch-ebsa285/entry-macro.S @@ -11,24 +11,24 @@ #include <asm/arch/irqs.h> #include <asm/hardware/dec21285.h> + .equ dc21285_high, ARMCSR_BASE & 0xff000000 + .equ dc21285_low, ARMCSR_BASE & 0x00ffffff + .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp + mov \base, #dc21285_high + .if dc21285_low + orr \base, \base, #dc21285_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 .endm - .equ dc21285_high, ARMCSR_BASE & 0xff000000 - .equ dc21285_low, ARMCSR_BASE & 0x00ffffff - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #dc21285_high - .if dc21285_low - orr r4, r4, #dc21285_low - .endif - ldr \irqstat, [r4, #0x180] @ get interrupts + ldr \irqstat, [\base, #0x180] @ get interrupts mov \irqnr, #IRQ_SDRAMPARITY tst \irqstat, #IRQ_MASK_SDRAMPARITY diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4ad82b..a6e0f9e6ddc 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h @@ -27,7 +27,7 @@ extern void __iomem * __iop13xx_io(unsigned long io_addr); extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop13xx_iounmap(void __iomem *addr); extern u32 iop13xx_atue_mem_base; diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c332..e6736c3d1f7 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_MU_PMMR_OFFSET 0x00004000 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) @@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) /*=======================================================================*/ +/*============================MESSAGING UNIT=============================*/ +#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) +#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) +#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) +#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) +#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) +#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) +#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) +#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) +#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) +#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) +#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) +#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) +#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) +#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) +#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) +#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) + +#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) +#define IOP13XX_MU_BASE_PHYS (0xff000000) +#define IOP13XX_MU_BASE_PCI (0xff000000) +#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) +#define IOP13XX_MU_MIMR_CORE_SELECT (15) +/*=======================================================================*/ + /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 5c6fac2a400..054e7acb5bf 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ +#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ @@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ #define IRQ_IOP13XX_HPI (127) /* 31 */ +#ifdef CONFIG_PCI_MSI +#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) +#else #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#endif + #define NR_IRQS NR_IOP13XX_IRQS #endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h new file mode 100644 index 00000000000..b80c5ae17e9 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/msi.h @@ -0,0 +1,11 @@ +#ifndef _IOP13XX_MSI_H_ +#define _IOP13XX_MSI_H_ +#ifdef CONFIG_PCI_MSI +void iop13xx_msi_init(void); +#else +static inline void iop13xx_msi_init(void) +{ + return; +} +#endif +#endif diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16af505..958af751a48 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -14,7 +14,7 @@ #include <asm/hardware.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f7589b29..fec9c53e2b1 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -14,7 +14,7 @@ #include <asm/hardware.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S new file mode 100644 index 00000000000..cd5f2fb1f06 --- /dev/null +++ b/include/asm-arm/arch-ks8695/debug-macro.S @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-ks8695/debug-macro.S + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Debug macros + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm/hardware.h> +#include <asm/arch/regs-uart.h> + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =KS8695_UART_PA @ physical base address + ldrne \rx, =KS8695_UART_VA @ virtual base address + .endm + + .macro senduart, rd, rx + str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register + .endm + + .macro busyuart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTE @ Holding & Shift registers empty? + beq 1001b + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTHRE @ Holding Register empty? + beq 1001b + .endm diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h new file mode 100644 index 00000000000..b0364dce463 --- /dev/null +++ b/include/asm-arm/arch-ks8695/devices.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-ks8695/devices.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DEVICES_H +#define __ASM_ARCH_DEVICES_H + +#include <linux/pci.h> + + /* Ethernet */ +extern void __init ks8695_add_device_wan(void); +extern void __init ks8695_add_device_lan(void); +extern void __init ks8695_add_device_hpna(void); + + /* PCI */ +#define KS8695_MODE_PCI 0 +#define KS8695_MODE_MINIPCI 1 +#define KS8695_MODE_CARDBUS 2 + +struct ks8695_pci_cfg { + short mode; + int (*map_irq)(struct pci_dev *, u8, u8); +}; +extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); + +#endif diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h new file mode 100644 index 00000000000..e5159ed42a4 --- /dev/null +++ b/include/asm-arm/arch-ks8695/dma.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/arch-ks8695/dma.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S new file mode 100644 index 00000000000..e34bdf85920 --- /dev/null +++ b/include/asm-arm/arch-ks8695/entry-macro.S @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/entry-macro.S + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * Low-level IRQ helper macros for KS8695 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include <asm/hardware.h> +#include <asm/arch/regs-irq.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register + + teq \irqstat, #0 + beq 1001f + + mov \irqnr, #0 + + tst \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tst \irqstat, #0x0f + moveq \irqstat, \irqstat, lsr #4 + addeq \irqnr, \irqnr, #4 + tst \irqstat, #0x03 + moveq \irqstat, \irqstat, lsr #2 + addeq \irqnr, \irqnr, #2 + tst \irqstat, #0x01 + addeqs \irqnr, \irqnr, #1 +1001: + .endm diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h new file mode 100644 index 00000000000..cb732bff328 --- /dev/null +++ b/include/asm-arm/arch-ks8695/hardware.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-ks8695/hardware.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Memory Map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> + +/* + * Physical RAM address. + */ +#define KS8695_SDRAM_PA 0x00000000 + + +/* + * We map an entire MiB with the System Configuration Registers in even + * though only 64KiB is needed. This makes it easier for use with the + * head debug code as the initial MMU setup only deals in L1 sections. + */ +#define KS8695_IO_PA 0x03F00000 +#define KS8695_IO_VA 0xF0000000 +#define KS8695_IO_SIZE SZ_1M + +#define KS8695_PCIMEM_PA 0x60000000 +#define KS8695_PCIMEM_SIZE SZ_512M + +#define KS8695_PCIIO_PA 0x80000000 +#define KS8695_PCIIO_SIZE SZ_64K + + +/* + * PCI support + */ +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 + +#endif diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h new file mode 100644 index 00000000000..8edc4bd6aad --- /dev/null +++ b/include/asm-arm/arch-ks8695/io.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-ks8695/io.h + * + * Copyright (C) 2006 Andrew Victor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h new file mode 100644 index 00000000000..8b1c4fe96a8 --- /dev/null +++ b/include/asm-arm/arch-ks8695/irqs.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-ks8695/irqs.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + + +#define NR_IRQS 32 + +/* + * IRQ definitions + */ +#define KS8695_IRQ_COMM_RX 0 +#define KS8695_IRQ_COMM_TX 1 +#define KS8695_IRQ_EXTERN0 2 +#define KS8695_IRQ_EXTERN1 3 +#define KS8695_IRQ_EXTERN2 4 +#define KS8695_IRQ_EXTERN3 5 +#define KS8695_IRQ_TIMER0 6 +#define KS8695_IRQ_TIMER1 7 +#define KS8695_IRQ_UART_TX 8 +#define KS8695_IRQ_UART_RX 9 +#define KS8695_IRQ_UART_LINE_STATUS 10 +#define KS8695_IRQ_UART_MODEM_STATUS 11 +#define KS8695_IRQ_LAN_RX_STOP 12 +#define KS8695_IRQ_LAN_TX_STOP 13 +#define KS8695_IRQ_LAN_RX_BUF 14 +#define KS8695_IRQ_LAN_TX_BUF 15 +#define KS8695_IRQ_LAN_RX_STATUS 16 +#define KS8695_IRQ_LAN_TX_STATUS 17 +#define KS8695_IRQ_HPNA_RX_STOP 18 +#define KS8695_IRQ_HPNA_TX_STOP 19 +#define KS8695_IRQ_HPNA_RX_BUF 20 +#define KS8695_IRQ_HPNA_TX_BUF 21 +#define KS8695_IRQ_HPNA_RX_STATUS 22 +#define KS8695_IRQ_HPNA_TX_STATUS 23 +#define KS8695_IRQ_BUS_ERROR 24 +#define KS8695_IRQ_WAN_RX_STOP 25 +#define KS8695_IRQ_WAN_TX_STOP 26 +#define KS8695_IRQ_WAN_RX_BUF 27 +#define KS8695_IRQ_WAN_TX_BUF 28 +#define KS8695_IRQ_WAN_RX_STATUS 29 +#define KS8695_IRQ_WAN_TX_STATUS 30 +#define KS8695_IRQ_WAN_LINK 31 + +#endif diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h new file mode 100644 index 00000000000..24f6a6e4a30 --- /dev/null +++ b/include/asm-arm/arch-ks8695/memory.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-ks8695/memory.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 Memory definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/hardware.h> + +/* + * Physical SRAM offset. + */ +#define PHYS_OFFSET KS8695_SDRAM_PA + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_PCI + +/* PCI mappings */ +#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) +#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) + +/* Platform-bus mapping */ +extern struct bus_type platform_bus_type; +#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) +#define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ + __phys_to_virt(x) : __bus_to_virt(x); }) +#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ + (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) +#define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) + +#else + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif + +#endif + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h new file mode 100644 index 00000000000..57fcf9fc82e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-gpio.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/regs-gpio.h + * + * Copyright (C) 2007 Andrew Victor + * + * KS8695 - GPIO control registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_GPIO_H +#define KS8695_GPIO_H + +#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) +#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) +#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) + + +#define KS8695_IOPM (0x00) /* I/O Port Mode Register */ +#define KS8695_IOPC (0x04) /* I/O Port Control Register */ +#define KS8695_IOPD (0x08) /* I/O Port Data Register */ + + +/* Port Mode Register */ +#define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ + +/* Port Control Register */ +#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ +#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ +#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ +#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ +#define IOPC_IOEINT3_MODE(x) ((x) << 12) +#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ +#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ +#define IOPC_IOEINT2_MODE(x) ((x) << 8) +#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ +#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ +#define IOPC_IOEINT1_MODE(x) ((x) << 4) +#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ +#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ +#define IOPC_IOEINT0_MODE(x) ((x) << 0) + + /* Trigger Modes */ +#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ +#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ +#define IOPC_TM_RISING (2) /* Rising Edge Detection */ +#define IOPC_TM_FALLING (4) /* Falling Edge Detection */ +#define IOPC_TM_EDGE (6) /* Both Edge Detection */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h new file mode 100644 index 00000000000..14091cdec10 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-hpna.h @@ -0,0 +1,25 @@ +/* + * include/asm-arm/arch-ks8695/regs-wan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - HPNA Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_HPNA_H +#define KS8695_HPNA_H + +#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) +#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) +#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) + + +/* + * HPNA registers + */ + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h new file mode 100644 index 00000000000..70b193f6b75 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-irq.h @@ -0,0 +1,41 @@ +/* + * include/asm-arm/arch-ks8695/regs-irq.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - IRQ registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_IRQ_H +#define KS8695_IRQ_H + +#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) +#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) +#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) + + +/* + * Interrupt Controller registers + */ +#define KS8695_INTMC (0x00) /* Mode Control Register */ +#define KS8695_INTEN (0x04) /* Interrupt Enable Register */ +#define KS8695_INTST (0x08) /* Interrupt Status Register */ +#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ +#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ +#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ +#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ +#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ +#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ +#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ +#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ +#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ +#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ +#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h new file mode 100644 index 00000000000..a63bd61c64e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-lan.h @@ -0,0 +1,65 @@ +/* + * include/asm-arm/arch-ks8695/regs-lan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - LAN Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_LAN_H +#define KS8695_LAN_H + +#define KS8695_LAN_OFFSET (0xF0000 + 0x8000) +#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) +#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) + + +/* + * LAN registers + */ +#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ +#define KS8695_LMDRXC (0x04) /* DMA Receive Control */ +#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ +#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ +#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ +#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ +#define KS8695_LMAL (0x18) /* MAC Station Address Low */ +#define KS8695_LMAH (0x1c) /* MAC Station Address High */ +#define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ +#define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ + + +/* DMA Transmit Control Register */ +#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ +#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ +#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ +#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ +#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ +#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ +#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ +#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ +#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ +#define LMDTXC_LMTE (1 << 0) /* TX Enable */ + +/* DMA Receive Control Register */ +#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ +#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ +#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ +#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ +#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ +#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ +#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ +#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ +#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ +#define LMDRXC_LMRA (1 << 2) /* Receive All */ +#define LMDRXC_LMRE (1 << 1) /* RX Enable */ + +/* Additional Station Address High */ +#define LMAAH_E (1 << 31) /* Address Enabled */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h new file mode 100644 index 00000000000..76b38e0862e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-mem.h @@ -0,0 +1,89 @@ +/* + * include/asm-arm/arch-ks8695/regs-mem.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Memory Controller registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_MEM_H +#define KS8695_MEM_H + +#define KS8695_MEM_OFFSET (0xF0000 + 0x4000) +#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) +#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) + + +/* + * Memory Controller Registers + */ +#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ +#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ +#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ +#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ +#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ +#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ +#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ +#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ +#define KS8695_SDGCON (0x38) /* SDRAM General Control */ +#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ +#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ + + +/* External I/O Access Control Registers */ +#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ +#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ +#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ +#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ +#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ + +/* ROM/SRAM/Flash Control Register */ +#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ +#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ +#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ +#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ +#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ +#define PMC_NORMAL (0 << 0) +#define PMC_4WORD (1 << 0) +#define PMC_8WORD (2 << 0) +#define PMC_16WORD (3 << 0) + +/* External I/O and ROM/SRAM/Flash General Register */ +#define ERGCON_TMULT (3 << 28) /* Time Multiplier */ +#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ +#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ +#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ +#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ +#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ + +/* SDRAM Control Register */ +#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ +#define SDCON_DBCAB (3 << 8) /* Column Address Bits */ +#define SDCON_DBBNUM (1 << 3) /* Number of Banks */ +#define SDCON_DBDBW (3 << 1) /* Data Bus Width */ + +/* SDRAM General Control Register */ +#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ +#define SDGCON_SDCAS (3 << 0) /* CAS latency */ + +/* SDRAM Buffer Control Register */ +#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ +#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ +#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ +#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ +#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ +#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ +#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ +#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ + +/* SDRAM Refresh Timer Register */ +#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h new file mode 100644 index 00000000000..632ca6601a9 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-misc.h @@ -0,0 +1,97 @@ +/* + * include/asm-arm/arch-ks8695/regs-misc.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Miscellaneous Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_MISC_H +#define KS8695_MISC_H + +#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) +#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) +#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) + + +/* + * Miscellaneous registers + */ +#define KS8695_DID (0x00) /* Device ID */ +#define KS8695_RID (0x04) /* Revision ID */ +#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ +#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ +#define KS8695_WPPM (0x10) /* WAN PHY Power Management */ +#define KS8695_PPS (0x1c) /* PHY PowerSave */ + +/* Device ID Register */ +#define DID_ID (0xffff << 0) /* Device ID */ + +/* Revision ID Register */ +#define RID_SUBID (0xf << 4) /* Sub-Device ID */ +#define RID_REVISION (0xf << 0) /* Revision ID */ + +/* HPNA Miscellaneous Control Register */ +#define HMC_HSS (1 << 1) /* Speed */ +#define HMC_HDS (1 << 0) /* Duplex */ + +/* WAN Miscellaneous Control Register */ +#define WMC_WANC (1 << 30) /* Auto-negotiation complete */ +#define WMC_WANR (1 << 29) /* Auto-negotiation restart */ +#define WMC_WANAP (1 << 28) /* Advertise Pause */ +#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ +#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ +#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ +#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ +#define WMC_WLS (1 << 23) /* Link status */ +#define WMC_WDS (1 << 22) /* Duplex status */ +#define WMC_WSS (1 << 21) /* Speed status */ +#define WMC_WLPP (1 << 20) /* Link Partner Pause */ +#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ +#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ +#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ +#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ +#define WMC_WAND (1 << 15) /* Auto-negotiation disable */ +#define WMC_WANF100 (1 << 14) /* Force 100 */ +#define WMC_WANFF (1 << 13) /* Force FDX */ +#define WMC_WLED1S (7 << 4) /* LED1 Select */ +#define WLED1S_SPEED (0 << 4) +#define WLED1S_LINK (1 << 4) +#define WLED1S_DUPLEX (2 << 4) +#define WLED1S_COLLISION (3 << 4) +#define WLED1S_ACTIVITY (4 << 4) +#define WLED1S_FDX_COLLISION (5 << 4) +#define WLED1S_LINK_ACTIVITY (6 << 4) +#define WMC_WLED0S (7 << 0) /* LED0 Select */ +#define WLED0S_SPEED (0 << 0) +#define WLED0S_LINK (1 << 0) +#define WLED0S_DUPLEX (2 << 0) +#define WLED0S_COLLISION (3 << 0) +#define WLED0S_ACTIVITY (4 << 0) +#define WLED0S_FDX_COLLISION (5 << 0) +#define WLED0S_LINK_ACTIVITY (6 << 0) + +/* WAN PHY Power Management Register */ +#define WPPM_WLPBK (1 << 14) /* Local Loopback */ +#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ +#define WPPM_WPI (1 << 12) /* PHY isolate */ +#define WPPM_WFL (1 << 10) /* Force link */ +#define WPPM_MDIXS (1 << 9) /* MDIX Status */ +#define WPPM_FEF (1 << 8) /* Far End Fault */ +#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ +#define WPPM_TXDIS (1 << 6) /* Disable transmitter */ +#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ +#define WPPM_PD (1 << 4) /* Power Down */ +#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ +#define WPPM_FMDX (1 << 2) /* Force MDIX */ +#define WPPM_LPBK (1 << 1) /* MAX Loopback */ + +/* PHY Power Save Register */ +#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h new file mode 100644 index 00000000000..286d6d488df --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-pci.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/regs-pci.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - PCI bridge registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define KS8695_PCI_OFFSET (0xF0000 + 0x2000) +#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) +#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) + + +#define KS8695_CRCFID (0x000) /* Configuration: Identification */ +#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ +#define KS8695_CRCFRV (0x008) /* Configuration: Revision */ +#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ +#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ +#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ +#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ +#define KS8695_PBCA (0x100) /* Bridge Configuration Address */ +#define KS8695_PBCD (0x104) /* Bridge Configuration Data */ +#define KS8695_PBM (0x200) /* Bridge Mode */ +#define KS8695_PBCS (0x204) /* Bridge Control and Status */ +#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ +#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ +#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ +#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ +#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ +#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ +#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ +#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ + + +/* Configuration: Identification */ + +/* Configuration: Command and Status */ + +/* Configuration: Revision */ + + + +#define CFRV_GUEST (1 << 23) + +#define PBCA_TYPE1 (1) +#define PBCA_ENABLE (1 << 31) + + diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h new file mode 100644 index 00000000000..5f37be3f2f6 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-switch.h @@ -0,0 +1,66 @@ +/* + * include/asm-arm/arch-ks8695/regs-switch.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Switch Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_SWITCH_H +#define KS8695_SWITCH_H + +#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) +#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) +#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) + + +/* + * Switch registers + */ +#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ +#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ +#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ + +#define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ + +#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ +#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ +#define KS8695_SEIAC (0x50) /* Indirect Access Control */ +#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ +#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ +#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ +#define KS8695_SEAFC (0x60) /* Advance Feature Control */ +#define KS8695_SEDSCPH (0x64) /* TOS Priority High */ +#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ +#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ +#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ +#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ +#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ + + +/* Switch Engine Control 0 */ +#define SEC0_LLED1S (7 << 25) /* LED1 Select */ +#define LLED1S_SPEED (0 << 25) +#define LLED1S_LINK (1 << 25) +#define LLED1S_DUPLEX (2 << 25) +#define LLED1S_COLLISION (3 << 25) +#define LLED1S_ACTIVITY (4 << 25) +#define LLED1S_FDX_COLLISION (5 << 25) +#define LLED1S_LINK_ACTIVITY (6 << 25) +#define SEC0_LLED0S (7 << 22) /* LED0 Select */ +#define LLED0S_SPEED (0 << 22) +#define LLED0S_LINK (1 << 22) +#define LLED0S_DUPLEX (2 << 22) +#define LLED0S_COLLISION (3 << 22) +#define LLED0S_ACTIVITY (4 << 22) +#define LLED0S_FDX_COLLISION (5 << 22) +#define LLED0S_LINK_ACTIVITY (6 << 22) +#define SEC0_ENABLE (1 << 0) /* Enable Switch */ + + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h new file mode 100644 index 00000000000..f3179815b8e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-sys.h @@ -0,0 +1,34 @@ +/* + * include/asm-arm/arch-ks8695/regs-sys.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - System control registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_SYS_H +#define KS8695_SYS_H + +#define KS8695_SYS_OFFSET (0xF0000 + 0x0000) +#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) +#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) + + +#define KS8695_SYSCFG (0x00) /* System Configuration Register */ +#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ + + +/* System Configuration Register */ +#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ + +/* System Clock and Bus Control Register */ +#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ +#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h new file mode 100644 index 00000000000..0a9f7f99ec5 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-timer.h @@ -0,0 +1,40 @@ +/* + * include/asm-arm/arch-ks8695/regs-timer.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Timer registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_TIMER_H +#define KS8695_TIMER_H + +#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) +#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) +#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) + + +/* + * Timer registers + */ +#define KS8695_TMCON (0x00) /* Timer Control Register */ +#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ +#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ +#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ +#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ + + +/* Timer Control Register */ +#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ +#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ + +/* Timer0 Timeout Counter Register */ +#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h new file mode 100644 index 00000000000..a27cb20502a --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-uart.h @@ -0,0 +1,92 @@ +/* + * linux/include/asm-arm/arch-ks8695/regs-uart.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - UART register and bit definitions. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef KS8695_UART_H +#define KS8695_UART_H + +#define KS8695_UART_OFFSET (0xF0000 + 0xE000) +#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) +#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) + + +/* + * UART registers + */ +#define KS8695_URRB (0x00) /* Receive Buffer Register */ +#define KS8695_URTH (0x04) /* Transmit Holding Register */ +#define KS8695_URFC (0x08) /* FIFO Control Register */ +#define KS8695_URLC (0x0C) /* Line Control Register */ +#define KS8695_URMC (0x10) /* Modem Control Register */ +#define KS8695_URLS (0x14) /* Line Status Register */ +#define KS8695_URMS (0x18) /* Modem Status Register */ +#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ +#define KS8695_USR (0x20) /* Status Register */ + + +/* FIFO Control Register */ +#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ +#define URFC_URFRT_1 (0 << 6) +#define URFC_URFRT_4 (1 << 6) +#define URFC_URFRT_8 (2 << 6) +#define URFC_URFRT_14 (3 << 6) +#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ +#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ +#define URFC_URFE (1 << 0) /* FIFO Enable */ + +/* Line Control Register */ +#define URLC_URSBC (1 << 6) /* Set Break Condition */ +#define URLC_PARITY (7 << 3) /* Parity */ +#define URPE_NONE (0 << 3) +#define URPE_ODD (1 << 3) +#define URPE_EVEN (3 << 3) +#define URPE_MARK (5 << 3) +#define URPE_SPACE (7 << 3) +#define URLC_URSB (1 << 2) /* Stop Bits */ +#define URLC_URCL (3 << 0) /* Character Length */ +#define URCL_5 (0 << 0) +#define URCL_6 (1 << 0) +#define URCL_7 (2 << 0) +#define URCL_8 (3 << 0) + +/* Modem Control Register */ +#define URMC_URLB (1 << 4) /* Loop-back mode */ +#define URMC_UROUT2 (1 << 3) /* OUT2 signal */ +#define URMC_UROUT1 (1 << 2) /* OUT1 signal */ +#define URMC_URRTS (1 << 1) /* Request to Send */ +#define URMC_URDTR (1 << 0) /* Data Terminal Ready */ + +/* Line Status Register */ +#define URLS_URRFE (1 << 7) /* Receive FIFO Error */ +#define URLS_URTE (1 << 6) /* Transmit Empty */ +#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ +#define URLS_URBI (1 << 4) /* Break Interrupt */ +#define URLS_URFE (1 << 3) /* Framing Error */ +#define URLS_URPE (1 << 2) /* Parity Error */ +#define URLS_URROE (1 << 1) /* Receive Overrun Error */ +#define URLS_URDR (1 << 0) /* Receive Data Ready */ + +/* Modem Status Register */ +#define URMS_URDCD (1 << 7) /* Data Carrier Detect */ +#define URMS_URRI (1 << 6) /* Ring Indicator */ +#define URMS_URDSR (1 << 5) /* Data Set Ready */ +#define URMS_URCTS (1 << 4) /* Clear to Send */ +#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ +#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ +#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ + +/* Status Register */ +#define USR_UTI (1 << 0) /* Timeout Indication */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h new file mode 100644 index 00000000000..52e35b0d65e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-wan.h @@ -0,0 +1,65 @@ +/* + * include/asm-arm/arch-ks8695/regs-wan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - WAN Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_WAN_H +#define KS8695_WAN_H + +#define KS8695_WAN_OFFSET (0xF0000 + 0x6000) +#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) +#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) + + +/* + * WAN registers + */ +#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ +#define KS8695_WMDRXC (0x04) /* DMA Receive Control */ +#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ +#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ +#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ +#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ +#define KS8695_WMAL (0x18) /* MAC Station Address Low */ +#define KS8695_WMAH (0x1c) /* MAC Station Address High */ +#define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ +#define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ + + +/* DMA Transmit Control Register */ +#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ +#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ +#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ +#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ +#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ +#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ +#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ +#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ +#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ +#define WMDTXC_WMTE (1 << 0) /* TX Enable */ + +/* DMA Receive Control Register */ +#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ +#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ +#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ +#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ +#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ +#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ +#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ +#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ +#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ +#define WMDRXC_WMRA (1 << 2) /* Receive All */ +#define WMDRXC_WMRE (1 << 0) /* RX Enable */ + +/* Additional Station Address High */ +#define WMAAH_E (1 << 31) /* Address Enabled */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h new file mode 100644 index 00000000000..3bc28106d93 --- /dev/null +++ b/include/asm-arm/arch-ks8695/system.h @@ -0,0 +1,48 @@ +/* + * include/asm-arm/arch-s3c2410/system.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * KS8695 - System function defines and includes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/io.h> +#include <asm/arch/regs-timer.h> + +static void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks, + */ + cpu_do_idle(); + +} + +static void arch_reset(char mode) +{ + unsigned int reg; + + if (mode == 's') + cpu_reset(0); + + /* disable timer0 */ + reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + + /* enable watchdog mode */ + __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); + + /* re-enable timer0 */ + __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); +} + +#endif diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h new file mode 100644 index 00000000000..8320d528b90 --- /dev/null +++ b/include/asm-arm/arch-ks8695/timex.h @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-ks8695/timex.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * KS8695 - Time Parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* timers are derived from MCLK, which is 25MHz */ +#define CLOCK_TICK_RATE 25000000 + +#endif diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h new file mode 100644 index 00000000000..733a50855b5 --- /dev/null +++ b/include/asm-arm/arch-ks8695/uncompress.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-ks8695/uncompress.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Kernel uncompressor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <asm/io.h> +#include <asm/arch/regs-uart.h> + +static void putc(char c) +{ + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) + barrier(); + + __raw_writel(c, KS8695_UART_PA + KS8695_URTH); +} + +static inline void flush(void) +{ + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h new file mode 100644 index 00000000000..d1d88e58117 --- /dev/null +++ b/include/asm-arm/arch-ks8695/vmalloc.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-ks8695/vmalloc.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk> + * + * KS8695 vmalloc definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) + +#endif diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 828cc5c114e..f1ec2edd404 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -421,7 +421,9 @@ enum omap24xx_index { /* 24xx clock */ W14_24XX_SYS_CLKOUT, - /* 24xx GPMC wait pin monitoring */ + /* 24xx GPMC chipselects, wait pin monitoring */ + E2_GPMC_NCS2, + L2_GPMC_NCS7, L3_GPMC_WAIT0, N7_GPMC_WAIT1, M1_GPMC_WAIT2, @@ -435,6 +437,7 @@ enum omap24xx_index { /* 24xx GPIO */ M21_242X_GPIO11, + P21_242X_GPIO12, AA10_242X_GPIO13, AA6_242X_GPIO14, AA4_242X_GPIO15, @@ -444,7 +447,9 @@ enum omap24xx_index { Y20_24XX_GPIO60, W4__24XX_GPIO74, M15_24XX_GPIO92, + J15_24XX_GPIO99, V14_24XX_GPIO117, + P14_24XX_GPIO125, /* 242x DBG GPIO */ V4_242X_GPIO49, @@ -486,6 +491,30 @@ enum omap24xx_index { G18_24XX_MMC_CMD_DIR, H15_24XX_MMC_CLKI, + /* Full speed USB */ + J20_24XX_USB0_PUEN, + J19_24XX_USB0_VP, + K20_24XX_USB0_VM, + J18_24XX_USB0_RCV, + K19_24XX_USB0_TXEN, + J14_24XX_USB0_SE0, + K18_24XX_USB0_DAT, + + N14_24XX_USB1_SE0, + W12_24XX_USB1_SE0, + P15_24XX_USB1_DAT, + R13_24XX_USB1_DAT, + W20_24XX_USB1_TXEN, + P13_24XX_USB1_TXEN, + V19_24XX_USB1_RCV, + V12_24XX_USB1_RCV, + + AA10_24XX_USB2_SE0, + Y11_24XX_USB2_DAT, + AA12_24XX_USB2_TXEN, + AA6_24XX_USB2_RCV, + AA4_24XX_USB2_TLLSE0, + /* Keypad GPIO*/ T19_24XX_KBR0, R19_24XX_KBR1, diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 138838d4ad7..3b4e2076603 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -14,6 +14,7 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 @@ -40,7 +41,6 @@ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ ldr \tmp, =1021 diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S index 0cfb89b229d..038b761fdad 100644 --- a/include/asm-arm/arch-rpc/entry-macro.S +++ b/include/asm-arm/arch-rpc/entry-macro.S @@ -1,6 +1,14 @@ #include <asm/hardware.h> #include <asm/hardware/entry-macro-iomd.S> + + .equ ioc_base_high, IOC_BASE & 0xff000000 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 + .macro get_irqnr_preamble, base, tmp + mov \base, #ioc_base_high @ point at IOC + .if ioc_base_low + orr \base, \base, #ioc_base_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index cd9e26568f8..c1414658d1c 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h @@ -129,6 +129,7 @@ #define S3C2443_PCLKCON_IIC (1<<4) #define S3C2443_PCLKCON_SDI (1<<5) #define S3C2443_PCLKCON_ADC (1<<7) +#define S3C2443_PCLKCON_AC97 (1<<8) #define S3C2443_PCLKCON_IIS (1<<9) #define S3C2443_PCLKCON_PWMT (1<<10) #define S3C2443_PCLKCON_WDT (1<<11) diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S index 02896762934..127db4aaf4f 100644 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ b/include/asm-arm/arch-sa1100/entry-macro.S @@ -12,16 +12,16 @@ .endm .macro get_irqnr_preamble, base, tmp + mov \base, #0xfa000000 @ ICIP = 0xfa050000 + add \base, \base, #0x00050000 .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #0xfa000000 @ ICIP = 0xfa050000 - add r4, r4, #0x00050000 - ldr \irqstat, [r4] @ get irqs - ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004 + ldr \irqstat, [\base] @ get irqs + ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 ands \irqstat, \irqstat, \irqnr mov \irqnr, #0 beq 1001f diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index 0fae002637a..924d1a8fe36 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S @@ -14,13 +14,13 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status mov \irqnr, #0 teq \irqstat, #0 diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 3a6d3eb2762..684fe064523 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -121,7 +121,7 @@ struct in_ecid { /* Packed card ID information */ typedef struct expansion_card ecard_t; typedef unsigned long *loader_t; -typedef struct { /* Card handler routines */ +typedef struct expansion_card_ops { /* Card handler routines */ void (*irqenable)(ecard_t *ec, int irqnr); void (*irqdisable)(ecard_t *ec, int irqnr); int (*irqpending)(ecard_t *ec); @@ -179,6 +179,8 @@ struct expansion_card { u64 dma_mask; }; +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); + struct in_chunk_dir { unsigned int start_offset; union { @@ -224,6 +226,10 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) extern int ecard_request_resources(struct expansion_card *ec); extern void ecard_release_resources(struct expansion_card *ec); +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize); +#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) + extern struct bus_type ecard_bus_type; #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) diff --git a/include/asm-arm/hardware/entry-macro-iomd.S b/include/asm-arm/hardware/entry-macro-iomd.S index fbed08f298d..9bb580a5b15 100644 --- a/include/asm-arm/hardware/entry-macro-iomd.S +++ b/include/asm-arm/hardware/entry-macro-iomd.S @@ -11,8 +11,6 @@ /* IOC / IOMD based hardware */ #include <asm/hardware/iomd.h> - .equ ioc_base_high, IOC_BASE & 0xff000000 - .equ ioc_base_low, IOC_BASE & 0x00ff0000 .macro disable_fiq mov r12, #ioc_base_high .if ioc_base_low @@ -22,33 +20,29 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #ioc_base_high @ point at IOC - .if ioc_base_low - orr r4, r4, #ioc_base_low - .endif - ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first - ldr \base, =irq_prio_h + ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first + ldr \tmp, =irq_prio_h teq \irqstat, #0 #ifdef IOMD_BASE - ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma - addeq \base, \base, #256 @ irq_prio_h table size + ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma + addeq \tmp, \tmp, #256 @ irq_prio_h table size teqeq \irqstat, #0 bne 2406f #endif - ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority - addeq \base, \base, #256 @ irq_prio_d table size + ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority + addeq \tmp, \tmp, #256 @ irq_prio_d table size teqeq \irqstat, #0 #ifdef IOMD_IRQREQC - ldreqb \irqstat, [r4, #IOMD_IRQREQC] - addeq \base, \base, #256 @ irq_prio_l table size + ldreqb \irqstat, [\base, #IOMD_IRQREQC] + addeq \tmp, \tmp, #256 @ irq_prio_l table size teqeq \irqstat, #0 #endif #ifdef IOMD_IRQREQD - ldreqb \irqstat, [r4, #IOMD_IRQREQD] - addeq \base, \base, #256 @ irq_prio_lc table size + ldreqb \irqstat, [\base, #IOMD_IRQREQD] + addeq \tmp, \tmp, #256 @ irq_prio_lc table size teqeq \irqstat, #0 #endif -2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number +2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number .endm /* diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h index 7f50ae0edf1..503843db156 100644 --- a/include/asm-arm/sizes.h +++ b/include/asm-arm/sizes.h @@ -24,6 +24,10 @@ #define __sizes_h 1 /* handy sizes */ +#define SZ_16 0x00000010 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + #define SZ_1K 0x00000400 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h index 2bdc5bd6f79..a762f42cbb7 100644 --- a/include/asm-avr32/arch-at32ap/cpu.h +++ b/include/asm-avr32/arch-at32ap/cpu.h @@ -29,5 +29,6 @@ #define cpu_is_at91sam9260() (0) #define cpu_is_at91sam9261() (0) #define cpu_is_at91sam9263() (0) +#define cpu_is_at91sam9rl() (0) #endif /* __ASM_ARCH_CPU_H */ diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index aa2653a159f..a3ac4c89683 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -139,6 +139,10 @@ /* Blackfin bf5xx */ #define PORT_BFIN 75 +/* Micrel KS8695 */ +#define PORT_KS8695 76 + + #ifdef __KERNEL__ #include <linux/compiler.h> |