diff options
| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2006-07-08 00:42:12 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-07-13 21:26:11 +0100 |
| commit | 2874fe55332e2fb4e9c8e672cf2b7361bb168d17 (patch) | |
| tree | bf62c9191328f2874745f9afb77187d0eca9ee2a | |
| parent | 1058ecda9bedaa2c3438376caa5f1925f3d15bbd (diff) | |
[MIPS] vr41xx: Replace magic number for P4K bit with symbol.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 | ||||
| -rw-r--r-- | include/asm-mips/mipsregs.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index d5111d16543..069803f58f3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -862,7 +862,7 @@ static void __init probe_pcache(void) break; case CPU_VR4133: - write_c0_config(config & ~CONF_EB); + write_c0_config(config & ~VR41_CONF_P4K); case CPU_VR4131: /* Workaround for cache instruction bug of VR4131 */ if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 677668867b9..1f318d70799 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -470,6 +470,7 @@ /* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) |