diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-11-30 01:14:48 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-11-30 01:14:48 +0000 |
| commit | 617667ba724d46ffeccb88ee99e1379f29b0bfa7 (patch) | |
| tree | 9a0ffd3f88a2c5fe063ef45d83d52552e51411a7 | |
| parent | 0550d9d13e02b30efa117d47fcadea450bb23d23 (diff) | |
[MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 0138cb2e456..df04a315d83 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -381,17 +381,21 @@ static inline void local_r4k_flush_cache_mm(void * args) if (!cpu_context(smp_processor_id(), mm)) return; - r4k_blast_dcache(); - /* * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we * only flush the primary caches but R10000 and R12000 behave sane ... + * R4000SC and R4400SC indexed S-cache ops also invalidate primary + * caches, so we can bail out early. */ if (current_cpu_data.cputype == CPU_R4000SC || current_cpu_data.cputype == CPU_R4000MC || current_cpu_data.cputype == CPU_R4400SC || - current_cpu_data.cputype == CPU_R4400MC) + current_cpu_data.cputype == CPU_R4400MC) { r4k_blast_scache(); + return; + } + + r4k_blast_dcache(); } static void r4k_flush_cache_mm(struct mm_struct *mm) |