diff options
| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2006-07-08 00:42:01 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-07-13 21:26:11 +0100 |
| commit | 1058ecda9bedaa2c3438376caa5f1925f3d15bbd (patch) | |
| tree | 838eb8232861cc6b927fedb1e76cd371a61b2fa7 | |
| parent | 30f244aed36f569c2e3ea6e8457bf66adaf98a3d (diff) | |
[MIPS] vr41xx: Changed workaround to recommended method
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 256b6611e71..d5111d16543 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -867,12 +867,13 @@ static void __init probe_pcache(void) /* Workaround for cache instruction bug of VR4131 */ if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || c->processor_id == 0x0c82U) { - config &= ~0x00000030U; config |= 0x00400000U; if (c->processor_id == 0x0c80U) config |= VR41_CONF_BP; write_c0_config(config); - } + } else + c->options |= MIPS_CPU_CACHE_CDEX_P; + icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); c->icache.ways = 2; @@ -882,8 +883,6 @@ static void __init probe_pcache(void) c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); c->dcache.ways = 2; c->dcache.waybit = __ffs(dcache_size/2); - - c->options |= MIPS_CPU_CACHE_CDEX_P; break; case CPU_VR41XX: |