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authorJoonyoung Shim <jy0922.shim@samsung.com>2009-06-16 20:05:57 +0900
committerNicolas Pitre <nico@cam.org>2009-06-19 13:38:53 -0400
commit5587931c30dcf778cf7071d1cbac8ea584706dd8 (patch)
tree00cc383e1c600c8f296754521fc0f383a02dd32b
parent3fade49b734cca2d8c4f1bcd7c3023302b557f3b (diff)
[ARM] Add old Feroceon support to compressed/head.S
This patch supports the cache handling for some old Feroceon cores for which the CPU ID is like 0x41159260. This is a complement to commit ab6d15d50637fc25ee941710b23fed09ceb28db3. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
-rw-r--r--arch/arm/boot/compressed/head.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 01d49be3b2c..4515728c534 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -674,6 +674,15 @@ proc_types:
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
+#ifdef CONFIG_CPU_FEROCEON_OLD_ID
+ /* this conflicts with the standard ARMv5TE entry */
+ .long 0x41009260 @ Old Feroceon
+ .long 0xff00fff0
+ b __armv4_mmu_cache_on
+ b __armv4_mmu_cache_off
+ b __armv5tej_mmu_cache_flush
+#endif
+
.word 0x66015261 @ FA526
.word 0xff01fff1
b __fa526_cache_on