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authorCatalin Marinas <catalin.marinas@arm.com>2009-04-01 13:53:48 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-04-01 22:15:57 +0100
commitfe68e68f6a379d317a87ae24de050a65b11ea1fb (patch)
tree7e6099b993d9385eae4e7a892271c3fd38a7c207
parent01a24d2b9309676ec2e7069cd19f5b1c4a1505e0 (diff)
[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6
Because of an ARM1136 erratum (326103), the current v6_early_abort function needs to set the correct FSR[11] value which determines whether the data abort was caused by a read or write. For legacy reasons (bit 10 not handled by software), bit 10 was also cleared masking out imprecise aborts on ARMv6 CPUs. This patch removes the clearing of bit 10 of FSR. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/abort-ev6.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 94077fbd96b..6f7e70907e4 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -29,10 +29,10 @@ ENTRY(v6_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
/*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
* The test below covers all the write situations, including Java bytecodes
*/
- bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
+ bic r1, r1, #1 << 11 @ clear bit 11 of FSR
tst r3, #PSR_J_BIT @ Java?
movne pc, lr
do_thumb_abort