diff options
| author | Werner Almesberger <werner@openmoko.org> | 2009-02-27 08:03:07 -0300 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-02-27 11:34:01 +0000 |
| commit | efeff568677aa325f84d3ce37c219019887a79eb (patch) | |
| tree | 455f6ff1ae9e64da5bd7b0e146f3b8479fc78b0c | |
| parent | fdca9bf2dae14218704ddd7dc60ad1b198c1d787 (diff) | |
[ARM] S3C64XX: Fix s3c64xx_setrate_clksrc
Some of the rate selection logic in s3c64xx_setrate_clksrc uses what
appears to be parent clock selection logic. This patch corrects it.
I also added a check for overly large dividers to prevent them from
changing unrelated clocks.
Signed-off-by: Werner Almesberger <werner@openmoko.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| -rw-r--r-- | arch/arm/plat-s3c64xx/s3c6400-clock.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 6edbeef6aa9..05b17528041 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -239,10 +239,12 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) rate = clk_round_rate(clk, rate); div = clk_get_rate(clk->parent) / rate; + if (div > 16) + return -EINVAL; val = __raw_readl(reg); - val &= ~sclk->mask; - val |= (rate - 1) << sclk->shift; + val &= ~(0xf << sclk->shift); + val |= (div - 1) << sclk->shift; __raw_writel(val, reg); return 0; |