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authorIngo Molnar <mingo@elte.hu>2009-12-07 13:14:12 +0100
committerIngo Molnar <mingo@elte.hu>2009-12-07 13:14:18 +0100
commitf3d607c6b39bd9cb5000e03e2c0dc2afe1241374 (patch)
tree885b5e0b5bb3d87efc4bfbde69feff2ece32ecac /Documentation/ABI/testing/sysfs-devices-cache_disable
parent8055039c2a2454c7159dcbde3161943b757a6e0e (diff)
parent6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff)
Merge branch 'linus' into x86/urgent
Merge reason: we want to queue up a dependent fix. Signed-off-by: Ingo Molnar <mingo@elte.hu>
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-What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
-Date: August 2008
-KernelVersion: 2.6.27
-Contact: mark.langsdorf@amd.com
-Description: These files exist in every cpu's cache index directories.
- There are currently 2 cache_disable_# files in each
- directory. Reading from these files on a supported
- processor will return that cache disable index value
- for that processor and node. Writing to one of these
- files will cause the specificed cache index to be disabled.
-
- Currently, only AMD Family 10h Processors support cache index
- disable, and only for their L3 caches. See the BIOS and
- Kernel Developer's Guide at
- http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
- for formatting information and other details on the
- cache index disable.
-Users: joachim.deguara@amd.com