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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 15:07:45 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 15:07:45 -0700 |
| commit | b4b9034132c7e1e4474999e688dd7d03b7d97a99 (patch) | |
| tree | c02c571b9e0e59b9ffa18baae23c83f09ff07adb /arch/arm/common/gic.c | |
| parent | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (diff) | |
| parent | 07d265dd59456f702b7d2a1ac471f06ee4adc9ef (diff) | |
Merge branch 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm: (24 commits)
[ARM] 3683/2: ARM: Convert at91rm9200 to generic irq handling
[ARM] 3682/2: ARM: Convert ixp4xx to generic irq handling
[ARM] 3702/1: ARM: Convert ixp23xx to generic irq handling
[ARM] 3701/1: ARM: Convert plat-omap to generic irq handling
[ARM] 3700/1: ARM: Convert lh7a40x to generic irq handling
[ARM] 3699/1: ARM: Convert s3c2410 to generic irq handling
[ARM] 3698/1: ARM: Convert sa1100 to generic irq handling
[ARM] 3697/1: ARM: Convert shark to generic irq handling
[ARM] 3696/1: ARM: Convert clps711x to generic irq handling
[ARM] 3694/1: ARM: Convert ecard driver to generic irq handling
[ARM] 3693/1: ARM: Convert omap1 to generic irq handling
[ARM] 3691/1: ARM: Convert imx to generic irq handling
[ARM] 3688/1: ARM: Convert clps7500 to generic irq handling
[ARM] 3687/1: ARM: Convert integrator to generic irq handling
[ARM] 3685/1: ARM: Convert pxa to generic irq handling
[ARM] 3684/1: ARM: Convert l7200 to generic irq handling
[ARM] 3681/1: ARM: Convert ixp2000 to generic irq handling
[ARM] 3680/1: ARM: Convert footbridge to generic irq handling
[ARM] 3695/1: ARM drivers/pcmcia: Fixup includes
[ARM] 3689/1: ARM drivers/input/touchscreen: Fixup includes
...
Manual conflict resolved in kernel/irq/handle.c (butt-ugly ARM tickless
code).
Diffstat (limited to 'arch/arm/common/gic.c')
| -rw-r--r-- | arch/arm/common/gic.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index c02dc8116a1..f3c1ebfdd0a 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -33,6 +33,7 @@ static void __iomem *gic_dist_base; static void __iomem *gic_cpu_base; +static DEFINE_SPINLOCK(irq_controller_lock); /* * Routines to acknowledge, disable and enable interrupts @@ -52,32 +53,45 @@ static void __iomem *gic_cpu_base; static void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); writel(irq, gic_cpu_base + GIC_CPU_EOI); + spin_unlock(&irq_controller_lock); } static void gic_mask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } static void gic_unmask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } #ifdef CONFIG_SMP -static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu) +static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) { void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3); unsigned int shift = (irq % 4) * 8; + unsigned int cpu = first_cpu(mask_val); u32 val; + spin_lock(&irq_controller_lock); + irq_desc[irq].cpu = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); + spin_unlock(&irq_controller_lock); } #endif @@ -86,7 +100,7 @@ static struct irqchip gic_chip = { .mask = gic_mask_irq, .unmask = gic_unmask_irq, #ifdef CONFIG_SMP - .set_cpu = gic_set_cpu, + .set_affinity = gic_set_cpu, #endif }; |