diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-10 16:45:24 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-10 16:45:24 -0700 |
| commit | 30d41bfbfb40bc6615e62eaa17fead79e3083c32 (patch) | |
| tree | b570a428b88e5cde113236c9cb208cdc1045ffb3 /arch/arm/mm/cache-v4wb.S | |
| parent | e38d557896c4213dd0919770feac0f4a8f60151b (diff) | |
| parent | 1356c1948da967bc1d4c663762bfe21dfcec4b2f (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3473/1: Use numbers 0-15 for the VFP double registers
[ARM] 3472/1: Use the D variants of FLDMIA/FSTMIA on ARMv6
[ARM] 3471/1: FTOSI functions should return 0 for NaN
[ARM] 3470/1: Clear the HWCAP bits for the disabled kernel features
[ARM] 3469/1: S3C24XX: clkout missing hclk selector
[ARM] 3468/1: S3C2410: SMDK common include fix
[ARM] 3461/1: ARM: OMAP: Fix clk_get() when using id and name
[ARM] 3460/1: ARM: OMAP: Remove unnecessary nop_release()
[ARM] 3459/1: ixp23xx: fix debug serial macros for big-endian operation
[ARM] Allow decompressor to be built with -ffunction-sections
[ARM] Fix SA110/SA1100 cache flushing
[ARM] ebsa110: Fix incorrect serial port address
[ARM] Fix ebsa110 debug macros
[ARM] Move FLUSH_BASE macros to asm/arch/memory.h
[ARM] Remove unnecessary extra parens in include/asm-arm/memory.h
[ARM] arm's arch_local_page_offset() fix against 2.6.17-rc1
Diffstat (limited to 'arch/arm/mm/cache-v4wb.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wb.S | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 5c4055b62d9..54e3c5bb518 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -10,7 +10,7 @@ #include <linux/config.h> #include <linux/linkage.h> #include <linux/init.h> -#include <asm/hardware.h> +#include <asm/memory.h> #include <asm/page.h> #include "proc-macros.S" @@ -46,6 +46,11 @@ */ #define CACHE_DLIMIT (CACHE_DSIZE * 4) + .data +flush_base: + .long FLUSH_BASE + .text + /* * flush_user_cache_all() * @@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all) mov ip, #0 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache __flush_whole_cache: - mov r0, #FLUSH_BASE - add r1, r0, #CACHE_DSIZE -1: ldr r2, [r0], #32 - cmp r0, r1 + ldr r3, =flush_base + ldr r1, [r3, #0] + eor r1, r1, #CACHE_DSIZE + str r1, [r3, #0] + add r2, r1, #CACHE_DSIZE +1: ldr r3, [r1], #32 + cmp r1, r2 + blo 1b +#ifdef FLUSH_BASE_MINICACHE + add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE + sub r1, r2, #512 @ only 512 bytes +1: ldr r3, [r1], #32 + cmp r1, r2 blo 1b +#endif mcr p15, 0, ip, c7, c10, 4 @ drain write buffer mov pc, lr @@ -82,6 +97,7 @@ __flush_whole_cache: * - flags - vma_area_struct flags describing address space */ ENTRY(v4wb_flush_user_cache_range) + mov ip, #0 sub r3, r1, r0 @ calculate total size tst r2, #VM_EXEC @ executable region? mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |