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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-07 19:08:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-07 19:08:56 +0100 |
| commit | 5a89770daad83df74d77a8d34a1ffaedae565ce9 (patch) | |
| tree | 0d8ef70293a6ef969ba8b7718e59608337643d40 /arch/arm/mm | |
| parent | c46c948260f41af18b277c1eb1895d788d3605dc (diff) | |
| parent | af7c951d76708c61b862463d579d76be757130bf (diff) | |
Merge branches 'pxa-core' and 'pxa-machines' into pxa-all
Conflicts:
arch/arm/mach-pxa/Kconfig
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/mmu.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 25d9a11eb61..a713e40e1f1 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -211,6 +211,12 @@ static struct mem_type mem_types[] = { PMD_SECT_TEX(1), .domain = DOMAIN_IO, }, + [MT_DEVICE_WC] = { /* ioremap_wc */ + .prot_pte = PROT_PTE_DEVICE, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PROT_SECT_DEVICE, + .domain = DOMAIN_IO, + }, [MT_CACHECLEAN] = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, .domain = DOMAIN_KERNEL, @@ -273,6 +279,20 @@ static void __init build_mem_type_table(void) } /* + * On non-Xscale3 ARMv5-and-older systems, use CB=01 + * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3 + * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable + * in xsc3 parlance, Uncached Normal in ARMv6 parlance). + */ + if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) { + mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1); + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); + } else { + mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_BUFFERABLE; + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; + } + + /* * ARMv5 and lower, bit 4 must be set for page tables. * (was: cache "update-able on write" bit on ARM610) * However, Xscale cores require this bit to be cleared. |