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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2006-06-26 16:16:06 -0700
committerTony Lindgren <tony@atomide.com>2006-06-26 16:16:06 -0700
commiteca9e56eb8dfcf2b8b966c1c49e4622196f0586d (patch)
tree09dfd83d3e56f1dfc52475f8e539b86b382d468b /arch/arm/plat-omap/dma.c
parente8cdf7bdf3efbb1e285fd82a86a3f8fae5ae2665 (diff)
ARM: OMAP: DMA transfer parameter configuration fix
Fix for re-using OMAP DMA channel with different transfer parameters. Bits in the CCR register need to be cleaned as well in some cases. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r--arch/arm/plat-omap/dma.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 5dac4230360..aa1cf79f954 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -166,18 +166,24 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
if (cpu_is_omap24xx() && dma_trigger) {
u32 val = OMAP_DMA_CCR_REG(lch);
+ val &= ~(3 << 19);
if (dma_trigger > 63)
val |= 1 << 20;
if (dma_trigger > 31)
val |= 1 << 19;
+ val &= ~(0x1f);
val |= (dma_trigger & 0x1f);
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;
+ else
+ val &= ~(1 << 5);
if (sync_mode & OMAP_DMA_SYNC_BLOCK)
val |= 1 << 18;
+ else
+ val &= ~(1 << 18);
if (src_or_dst_synch)
val |= 1 << 24; /* source synch */