diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2009-05-28 14:16:04 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-05-28 14:16:04 -0700 |
| commit | 44169075e6eaa87bab6a296209d8d0610879b394 (patch) | |
| tree | 4aca7ea61215bb50d647476de30c558859c2f2f3 /arch/arm/plat-omap/include/mach/irqs.h | |
| parent | 7419045016e5002b3ccee72b28e41bf53dca68f2 (diff) | |
ARM: OMAP4: Add minimal support for omap4
This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.
OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/irqs.h')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/irqs.h | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index 7f57ee66f36..5bc331e93cf 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h @@ -4,6 +4,9 @@ * Copyright (C) Greg Lonnon 2001 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -422,6 +425,92 @@ #define INT_34XX_BENCH_MPU_EMUL 3 + +#define IRQ_GIC_START 32 + +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) + +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) + +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) + + /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ #define OMAP_MAX_GPIO_LINES 192 |