diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-05-12 17:26:32 -0600 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-05-12 17:27:10 -0600 |
| commit | 4519c2bf433b97d091635eb51e4ba8ffa1c84d62 (patch) | |
| tree | 0b36fc5e39c6a29005783c74f727c953c75e2198 /arch/arm/plat-omap/include/mach/sram.h | |
| parent | b2abb271a5705bc80478e79d95fc9f3babc2605c (diff) | |
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz. CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations. Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/sram.h')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/sram.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index ab35d622dcf..dca7c16ae90 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif |