diff options
| author | Thara Gopinath <thara@ti.com> | 2009-12-08 16:33:15 -0700 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-11 17:00:42 -0700 |
| commit | 3863c74b512c1afd3ce6b2f81d8dea9f1d860968 (patch) | |
| tree | 1d7d15664c0ae3a71be7949e9c52ca2f79a73811 /arch/arm/plat-omap/include | |
| parent | 18862cbe47e37beba98f22c088fbe6fe029df889 (diff) | |
OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/powerdomain.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 56bb1b9bf2b..0b960051eae 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -42,7 +42,10 @@ /* Powerdomain flags */ #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ - +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits + * in MEM bank 1 position. This is + * true for OMAP3430 + */ /* * Number of memory banks that are power-controllable. On OMAP3430, the |