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authorJarkko Nikula <jhnikula@gmail.com>2009-08-23 12:24:26 +0300
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-08-25 10:20:48 +0100
commit32080af7a612e8c56131d6bdcd268cd9e8b0add1 (patch)
tree8022b8c7cdd0e2efc9f73e5f913cdd913078bd27 /arch/arm
parent9b30050908fad96968497e73b88626056ea33c96 (diff)
ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
Commit ca6e2ce08679c094878d7f39a0349a7db1d13675 is setting up few XCCR and RCCR bits for I2S and DPS_A formats. Part of the bits are already set for all formats and I believe that XDISABLE and RDISABLE bits are format independent. As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup of XDISABLE and RDISABLE to where those cpu's are tested and remove format dependent part for simplicity. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'arch/arm')
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