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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-10-21 18:17:58 +0100
committerBen Dooks <ben-linux@fluff.org>2009-10-26 16:49:46 +0000
commite179ac0f4ea4f1e989fa754bada366f88fd81d27 (patch)
tree0111a980b3822e5ff2ab110f42b415378b3e2291 /arch/arm
parente73486b8c9d8d649dd080eb1b810e5b0c11a955a (diff)
ARM: S3C64XX: Set rate of crystal mux
The current code assumes that the external clock mux will be set to the crystal. Set this up explicitly within the clock API. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 9745852261e..6ffa21eb1b9 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+ /* For now assume the mux always selects the crystal */
+ clk_ext_xtal_mux.parent = xtal_clk;
+
epll = s3c6400_get_epll(xtal);
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));