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| author | Simon Horman <horms@verge.net.au> | 2008-09-10 09:14:52 +1000 |
|---|---|---|
| committer | Simon Horman <horms@verge.net.au> | 2008-09-10 09:14:52 +1000 |
| commit | c051a0a2c9e283c1123ed3ce65e66e41d2ce5e24 (patch) | |
| tree | 1202d018129ca5538cd98b1e4542b239045c1a2d /arch/blackfin/include/asm/cache.h | |
| parent | e9c0ce232e7a36daae1ca08282609d7f0c57c567 (diff) | |
| parent | 28faa979746b2352cd78a376bf9f52db953bda46 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6 into lvs-next-2.6
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 00000000000..023d72133b5 --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |